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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfh,+zvfbfmin -verify-machineinstrs -riscv-v-vector-bits-min=128 \3; RUN: < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs -riscv-v-vector-bits-min=128 \5; RUN: < %s | FileCheck %s6 7define <2 x double> @test_vp_reverse_v2f64_masked(<2 x double> %src, <2 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: test_vp_reverse_v2f64_masked:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma11; CHECK-NEXT: vid.v v9, v0.t12; CHECK-NEXT: addi a0, a0, -113; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t14; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t15; CHECK-NEXT: vmv.v.v v8, v916; CHECK-NEXT: ret17 %dst = call <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double> %src, <2 x i1> %mask, i32 %evl)18 ret <2 x double> %dst19}20 21define <2 x double> @test_vp_reverse_v2f64(<2 x double> %src, i32 zeroext %evl) {22; CHECK-LABEL: test_vp_reverse_v2f64:23; CHECK: # %bb.0:24; CHECK-NEXT: addi a1, a0, -125; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma26; CHECK-NEXT: vid.v v927; CHECK-NEXT: vrsub.vx v10, v9, a128; CHECK-NEXT: vrgather.vv v9, v8, v1029; CHECK-NEXT: vmv.v.v v8, v930; CHECK-NEXT: ret31 32 %dst = call <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double> %src, <2 x i1> splat (i1 1), i32 %evl)33 ret <2 x double> %dst34}35 36define <4 x float> @test_vp_reverse_v4f32_masked(<4 x float> %src, <4 x i1> %mask, i32 zeroext %evl) {37; CHECK-LABEL: test_vp_reverse_v4f32_masked:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma40; CHECK-NEXT: vid.v v9, v0.t41; CHECK-NEXT: addi a0, a0, -142; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t43; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t44; CHECK-NEXT: vmv.v.v v8, v945; CHECK-NEXT: ret46 %dst = call <4 x float> @llvm.experimental.vp.reverse.v4f32(<4 x float> %src, <4 x i1> %mask, i32 %evl)47 ret <4 x float> %dst48}49 50define <4 x float> @test_vp_reverse_v4f32(<4 x float> %src, i32 zeroext %evl) {51; CHECK-LABEL: test_vp_reverse_v4f32:52; CHECK: # %bb.0:53; CHECK-NEXT: addi a1, a0, -154; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma55; CHECK-NEXT: vid.v v956; CHECK-NEXT: vrsub.vx v10, v9, a157; CHECK-NEXT: vrgather.vv v9, v8, v1058; CHECK-NEXT: vmv.v.v v8, v959; CHECK-NEXT: ret60 61 %dst = call <4 x float> @llvm.experimental.vp.reverse.v4f32(<4 x float> %src, <4 x i1> splat (i1 1), i32 %evl)62 ret <4 x float> %dst63}64 65define <4 x half> @test_vp_reverse_v4f16_masked(<4 x half> %src, <4 x i1> %mask, i32 zeroext %evl) {66; CHECK-LABEL: test_vp_reverse_v4f16_masked:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma69; CHECK-NEXT: vid.v v9, v0.t70; CHECK-NEXT: addi a0, a0, -171; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t72; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t73; CHECK-NEXT: vmv1r.v v8, v974; CHECK-NEXT: ret75 %dst = call <4 x half> @llvm.experimental.vp.reverse.v4f16(<4 x half> %src, <4 x i1> %mask, i32 %evl)76 ret <4 x half> %dst77}78 79define <4 x half> @test_vp_reverse_v4f16(<4 x half> %src, i32 zeroext %evl) {80; CHECK-LABEL: test_vp_reverse_v4f16:81; CHECK: # %bb.0:82; CHECK-NEXT: addi a1, a0, -183; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma84; CHECK-NEXT: vid.v v985; CHECK-NEXT: vrsub.vx v10, v9, a186; CHECK-NEXT: vrgather.vv v9, v8, v1087; CHECK-NEXT: vmv1r.v v8, v988; CHECK-NEXT: ret89 90 %dst = call <4 x half> @llvm.experimental.vp.reverse.v4f16(<4 x half> %src, <4 x i1> splat (i1 1), i32 %evl)91 ret <4 x half> %dst92}93 94define <4 x bfloat> @test_vp_reverse_v4bf16_masked(<4 x bfloat> %src, <4 x i1> %mask, i32 zeroext %evl) {95; CHECK-LABEL: test_vp_reverse_v4bf16_masked:96; CHECK: # %bb.0:97; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma98; CHECK-NEXT: vid.v v9, v0.t99; CHECK-NEXT: addi a0, a0, -1100; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t101; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t102; CHECK-NEXT: vmv1r.v v8, v9103; CHECK-NEXT: ret104 %dst = call <4 x bfloat> @llvm.experimental.vp.reverse.v4bf16(<4 x bfloat> %src, <4 x i1> %mask, i32 %evl)105 ret <4 x bfloat> %dst106}107 108define <4 x bfloat> @test_vp_reverse_v4bf16(<4 x bfloat> %src, i32 zeroext %evl) {109; CHECK-LABEL: test_vp_reverse_v4bf16:110; CHECK: # %bb.0:111; CHECK-NEXT: addi a1, a0, -1112; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma113; CHECK-NEXT: vid.v v9114; CHECK-NEXT: vrsub.vx v10, v9, a1115; CHECK-NEXT: vrgather.vv v9, v8, v10116; CHECK-NEXT: vmv1r.v v8, v9117; CHECK-NEXT: ret118 119 %dst = call <4 x bfloat> @llvm.experimental.vp.reverse.v4bf16(<4 x bfloat> %src, <4 x i1> splat (i1 1), i32 %evl)120 ret <4 x bfloat> %dst121}122