123 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 \3; RUN: < %s | FileCheck %s4 5define <2 x i64> @test_vp_reverse_v2i64_masked(<2 x i64> %src, <2 x i1> %mask, i32 zeroext %evl) {6; CHECK-LABEL: test_vp_reverse_v2i64_masked:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma9; CHECK-NEXT: vid.v v9, v0.t10; CHECK-NEXT: addi a0, a0, -111; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t12; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t13; CHECK-NEXT: vmv.v.v v8, v914; CHECK-NEXT: ret15 %dst = call <2 x i64> @llvm.experimental.vp.reverse.v2i64(<2 x i64> %src, <2 x i1> %mask, i32 %evl)16 ret <2 x i64> %dst17}18 19define <2 x i64> @test_vp_reverse_v2i64(<2 x i64> %src, i32 zeroext %evl) {20; CHECK-LABEL: test_vp_reverse_v2i64:21; CHECK: # %bb.0:22; CHECK-NEXT: addi a1, a0, -123; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma24; CHECK-NEXT: vid.v v925; CHECK-NEXT: vrsub.vx v10, v9, a126; CHECK-NEXT: vrgather.vv v9, v8, v1027; CHECK-NEXT: vmv.v.v v8, v928; CHECK-NEXT: ret29 30 %dst = call <2 x i64> @llvm.experimental.vp.reverse.v2i64(<2 x i64> %src, <2 x i1> splat (i1 1), i32 %evl)31 ret <2 x i64> %dst32}33 34define <4 x i32> @test_vp_reverse_v4i32_masked(<4 x i32> %src, <4 x i1> %mask, i32 zeroext %evl) {35; CHECK-LABEL: test_vp_reverse_v4i32_masked:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma38; CHECK-NEXT: vid.v v9, v0.t39; CHECK-NEXT: addi a0, a0, -140; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t41; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t42; CHECK-NEXT: vmv.v.v v8, v943; CHECK-NEXT: ret44 %dst = call <4 x i32> @llvm.experimental.vp.reverse.v4i32(<4 x i32> %src, <4 x i1> %mask, i32 %evl)45 ret <4 x i32> %dst46}47 48define <4 x i32> @test_vp_reverse_v4i32(<4 x i32> %src, i32 zeroext %evl) {49; CHECK-LABEL: test_vp_reverse_v4i32:50; CHECK: # %bb.0:51; CHECK-NEXT: addi a1, a0, -152; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma53; CHECK-NEXT: vid.v v954; CHECK-NEXT: vrsub.vx v10, v9, a155; CHECK-NEXT: vrgather.vv v9, v8, v1056; CHECK-NEXT: vmv.v.v v8, v957; CHECK-NEXT: ret58 59 %dst = call <4 x i32> @llvm.experimental.vp.reverse.v4i32(<4 x i32> %src, <4 x i1> splat (i1 1), i32 %evl)60 ret <4 x i32> %dst61}62 63define <8 x i16> @test_vp_reverse_v8i16_masked(<8 x i16> %src, <8 x i1> %mask, i32 zeroext %evl) {64; CHECK-LABEL: test_vp_reverse_v8i16_masked:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma67; CHECK-NEXT: vid.v v9, v0.t68; CHECK-NEXT: addi a0, a0, -169; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t70; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t71; CHECK-NEXT: vmv.v.v v8, v972; CHECK-NEXT: ret73 %dst = call <8 x i16> @llvm.experimental.vp.reverse.v8i16(<8 x i16> %src, <8 x i1> %mask, i32 %evl)74 ret <8 x i16> %dst75}76 77define <8 x i16> @test_vp_reverse_v8i16(<8 x i16> %src, i32 zeroext %evl) {78; CHECK-LABEL: test_vp_reverse_v8i16:79; CHECK: # %bb.0:80; CHECK-NEXT: addi a1, a0, -181; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma82; CHECK-NEXT: vid.v v983; CHECK-NEXT: vrsub.vx v10, v9, a184; CHECK-NEXT: vrgather.vv v9, v8, v1085; CHECK-NEXT: vmv.v.v v8, v986; CHECK-NEXT: ret87 88 %dst = call <8 x i16> @llvm.experimental.vp.reverse.v8i16(<8 x i16> %src, <8 x i1> splat (i1 1), i32 %evl)89 ret <8 x i16> %dst90}91 92define <16 x i8> @test_vp_reverse_v16i8_masked(<16 x i8> %src, <16 x i1> %mask, i32 zeroext %evl) {93; CHECK-LABEL: test_vp_reverse_v16i8_masked:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma96; CHECK-NEXT: vid.v v10, v0.t97; CHECK-NEXT: addi a0, a0, -198; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t99; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma100; CHECK-NEXT: vrgatherei16.vv v9, v8, v10, v0.t101; CHECK-NEXT: vmv.v.v v8, v9102; CHECK-NEXT: ret103 %dst = call <16 x i8> @llvm.experimental.vp.reverse.v16i8(<16 x i8> %src, <16 x i1> %mask, i32 %evl)104 ret <16 x i8> %dst105}106 107define <16 x i8> @test_vp_reverse_v16i8(<16 x i8> %src, i32 zeroext %evl) {108; CHECK-LABEL: test_vp_reverse_v16i8:109; CHECK: # %bb.0:110; CHECK-NEXT: addi a1, a0, -1111; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma112; CHECK-NEXT: vid.v v10113; CHECK-NEXT: vrsub.vx v10, v10, a1114; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma115; CHECK-NEXT: vrgatherei16.vv v9, v8, v10116; CHECK-NEXT: vmv.v.v v8, v9117; CHECK-NEXT: ret118 119 %dst = call <16 x i8> @llvm.experimental.vp.reverse.v16i8(<16 x i8> %src, <16 x i1> splat (i1 1), i32 %evl)120 ret <16 x i8> %dst121}122 123