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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH_RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH_RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFBFA_RV325; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA,ZVFBFA_RV646 7define <1 x i8> @vp_splat_v1i8(i8 %val, <1 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_splat_v1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vmv.v.x v8, a012; CHECK-NEXT: ret13 %splat = call <1 x i8> @llvm.experimental.vp.splat.v1i8(i8 %val, <1 x i1> %m, i32 %evl)14 ret <1 x i8> %splat15}16 17define <2 x i8> @vp_splat_v2i8(i8 %val, <2 x i1> %m, i32 zeroext %evl) {18; CHECK-LABEL: vp_splat_v2i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma21; CHECK-NEXT: vmv.v.x v8, a022; CHECK-NEXT: ret23 %splat = call <2 x i8> @llvm.experimental.vp.splat.v2i8(i8 %val, <2 x i1> %m, i32 %evl)24 ret <2 x i8> %splat25}26 27define <4 x i8> @vp_splat_v4i8(i8 %val, <4 x i1> %m, i32 zeroext %evl) {28; CHECK-LABEL: vp_splat_v4i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma31; CHECK-NEXT: vmv.v.x v8, a032; CHECK-NEXT: ret33 %splat = call <4 x i8> @llvm.experimental.vp.splat.v4i8(i8 %val, <4 x i1> %m, i32 %evl)34 ret <4 x i8> %splat35}36 37define <8 x i8> @vp_splat_v8i8(i8 %val, <8 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: vp_splat_v8i8:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma41; CHECK-NEXT: vmv.v.x v8, a042; CHECK-NEXT: ret43 %splat = call <8 x i8> @llvm.experimental.vp.splat.v8i8(i8 %val, <8 x i1> %m, i32 %evl)44 ret <8 x i8> %splat45}46 47define <16 x i8> @vp_splat_v16i8(i8 %val, <16 x i1> %m, i32 zeroext %evl) {48; CHECK-LABEL: vp_splat_v16i8:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma51; CHECK-NEXT: vmv.v.x v8, a052; CHECK-NEXT: ret53 %splat = call <16 x i8> @llvm.experimental.vp.splat.v16i8(i8 %val, <16 x i1> %m, i32 %evl)54 ret <16 x i8> %splat55}56 57define <32 x i8> @vp_splat_v32i8(i8 %val, <32 x i1> %m, i32 zeroext %evl) {58; CHECK-LABEL: vp_splat_v32i8:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma61; CHECK-NEXT: vmv.v.x v8, a062; CHECK-NEXT: ret63 %splat = call <32 x i8> @llvm.experimental.vp.splat.v32i8(i8 %val, <32 x i1> %m, i32 %evl)64 ret <32 x i8> %splat65}66 67define <64 x i8> @vp_splat_v64i8(i8 %val, <64 x i1> %m, i32 zeroext %evl) {68; CHECK-LABEL: vp_splat_v64i8:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma71; CHECK-NEXT: vmv.v.x v8, a072; CHECK-NEXT: ret73 %splat = call <64 x i8> @llvm.experimental.vp.splat.v64i8(i8 %val, <64 x i1> %m, i32 %evl)74 ret <64 x i8> %splat75}76 77define <1 x i16> @vp_splat_v1i16(i16 %val, <1 x i1> %m, i32 zeroext %evl) {78; CHECK-LABEL: vp_splat_v1i16:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma81; CHECK-NEXT: vmv.v.x v8, a082; CHECK-NEXT: ret83 %splat = call <1 x i16> @llvm.experimental.vp.splat.v1i16(i16 %val, <1 x i1> %m, i32 %evl)84 ret <1 x i16> %splat85}86 87define <2 x i16> @vp_splat_v2i16(i16 %val, <2 x i1> %m, i32 zeroext %evl) {88; CHECK-LABEL: vp_splat_v2i16:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma91; CHECK-NEXT: vmv.v.x v8, a092; CHECK-NEXT: ret93 %splat = call <2 x i16> @llvm.experimental.vp.splat.v2i16(i16 %val, <2 x i1> %m, i32 %evl)94 ret <2 x i16> %splat95}96 97define <4 x i16> @vp_splat_v4i16(i16 %val, <4 x i1> %m, i32 zeroext %evl) {98; CHECK-LABEL: vp_splat_v4i16:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma101; CHECK-NEXT: vmv.v.x v8, a0102; CHECK-NEXT: ret103 %splat = call <4 x i16> @llvm.experimental.vp.splat.v4i16(i16 %val, <4 x i1> %m, i32 %evl)104 ret <4 x i16> %splat105}106 107define <8 x i16> @vp_splat_v8i16(i16 %val, <8 x i1> %m, i32 zeroext %evl) {108; CHECK-LABEL: vp_splat_v8i16:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma111; CHECK-NEXT: vmv.v.x v8, a0112; CHECK-NEXT: ret113 %splat = call <8 x i16> @llvm.experimental.vp.splat.v8i16(i16 %val, <8 x i1> %m, i32 %evl)114 ret <8 x i16> %splat115}116 117define <16 x i16> @vp_splat_v16i16(i16 %val, <16 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: vp_splat_v16i16:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma121; CHECK-NEXT: vmv.v.x v8, a0122; CHECK-NEXT: ret123 %splat = call <16 x i16> @llvm.experimental.vp.splat.v16i16(i16 %val, <16 x i1> %m, i32 %evl)124 ret <16 x i16> %splat125}126 127define <32 x i16> @vp_splat_v32i16(i16 %val, <32 x i1> %m, i32 zeroext %evl) {128; CHECK-LABEL: vp_splat_v32i16:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma131; CHECK-NEXT: vmv.v.x v8, a0132; CHECK-NEXT: ret133 %splat = call <32 x i16> @llvm.experimental.vp.splat.v32i16(i16 %val, <32 x i1> %m, i32 %evl)134 ret <32 x i16> %splat135}136 137define <1 x i32> @vp_splat_v1i32(i32 %val, <1 x i1> %m, i32 zeroext %evl) {138; CHECK-LABEL: vp_splat_v1i32:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma141; CHECK-NEXT: vmv.v.x v8, a0142; CHECK-NEXT: ret143 %splat = call <1 x i32> @llvm.experimental.vp.splat.v1i32(i32 %val, <1 x i1> %m, i32 %evl)144 ret <1 x i32> %splat145}146 147define <2 x i32> @vp_splat_v2i32(i32 %val, <2 x i1> %m, i32 zeroext %evl) {148; CHECK-LABEL: vp_splat_v2i32:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma151; CHECK-NEXT: vmv.v.x v8, a0152; CHECK-NEXT: ret153 %splat = call <2 x i32> @llvm.experimental.vp.splat.v2i32(i32 %val, <2 x i1> %m, i32 %evl)154 ret <2 x i32> %splat155}156 157define <4 x i32> @vp_splat_v4i32(i32 %val, <4 x i1> %m, i32 zeroext %evl) {158; CHECK-LABEL: vp_splat_v4i32:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma161; CHECK-NEXT: vmv.v.x v8, a0162; CHECK-NEXT: ret163 %splat = call <4 x i32> @llvm.experimental.vp.splat.v4i32(i32 %val, <4 x i1> %m, i32 %evl)164 ret <4 x i32> %splat165}166 167define <8 x i32> @vp_splat_v8i32(i32 %val, <8 x i1> %m, i32 zeroext %evl) {168; CHECK-LABEL: vp_splat_v8i32:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma171; CHECK-NEXT: vmv.v.x v8, a0172; CHECK-NEXT: ret173 %splat = call <8 x i32> @llvm.experimental.vp.splat.v8i32(i32 %val, <8 x i1> %m, i32 %evl)174 ret <8 x i32> %splat175}176 177define <16 x i32> @vp_splat_v16i32(i32 %val, <16 x i1> %m, i32 zeroext %evl) {178; CHECK-LABEL: vp_splat_v16i32:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma181; CHECK-NEXT: vmv.v.x v8, a0182; CHECK-NEXT: ret183 %splat = call <16 x i32> @llvm.experimental.vp.splat.v16i32(i32 %val, <16 x i1> %m, i32 %evl)184 ret <16 x i32> %splat185}186 187define <1 x i64> @vp_splat_v1i64(i64 %val, <1 x i1> %m, i32 zeroext %evl) {188; ZVFH_RV32-LABEL: vp_splat_v1i64:189; ZVFH_RV32: # %bb.0:190; ZVFH_RV32-NEXT: addi sp, sp, -16191; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 16192; ZVFH_RV32-NEXT: sw a0, 8(sp)193; ZVFH_RV32-NEXT: sw a1, 12(sp)194; ZVFH_RV32-NEXT: addi a0, sp, 8195; ZVFH_RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma196; ZVFH_RV32-NEXT: vlse64.v v8, (a0), zero197; ZVFH_RV32-NEXT: addi sp, sp, 16198; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 0199; ZVFH_RV32-NEXT: ret200;201; ZVFH_RV64-LABEL: vp_splat_v1i64:202; ZVFH_RV64: # %bb.0:203; ZVFH_RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma204; ZVFH_RV64-NEXT: vmv.v.x v8, a0205; ZVFH_RV64-NEXT: ret206;207; ZVFBFA_RV32-LABEL: vp_splat_v1i64:208; ZVFBFA_RV32: # %bb.0:209; ZVFBFA_RV32-NEXT: addi sp, sp, -16210; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 16211; ZVFBFA_RV32-NEXT: sw a0, 8(sp)212; ZVFBFA_RV32-NEXT: sw a1, 12(sp)213; ZVFBFA_RV32-NEXT: addi a0, sp, 8214; ZVFBFA_RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma215; ZVFBFA_RV32-NEXT: vlse64.v v8, (a0), zero216; ZVFBFA_RV32-NEXT: addi sp, sp, 16217; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 0218; ZVFBFA_RV32-NEXT: ret219;220; ZVFBFA_RV64-LABEL: vp_splat_v1i64:221; ZVFBFA_RV64: # %bb.0:222; ZVFBFA_RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma223; ZVFBFA_RV64-NEXT: vmv.v.x v8, a0224; ZVFBFA_RV64-NEXT: ret225 %splat = call <1 x i64> @llvm.experimental.vp.splat.v1i64(i64 %val, <1 x i1> %m, i32 %evl)226 ret <1 x i64> %splat227}228 229define <2 x i64> @vp_splat_v2i64(i64 %val, <2 x i1> %m, i32 zeroext %evl) {230; ZVFH_RV32-LABEL: vp_splat_v2i64:231; ZVFH_RV32: # %bb.0:232; ZVFH_RV32-NEXT: addi sp, sp, -16233; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 16234; ZVFH_RV32-NEXT: sw a0, 8(sp)235; ZVFH_RV32-NEXT: sw a1, 12(sp)236; ZVFH_RV32-NEXT: addi a0, sp, 8237; ZVFH_RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma238; ZVFH_RV32-NEXT: vlse64.v v8, (a0), zero239; ZVFH_RV32-NEXT: addi sp, sp, 16240; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 0241; ZVFH_RV32-NEXT: ret242;243; ZVFH_RV64-LABEL: vp_splat_v2i64:244; ZVFH_RV64: # %bb.0:245; ZVFH_RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma246; ZVFH_RV64-NEXT: vmv.v.x v8, a0247; ZVFH_RV64-NEXT: ret248;249; ZVFBFA_RV32-LABEL: vp_splat_v2i64:250; ZVFBFA_RV32: # %bb.0:251; ZVFBFA_RV32-NEXT: addi sp, sp, -16252; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 16253; ZVFBFA_RV32-NEXT: sw a0, 8(sp)254; ZVFBFA_RV32-NEXT: sw a1, 12(sp)255; ZVFBFA_RV32-NEXT: addi a0, sp, 8256; ZVFBFA_RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma257; ZVFBFA_RV32-NEXT: vlse64.v v8, (a0), zero258; ZVFBFA_RV32-NEXT: addi sp, sp, 16259; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 0260; ZVFBFA_RV32-NEXT: ret261;262; ZVFBFA_RV64-LABEL: vp_splat_v2i64:263; ZVFBFA_RV64: # %bb.0:264; ZVFBFA_RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma265; ZVFBFA_RV64-NEXT: vmv.v.x v8, a0266; ZVFBFA_RV64-NEXT: ret267 %splat = call <2 x i64> @llvm.experimental.vp.splat.v2i64(i64 %val, <2 x i1> %m, i32 %evl)268 ret <2 x i64> %splat269}270 271define <4 x i64> @vp_splat_v4i64(i64 %val, <4 x i1> %m, i32 zeroext %evl) {272; ZVFH_RV32-LABEL: vp_splat_v4i64:273; ZVFH_RV32: # %bb.0:274; ZVFH_RV32-NEXT: addi sp, sp, -16275; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 16276; ZVFH_RV32-NEXT: sw a0, 8(sp)277; ZVFH_RV32-NEXT: sw a1, 12(sp)278; ZVFH_RV32-NEXT: addi a0, sp, 8279; ZVFH_RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma280; ZVFH_RV32-NEXT: vlse64.v v8, (a0), zero281; ZVFH_RV32-NEXT: addi sp, sp, 16282; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 0283; ZVFH_RV32-NEXT: ret284;285; ZVFH_RV64-LABEL: vp_splat_v4i64:286; ZVFH_RV64: # %bb.0:287; ZVFH_RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma288; ZVFH_RV64-NEXT: vmv.v.x v8, a0289; ZVFH_RV64-NEXT: ret290;291; ZVFBFA_RV32-LABEL: vp_splat_v4i64:292; ZVFBFA_RV32: # %bb.0:293; ZVFBFA_RV32-NEXT: addi sp, sp, -16294; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 16295; ZVFBFA_RV32-NEXT: sw a0, 8(sp)296; ZVFBFA_RV32-NEXT: sw a1, 12(sp)297; ZVFBFA_RV32-NEXT: addi a0, sp, 8298; ZVFBFA_RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma299; ZVFBFA_RV32-NEXT: vlse64.v v8, (a0), zero300; ZVFBFA_RV32-NEXT: addi sp, sp, 16301; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 0302; ZVFBFA_RV32-NEXT: ret303;304; ZVFBFA_RV64-LABEL: vp_splat_v4i64:305; ZVFBFA_RV64: # %bb.0:306; ZVFBFA_RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma307; ZVFBFA_RV64-NEXT: vmv.v.x v8, a0308; ZVFBFA_RV64-NEXT: ret309 %splat = call <4 x i64> @llvm.experimental.vp.splat.v4i64(i64 %val, <4 x i1> %m, i32 %evl)310 ret <4 x i64> %splat311}312 313define <8 x i64> @vp_splat_v8i64(i64 %val, <8 x i1> %m, i32 zeroext %evl) {314; ZVFH_RV32-LABEL: vp_splat_v8i64:315; ZVFH_RV32: # %bb.0:316; ZVFH_RV32-NEXT: addi sp, sp, -16317; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 16318; ZVFH_RV32-NEXT: sw a0, 8(sp)319; ZVFH_RV32-NEXT: sw a1, 12(sp)320; ZVFH_RV32-NEXT: addi a0, sp, 8321; ZVFH_RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma322; ZVFH_RV32-NEXT: vlse64.v v8, (a0), zero323; ZVFH_RV32-NEXT: addi sp, sp, 16324; ZVFH_RV32-NEXT: .cfi_def_cfa_offset 0325; ZVFH_RV32-NEXT: ret326;327; ZVFH_RV64-LABEL: vp_splat_v8i64:328; ZVFH_RV64: # %bb.0:329; ZVFH_RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma330; ZVFH_RV64-NEXT: vmv.v.x v8, a0331; ZVFH_RV64-NEXT: ret332;333; ZVFBFA_RV32-LABEL: vp_splat_v8i64:334; ZVFBFA_RV32: # %bb.0:335; ZVFBFA_RV32-NEXT: addi sp, sp, -16336; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 16337; ZVFBFA_RV32-NEXT: sw a0, 8(sp)338; ZVFBFA_RV32-NEXT: sw a1, 12(sp)339; ZVFBFA_RV32-NEXT: addi a0, sp, 8340; ZVFBFA_RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma341; ZVFBFA_RV32-NEXT: vlse64.v v8, (a0), zero342; ZVFBFA_RV32-NEXT: addi sp, sp, 16343; ZVFBFA_RV32-NEXT: .cfi_def_cfa_offset 0344; ZVFBFA_RV32-NEXT: ret345;346; ZVFBFA_RV64-LABEL: vp_splat_v8i64:347; ZVFBFA_RV64: # %bb.0:348; ZVFBFA_RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma349; ZVFBFA_RV64-NEXT: vmv.v.x v8, a0350; ZVFBFA_RV64-NEXT: ret351 %splat = call <8 x i64> @llvm.experimental.vp.splat.v8i64(i64 %val, <8 x i1> %m, i32 %evl)352 ret <8 x i64> %splat353}354 355define <1 x bfloat> @vp_splat_v1bf16(bfloat %val, <1 x i1> %m, i32 zeroext %evl) {356; ZVFH-LABEL: vp_splat_v1bf16:357; ZVFH: # %bb.0:358; ZVFH-NEXT: fmv.x.w a1, fa0359; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma360; ZVFH-NEXT: vmv.v.x v8, a1361; ZVFH-NEXT: ret362;363; ZVFBFA-LABEL: vp_splat_v1bf16:364; ZVFBFA: # %bb.0:365; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma366; ZVFBFA-NEXT: vfmv.v.f v8, fa0367; ZVFBFA-NEXT: ret368 %splat = call <1 x bfloat> @llvm.experimental.vp.splat.v1bf16(bfloat %val, <1 x i1> %m, i32 %evl)369 ret <1 x bfloat> %splat370}371 372define <2 x bfloat> @vp_splat_v2bf16(bfloat %val, <2 x i1> %m, i32 zeroext %evl) {373; ZVFH-LABEL: vp_splat_v2bf16:374; ZVFH: # %bb.0:375; ZVFH-NEXT: fmv.x.w a1, fa0376; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma377; ZVFH-NEXT: vmv.v.x v8, a1378; ZVFH-NEXT: ret379;380; ZVFBFA-LABEL: vp_splat_v2bf16:381; ZVFBFA: # %bb.0:382; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma383; ZVFBFA-NEXT: vfmv.v.f v8, fa0384; ZVFBFA-NEXT: ret385 %splat = call <2 x bfloat> @llvm.experimental.vp.splat.v2bf16(bfloat %val, <2 x i1> %m, i32 %evl)386 ret <2 x bfloat> %splat387}388 389define <4 x bfloat> @vp_splat_v4bf16(bfloat %val, <4 x i1> %m, i32 zeroext %evl) {390; ZVFH-LABEL: vp_splat_v4bf16:391; ZVFH: # %bb.0:392; ZVFH-NEXT: fmv.x.w a1, fa0393; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma394; ZVFH-NEXT: vmv.v.x v8, a1395; ZVFH-NEXT: ret396;397; ZVFBFA-LABEL: vp_splat_v4bf16:398; ZVFBFA: # %bb.0:399; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma400; ZVFBFA-NEXT: vfmv.v.f v8, fa0401; ZVFBFA-NEXT: ret402 %splat = call <4 x bfloat> @llvm.experimental.vp.splat.v4bf16(bfloat %val, <4 x i1> %m, i32 %evl)403 ret <4 x bfloat> %splat404}405 406define <8 x bfloat> @vp_splat_v8bf16(bfloat %val, <8 x i1> %m, i32 zeroext %evl) {407; ZVFH-LABEL: vp_splat_v8bf16:408; ZVFH: # %bb.0:409; ZVFH-NEXT: fmv.x.w a1, fa0410; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma411; ZVFH-NEXT: vmv.v.x v8, a1412; ZVFH-NEXT: ret413;414; ZVFBFA-LABEL: vp_splat_v8bf16:415; ZVFBFA: # %bb.0:416; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma417; ZVFBFA-NEXT: vfmv.v.f v8, fa0418; ZVFBFA-NEXT: ret419 %splat = call <8 x bfloat> @llvm.experimental.vp.splat.v8bf16(bfloat %val, <8 x i1> %m, i32 %evl)420 ret <8 x bfloat> %splat421}422 423define <16 x bfloat> @vp_splat_v16bf16(bfloat %val, <16 x i1> %m, i32 zeroext %evl) {424; ZVFH-LABEL: vp_splat_v16bf16:425; ZVFH: # %bb.0:426; ZVFH-NEXT: fmv.x.w a1, fa0427; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma428; ZVFH-NEXT: vmv.v.x v8, a1429; ZVFH-NEXT: ret430;431; ZVFBFA-LABEL: vp_splat_v16bf16:432; ZVFBFA: # %bb.0:433; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma434; ZVFBFA-NEXT: vfmv.v.f v8, fa0435; ZVFBFA-NEXT: ret436 %splat = call <16 x bfloat> @llvm.experimental.vp.splat.v16bf16(bfloat %val, <16 x i1> %m, i32 %evl)437 ret <16 x bfloat> %splat438}439 440define <32 x bfloat> @vp_splat_v32bf16(bfloat %val, <32 x i1> %m, i32 zeroext %evl) {441; ZVFH-LABEL: vp_splat_v32bf16:442; ZVFH: # %bb.0:443; ZVFH-NEXT: fmv.x.w a1, fa0444; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma445; ZVFH-NEXT: vmv.v.x v8, a1446; ZVFH-NEXT: ret447;448; ZVFBFA-LABEL: vp_splat_v32bf16:449; ZVFBFA: # %bb.0:450; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma451; ZVFBFA-NEXT: vfmv.v.f v8, fa0452; ZVFBFA-NEXT: ret453 %splat = call <32 x bfloat> @llvm.experimental.vp.splat.v32bf16(bfloat %val, <32 x i1> %m, i32 %evl)454 ret <32 x bfloat> %splat455}456 457define <1 x half> @vp_splat_v1f16(half %val, <1 x i1> %m, i32 zeroext %evl) {458; CHECK-LABEL: vp_splat_v1f16:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma461; CHECK-NEXT: vfmv.v.f v8, fa0462; CHECK-NEXT: ret463 %splat = call <1 x half> @llvm.experimental.vp.splat.v1f16(half %val, <1 x i1> %m, i32 %evl)464 ret <1 x half> %splat465}466 467define <2 x half> @vp_splat_v2f16(half %val, <2 x i1> %m, i32 zeroext %evl) {468; CHECK-LABEL: vp_splat_v2f16:469; CHECK: # %bb.0:470; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma471; CHECK-NEXT: vfmv.v.f v8, fa0472; CHECK-NEXT: ret473 %splat = call <2 x half> @llvm.experimental.vp.splat.v2f16(half %val, <2 x i1> %m, i32 %evl)474 ret <2 x half> %splat475}476 477define <4 x half> @vp_splat_v4f16(half %val, <4 x i1> %m, i32 zeroext %evl) {478; CHECK-LABEL: vp_splat_v4f16:479; CHECK: # %bb.0:480; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma481; CHECK-NEXT: vfmv.v.f v8, fa0482; CHECK-NEXT: ret483 %splat = call <4 x half> @llvm.experimental.vp.splat.v4f16(half %val, <4 x i1> %m, i32 %evl)484 ret <4 x half> %splat485}486 487define <8 x half> @vp_splat_v8f16(half %val, <8 x i1> %m, i32 zeroext %evl) {488; CHECK-LABEL: vp_splat_v8f16:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma491; CHECK-NEXT: vfmv.v.f v8, fa0492; CHECK-NEXT: ret493 %splat = call <8 x half> @llvm.experimental.vp.splat.v8f16(half %val, <8 x i1> %m, i32 %evl)494 ret <8 x half> %splat495}496 497define <16 x half> @vp_splat_v16f16(half %val, <16 x i1> %m, i32 zeroext %evl) {498; CHECK-LABEL: vp_splat_v16f16:499; CHECK: # %bb.0:500; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma501; CHECK-NEXT: vfmv.v.f v8, fa0502; CHECK-NEXT: ret503 %splat = call <16 x half> @llvm.experimental.vp.splat.v16f16(half %val, <16 x i1> %m, i32 %evl)504 ret <16 x half> %splat505}506 507define <32 x half> @vp_splat_v32f16(half %val, <32 x i1> %m, i32 zeroext %evl) {508; CHECK-LABEL: vp_splat_v32f16:509; CHECK: # %bb.0:510; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma511; CHECK-NEXT: vfmv.v.f v8, fa0512; CHECK-NEXT: ret513 %splat = call <32 x half> @llvm.experimental.vp.splat.v32f16(half %val, <32 x i1> %m, i32 %evl)514 ret <32 x half> %splat515}516 517define <1 x float> @vp_splat_v1f32(float %val, <1 x i1> %m, i32 zeroext %evl) {518; CHECK-LABEL: vp_splat_v1f32:519; CHECK: # %bb.0:520; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma521; CHECK-NEXT: vfmv.v.f v8, fa0522; CHECK-NEXT: ret523 %splat = call <1 x float> @llvm.experimental.vp.splat.v1f32(float %val, <1 x i1> %m, i32 %evl)524 ret <1 x float> %splat525}526 527define <2 x float> @vp_splat_v2f32(float %val, <2 x i1> %m, i32 zeroext %evl) {528; CHECK-LABEL: vp_splat_v2f32:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma531; CHECK-NEXT: vfmv.v.f v8, fa0532; CHECK-NEXT: ret533 %splat = call <2 x float> @llvm.experimental.vp.splat.v2f32(float %val, <2 x i1> %m, i32 %evl)534 ret <2 x float> %splat535}536 537define <4 x float> @vp_splat_v4f32(float %val, <4 x i1> %m, i32 zeroext %evl) {538; CHECK-LABEL: vp_splat_v4f32:539; CHECK: # %bb.0:540; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma541; CHECK-NEXT: vfmv.v.f v8, fa0542; CHECK-NEXT: ret543 %splat = call <4 x float> @llvm.experimental.vp.splat.v4f32(float %val, <4 x i1> %m, i32 %evl)544 ret <4 x float> %splat545}546 547define <8 x float> @vp_splat_v8f32(float %val, <8 x i1> %m, i32 zeroext %evl) {548; CHECK-LABEL: vp_splat_v8f32:549; CHECK: # %bb.0:550; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma551; CHECK-NEXT: vfmv.v.f v8, fa0552; CHECK-NEXT: ret553 %splat = call <8 x float> @llvm.experimental.vp.splat.v8f32(float %val, <8 x i1> %m, i32 %evl)554 ret <8 x float> %splat555}556 557define <16 x float> @vp_splat_v16f32(float %val, <16 x i1> %m, i32 zeroext %evl) {558; CHECK-LABEL: vp_splat_v16f32:559; CHECK: # %bb.0:560; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma561; CHECK-NEXT: vfmv.v.f v8, fa0562; CHECK-NEXT: ret563 %splat = call <16 x float> @llvm.experimental.vp.splat.v16f32(float %val, <16 x i1> %m, i32 %evl)564 ret <16 x float> %splat565}566 567define <1 x double> @vp_splat_v1f64(double %val, <1 x i1> %m, i32 zeroext %evl) {568; CHECK-LABEL: vp_splat_v1f64:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma571; CHECK-NEXT: vfmv.v.f v8, fa0572; CHECK-NEXT: ret573 %splat = call <1 x double> @llvm.experimental.vp.splat.v1f64(double %val, <1 x i1> %m, i32 %evl)574 ret <1 x double> %splat575}576 577define <2 x double> @vp_splat_v2f64(double %val, <2 x i1> %m, i32 zeroext %evl) {578; CHECK-LABEL: vp_splat_v2f64:579; CHECK: # %bb.0:580; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma581; CHECK-NEXT: vfmv.v.f v8, fa0582; CHECK-NEXT: ret583 %splat = call <2 x double> @llvm.experimental.vp.splat.v2f64(double %val, <2 x i1> %m, i32 %evl)584 ret <2 x double> %splat585}586 587define <4 x double> @vp_splat_v4f64(double %val, <4 x i1> %m, i32 zeroext %evl) {588; CHECK-LABEL: vp_splat_v4f64:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma591; CHECK-NEXT: vfmv.v.f v8, fa0592; CHECK-NEXT: ret593 %splat = call <4 x double> @llvm.experimental.vp.splat.v4f64(double %val, <4 x i1> %m, i32 %evl)594 ret <4 x double> %splat595}596 597define <8 x double> @vp_splat_v8f64(double %val, <8 x i1> %m, i32 zeroext %evl) {598; CHECK-LABEL: vp_splat_v8f64:599; CHECK: # %bb.0:600; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma601; CHECK-NEXT: vfmv.v.f v8, fa0602; CHECK-NEXT: ret603 %splat = call <8 x double> @llvm.experimental.vp.splat.v8f64(double %val, <8 x i1> %m, i32 %evl)604 ret <8 x double> %splat605}606 607define <16 x i31> @vp_splat_v16i31(i31 %val, <16 x i1> %m, i32 zeroext %evl) {608; CHECK-LABEL: vp_splat_v16i31:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma611; CHECK-NEXT: vmv.v.x v8, a0612; CHECK-NEXT: ret613 %splat = call <16 x i31> @llvm.experimental.vp.splat.v16i31(i31 %val, <16 x i1> %m, i32 %evl)614 ret <16 x i31> %splat615}616 617define <15 x i32> @vp_splat_v15i32(i32 %val, <15 x i1> %m, i32 zeroext %evl) {618; CHECK-LABEL: vp_splat_v15i32:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma621; CHECK-NEXT: vmv.v.x v8, a0622; CHECK-NEXT: ret623 %splat = call <15 x i32> @llvm.experimental.vp.splat.v15i32(i32 %val, <15 x i1> %m, i32 %evl)624 ret <15 x i32> %splat625}626 627; Split case.628define <32 x i32> @vp_splat_v32i32(i32 %val, <32 x i1> %m, i32 zeroext %evl) {629; CHECK-LABEL: vp_splat_v32i32:630; CHECK: # %bb.0:631; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma632; CHECK-NEXT: vmv.v.x v8, a0633; CHECK-NEXT: ret634 %splat = call <32 x i32> @llvm.experimental.vp.splat.v32i32(i32 %val, <32 x i1> %m, i32 %evl)635 ret <32 x i32> %splat636}637