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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfh,+zvfbfmin -verify-machineinstrs \3; RUN: < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFH4; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfhmin,+zvfbfmin -verify-machineinstrs \5; RUN: < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFHMIN6; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfh,+zvfbfmin,+vl-dependent-latency -verify-machineinstrs \7; RUN: < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFH8; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfhmin,+zvfbfmin,+vl-dependent-latency -verify-machineinstrs \9; RUN: < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFHMIN10 11define <2 x i64> @test_vp_splice_v2i64(<2 x i64> %va, <2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {12; NOVLDEP-LABEL: test_vp_splice_v2i64:13; NOVLDEP: # %bb.0:14; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma15; NOVLDEP-NEXT: vslidedown.vi v8, v8, 116; NOVLDEP-NEXT: addi a0, a0, -117; NOVLDEP-NEXT: vslideup.vx v8, v9, a018; NOVLDEP-NEXT: ret19;20; VLDEP-LABEL: test_vp_splice_v2i64:21; VLDEP: # %bb.0:22; VLDEP-NEXT: addi a0, a0, -123; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma24; VLDEP-NEXT: vslidedown.vi v8, v8, 125; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma26; VLDEP-NEXT: vslideup.vx v8, v9, a027; VLDEP-NEXT: ret28 29 %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 1, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)30 ret <2 x i64> %v31}32 33define <2 x i64> @test_vp_splice_v2i64_negative_offset(<2 x i64> %va, <2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {34; NOVLDEP-LABEL: test_vp_splice_v2i64_negative_offset:35; NOVLDEP: # %bb.0:36; NOVLDEP-NEXT: addi a0, a0, -137; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma38; NOVLDEP-NEXT: vslidedown.vx v8, v8, a039; NOVLDEP-NEXT: vslideup.vi v8, v9, 140; NOVLDEP-NEXT: ret41;42; VLDEP-LABEL: test_vp_splice_v2i64_negative_offset:43; VLDEP: # %bb.0:44; VLDEP-NEXT: addi a0, a0, -145; VLDEP-NEXT: vsetivli zero, 1, e64, m1, ta, ma46; VLDEP-NEXT: vslidedown.vx v8, v8, a047; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma48; VLDEP-NEXT: vslideup.vi v8, v9, 149; VLDEP-NEXT: ret50 51 %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 -1, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)52 ret <2 x i64> %v53}54 55define <2 x i64> @test_vp_splice_v2i64_zero_offset(<2 x i64> %va, <2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {56; CHECK-LABEL: test_vp_splice_v2i64_zero_offset:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma59; CHECK-NEXT: vslideup.vx v8, v9, a060; CHECK-NEXT: ret61 62 %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 0, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)63 ret <2 x i64> %v64}65 66define <2 x i64> @test_vp_splice_v2i64_masked(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {67; NOVLDEP-LABEL: test_vp_splice_v2i64_masked:68; NOVLDEP: # %bb.0:69; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma70; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t71; NOVLDEP-NEXT: addi a0, a0, -172; NOVLDEP-NEXT: vsetvli zero, zero, e64, m1, ta, mu73; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t74; NOVLDEP-NEXT: ret75;76; VLDEP-LABEL: test_vp_splice_v2i64_masked:77; VLDEP: # %bb.0:78; VLDEP-NEXT: addi a0, a0, -179; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma80; VLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t81; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, mu82; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t83; VLDEP-NEXT: ret84 %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 1, <2 x i1> %mask, i32 %evla, i32 %evlb)85 ret <2 x i64> %v86}87 88define <4 x i32> @test_vp_splice_v4i32(<4 x i32> %va, <4 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) {89; NOVLDEP-LABEL: test_vp_splice_v4i32:90; NOVLDEP: # %bb.0:91; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma92; NOVLDEP-NEXT: vslidedown.vi v8, v8, 393; NOVLDEP-NEXT: addi a0, a0, -394; NOVLDEP-NEXT: vslideup.vx v8, v9, a095; NOVLDEP-NEXT: ret96;97; VLDEP-LABEL: test_vp_splice_v4i32:98; VLDEP: # %bb.0:99; VLDEP-NEXT: addi a0, a0, -3100; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma101; VLDEP-NEXT: vslidedown.vi v8, v8, 3102; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma103; VLDEP-NEXT: vslideup.vx v8, v9, a0104; VLDEP-NEXT: ret105 106 %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 3, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb)107 ret <4 x i32> %v108}109 110define <4 x i32> @test_vp_splice_v4i32_negative_offset(<4 x i32> %va, <4 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) {111; NOVLDEP-LABEL: test_vp_splice_v4i32_negative_offset:112; NOVLDEP: # %bb.0:113; NOVLDEP-NEXT: addi a0, a0, -3114; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma115; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0116; NOVLDEP-NEXT: vslideup.vi v8, v9, 3117; NOVLDEP-NEXT: ret118;119; VLDEP-LABEL: test_vp_splice_v4i32_negative_offset:120; VLDEP: # %bb.0:121; VLDEP-NEXT: addi a0, a0, -3122; VLDEP-NEXT: vsetivli zero, 3, e32, m1, ta, ma123; VLDEP-NEXT: vslidedown.vx v8, v8, a0124; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma125; VLDEP-NEXT: vslideup.vi v8, v9, 3126; VLDEP-NEXT: ret127 128 %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 -3, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb)129 ret <4 x i32> %v130}131 132define <4 x i32> @test_vp_splice_v4i32_masked(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {133; NOVLDEP-LABEL: test_vp_splice_v4i32_masked:134; NOVLDEP: # %bb.0:135; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma136; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t137; NOVLDEP-NEXT: addi a0, a0, -3138; NOVLDEP-NEXT: vsetvli zero, zero, e32, m1, ta, mu139; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t140; NOVLDEP-NEXT: ret141;142; VLDEP-LABEL: test_vp_splice_v4i32_masked:143; VLDEP: # %bb.0:144; VLDEP-NEXT: addi a0, a0, -3145; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma146; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t147; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, mu148; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t149; VLDEP-NEXT: ret150 %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 3, <4 x i1> %mask, i32 %evla, i32 %evlb)151 ret <4 x i32> %v152}153 154define <8 x i16> @test_vp_splice_v8i16(<8 x i16> %va, <8 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) {155; NOVLDEP-LABEL: test_vp_splice_v8i16:156; NOVLDEP: # %bb.0:157; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma158; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5159; NOVLDEP-NEXT: addi a0, a0, -5160; NOVLDEP-NEXT: vslideup.vx v8, v9, a0161; NOVLDEP-NEXT: ret162;163; VLDEP-LABEL: test_vp_splice_v8i16:164; VLDEP: # %bb.0:165; VLDEP-NEXT: addi a0, a0, -5166; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma167; VLDEP-NEXT: vslidedown.vi v8, v8, 5168; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma169; VLDEP-NEXT: vslideup.vx v8, v9, a0170; VLDEP-NEXT: ret171 172 %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)173 ret <8 x i16> %v174}175 176define <8 x i16> @test_vp_splice_v8i16_negative_offset(<8 x i16> %va, <8 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) {177; NOVLDEP-LABEL: test_vp_splice_v8i16_negative_offset:178; NOVLDEP: # %bb.0:179; NOVLDEP-NEXT: addi a0, a0, -5180; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma181; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0182; NOVLDEP-NEXT: vslideup.vi v8, v9, 5183; NOVLDEP-NEXT: ret184;185; VLDEP-LABEL: test_vp_splice_v8i16_negative_offset:186; VLDEP: # %bb.0:187; VLDEP-NEXT: addi a0, a0, -5188; VLDEP-NEXT: vsetivli zero, 5, e16, m1, ta, ma189; VLDEP-NEXT: vslidedown.vx v8, v8, a0190; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma191; VLDEP-NEXT: vslideup.vi v8, v9, 5192; VLDEP-NEXT: ret193 194 %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)195 ret <8 x i16> %v196}197 198define <8 x i16> @test_vp_splice_v8i16_masked(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {199; NOVLDEP-LABEL: test_vp_splice_v8i16_masked:200; NOVLDEP: # %bb.0:201; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma202; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t203; NOVLDEP-NEXT: addi a0, a0, -5204; NOVLDEP-NEXT: vsetvli zero, zero, e16, m1, ta, mu205; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t206; NOVLDEP-NEXT: ret207;208; VLDEP-LABEL: test_vp_splice_v8i16_masked:209; VLDEP: # %bb.0:210; VLDEP-NEXT: addi a0, a0, -5211; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma212; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t213; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, mu214; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t215; VLDEP-NEXT: ret216 %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)217 ret <8 x i16> %v218}219 220define <16 x i8> @test_vp_splice_v16i8(<16 x i8> %va, <16 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) {221; NOVLDEP-LABEL: test_vp_splice_v16i8:222; NOVLDEP: # %bb.0:223; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma224; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5225; NOVLDEP-NEXT: addi a0, a0, -5226; NOVLDEP-NEXT: vslideup.vx v8, v9, a0227; NOVLDEP-NEXT: ret228;229; VLDEP-LABEL: test_vp_splice_v16i8:230; VLDEP: # %bb.0:231; VLDEP-NEXT: addi a0, a0, -5232; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma233; VLDEP-NEXT: vslidedown.vi v8, v8, 5234; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma235; VLDEP-NEXT: vslideup.vx v8, v9, a0236; VLDEP-NEXT: ret237 238 %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb)239 ret <16 x i8> %v240}241 242define <16 x i8> @test_vp_splice_v16i8_negative_offset(<16 x i8> %va, <16 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) {243; NOVLDEP-LABEL: test_vp_splice_v16i8_negative_offset:244; NOVLDEP: # %bb.0:245; NOVLDEP-NEXT: addi a0, a0, -5246; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma247; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0248; NOVLDEP-NEXT: vslideup.vi v8, v9, 5249; NOVLDEP-NEXT: ret250;251; VLDEP-LABEL: test_vp_splice_v16i8_negative_offset:252; VLDEP: # %bb.0:253; VLDEP-NEXT: addi a0, a0, -5254; VLDEP-NEXT: vsetivli zero, 5, e8, m1, ta, ma255; VLDEP-NEXT: vslidedown.vx v8, v8, a0256; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma257; VLDEP-NEXT: vslideup.vi v8, v9, 5258; VLDEP-NEXT: ret259 260 %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 -5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb)261 ret <16 x i8> %v262}263 264define <16 x i8> @test_vp_splice_v16i8_masked(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {265; NOVLDEP-LABEL: test_vp_splice_v16i8_masked:266; NOVLDEP: # %bb.0:267; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma268; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t269; NOVLDEP-NEXT: addi a0, a0, -5270; NOVLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, mu271; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t272; NOVLDEP-NEXT: ret273;274; VLDEP-LABEL: test_vp_splice_v16i8_masked:275; VLDEP: # %bb.0:276; VLDEP-NEXT: addi a0, a0, -5277; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma278; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t279; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, mu280; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t281; VLDEP-NEXT: ret282 %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 5, <16 x i1> %mask, i32 %evla, i32 %evlb)283 ret <16 x i8> %v284}285 286define <2 x double> @test_vp_splice_v2f64(<2 x double> %va, <2 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) {287; NOVLDEP-LABEL: test_vp_splice_v2f64:288; NOVLDEP: # %bb.0:289; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma290; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1291; NOVLDEP-NEXT: addi a0, a0, -1292; NOVLDEP-NEXT: vslideup.vx v8, v9, a0293; NOVLDEP-NEXT: ret294;295; VLDEP-LABEL: test_vp_splice_v2f64:296; VLDEP: # %bb.0:297; VLDEP-NEXT: addi a0, a0, -1298; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma299; VLDEP-NEXT: vslidedown.vi v8, v8, 1300; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma301; VLDEP-NEXT: vslideup.vx v8, v9, a0302; VLDEP-NEXT: ret303 304 %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 1, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)305 ret <2 x double> %v306}307 308define <2 x double> @test_vp_splice_v2f64_negative_offset(<2 x double> %va, <2 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) {309; NOVLDEP-LABEL: test_vp_splice_v2f64_negative_offset:310; NOVLDEP: # %bb.0:311; NOVLDEP-NEXT: addi a0, a0, -1312; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma313; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0314; NOVLDEP-NEXT: vslideup.vi v8, v9, 1315; NOVLDEP-NEXT: ret316;317; VLDEP-LABEL: test_vp_splice_v2f64_negative_offset:318; VLDEP: # %bb.0:319; VLDEP-NEXT: addi a0, a0, -1320; VLDEP-NEXT: vsetivli zero, 1, e64, m1, ta, ma321; VLDEP-NEXT: vslidedown.vx v8, v8, a0322; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma323; VLDEP-NEXT: vslideup.vi v8, v9, 1324; VLDEP-NEXT: ret325 326 %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 -1, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb)327 ret <2 x double> %v328}329 330define <2 x double> @test_vp_splice_v2f64_masked(<2 x double> %va, <2 x double> %vb, <2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {331; NOVLDEP-LABEL: test_vp_splice_v2f64_masked:332; NOVLDEP: # %bb.0:333; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma334; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t335; NOVLDEP-NEXT: addi a0, a0, -1336; NOVLDEP-NEXT: vsetvli zero, zero, e64, m1, ta, mu337; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t338; NOVLDEP-NEXT: ret339;340; VLDEP-LABEL: test_vp_splice_v2f64_masked:341; VLDEP: # %bb.0:342; VLDEP-NEXT: addi a0, a0, -1343; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma344; VLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t345; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, mu346; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t347; VLDEP-NEXT: ret348 %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 1, <2 x i1> %mask, i32 %evla, i32 %evlb)349 ret <2 x double> %v350}351 352define <4 x float> @test_vp_splice_v4f32(<4 x float> %va, <4 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) {353; NOVLDEP-LABEL: test_vp_splice_v4f32:354; NOVLDEP: # %bb.0:355; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma356; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3357; NOVLDEP-NEXT: addi a0, a0, -3358; NOVLDEP-NEXT: vslideup.vx v8, v9, a0359; NOVLDEP-NEXT: ret360;361; VLDEP-LABEL: test_vp_splice_v4f32:362; VLDEP: # %bb.0:363; VLDEP-NEXT: addi a0, a0, -3364; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma365; VLDEP-NEXT: vslidedown.vi v8, v8, 3366; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma367; VLDEP-NEXT: vslideup.vx v8, v9, a0368; VLDEP-NEXT: ret369 370 %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 3, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb)371 ret <4 x float> %v372}373 374define <4 x float> @test_vp_splice_v4f32_negative_offset(<4 x float> %va, <4 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) {375; NOVLDEP-LABEL: test_vp_splice_v4f32_negative_offset:376; NOVLDEP: # %bb.0:377; NOVLDEP-NEXT: addi a0, a0, -3378; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma379; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0380; NOVLDEP-NEXT: vslideup.vi v8, v9, 3381; NOVLDEP-NEXT: ret382;383; VLDEP-LABEL: test_vp_splice_v4f32_negative_offset:384; VLDEP: # %bb.0:385; VLDEP-NEXT: addi a0, a0, -3386; VLDEP-NEXT: vsetivli zero, 3, e32, m1, ta, ma387; VLDEP-NEXT: vslidedown.vx v8, v8, a0388; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma389; VLDEP-NEXT: vslideup.vi v8, v9, 3390; VLDEP-NEXT: ret391 392 %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 -3, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb)393 ret <4 x float> %v394}395 396define <4 x float> @test_vp_splice_v4f32_masked(<4 x float> %va, <4 x float> %vb, <4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {397; NOVLDEP-LABEL: test_vp_splice_v4f32_masked:398; NOVLDEP: # %bb.0:399; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma400; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t401; NOVLDEP-NEXT: addi a0, a0, -3402; NOVLDEP-NEXT: vsetvli zero, zero, e32, m1, ta, mu403; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t404; NOVLDEP-NEXT: ret405;406; VLDEP-LABEL: test_vp_splice_v4f32_masked:407; VLDEP: # %bb.0:408; VLDEP-NEXT: addi a0, a0, -3409; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma410; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t411; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, mu412; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t413; VLDEP-NEXT: ret414 %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 3, <4 x i1> %mask, i32 %evla, i32 %evlb)415 ret <4 x float> %v416}417 418define <8 x half> @test_vp_splice_v8f16(<8 x half> %va, <8 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) {419; NOVLDEP-LABEL: test_vp_splice_v8f16:420; NOVLDEP: # %bb.0:421; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma422; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5423; NOVLDEP-NEXT: addi a0, a0, -5424; NOVLDEP-NEXT: vslideup.vx v8, v9, a0425; NOVLDEP-NEXT: ret426;427; VLDEP-LABEL: test_vp_splice_v8f16:428; VLDEP: # %bb.0:429; VLDEP-NEXT: addi a0, a0, -5430; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma431; VLDEP-NEXT: vslidedown.vi v8, v8, 5432; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma433; VLDEP-NEXT: vslideup.vx v8, v9, a0434; VLDEP-NEXT: ret435 436 %v = call <8 x half> @llvm.experimental.vp.splice.v8f16(<8 x half> %va, <8 x half> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)437 ret <8 x half> %v438}439 440define <8 x half> @test_vp_splice_v8f16_negative_offset(<8 x half> %va, <8 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) {441; NOVLDEP-LABEL: test_vp_splice_v8f16_negative_offset:442; NOVLDEP: # %bb.0:443; NOVLDEP-NEXT: addi a0, a0, -5444; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma445; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0446; NOVLDEP-NEXT: vslideup.vi v8, v9, 5447; NOVLDEP-NEXT: ret448;449; VLDEP-LABEL: test_vp_splice_v8f16_negative_offset:450; VLDEP: # %bb.0:451; VLDEP-NEXT: addi a0, a0, -5452; VLDEP-NEXT: vsetivli zero, 5, e16, m1, ta, ma453; VLDEP-NEXT: vslidedown.vx v8, v8, a0454; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma455; VLDEP-NEXT: vslideup.vi v8, v9, 5456; VLDEP-NEXT: ret457 458 %v = call <8 x half> @llvm.experimental.vp.splice.v8f16(<8 x half> %va, <8 x half> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)459 ret <8 x half> %v460}461 462define <8 x half> @test_vp_splice_v8f16_masked(<8 x half> %va, <8 x half> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {463; NOVLDEP-LABEL: test_vp_splice_v8f16_masked:464; NOVLDEP: # %bb.0:465; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma466; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t467; NOVLDEP-NEXT: addi a0, a0, -5468; NOVLDEP-NEXT: vsetvli zero, zero, e16, m1, ta, mu469; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t470; NOVLDEP-NEXT: ret471;472; VLDEP-LABEL: test_vp_splice_v8f16_masked:473; VLDEP: # %bb.0:474; VLDEP-NEXT: addi a0, a0, -5475; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma476; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t477; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, mu478; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t479; VLDEP-NEXT: ret480 %v = call <8 x half> @llvm.experimental.vp.splice.v8f16(<8 x half> %va, <8 x half> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)481 ret <8 x half> %v482}483 484define <4 x i32> @test_vp_splice_v4i32_with_firstelt(i32 %first, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evl) {485; CHECK-LABEL: test_vp_splice_v4i32_with_firstelt:486; CHECK: # %bb.0:487; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma488; CHECK-NEXT: vslide1up.vx v9, v8, a0, v0.t489; CHECK-NEXT: vmv.v.v v8, v9490; CHECK-NEXT: ret491 %va = insertelement <4 x i32> poison, i32 %first, i32 0492 %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)493 ret <4 x i32> %v494}495 496define <4 x i32> @test_vp_splice_v4i32_with_splat_firstelt(i32 %first, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evl) {497; CHECK-LABEL: test_vp_splice_v4i32_with_splat_firstelt:498; CHECK: # %bb.0:499; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma500; CHECK-NEXT: vslide1up.vx v9, v8, a0, v0.t501; CHECK-NEXT: vmv.v.v v8, v9502; CHECK-NEXT: ret503 %ins = insertelement <4 x i32> poison, i32 %first, i32 0504 %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer505 %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %splat, <4 x i32> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)506 ret <4 x i32> %v507}508 509define <4 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <4 x float> %vb, <4 x i1> %mask, i32 zeroext %evl) {510; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:511; CHECK: # %bb.0:512; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma513; CHECK-NEXT: vfslide1up.vf v9, v8, fa0, v0.t514; CHECK-NEXT: vmv.v.v v8, v9515; CHECK-NEXT: ret516 %va = insertelement <4 x float> poison, float %first, i32 0517 %v = call <4 x float> @llvm.experimental.vp.splice.nxv2f32(<4 x float> %va, <4 x float> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)518 ret <4 x float> %v519}520 521define <4 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <4 x half> %vb, <4 x i1> %mask, i32 zeroext %evl) {522; ZVFH-LABEL: test_vp_splice_nxv2f16_with_firstelt:523; ZVFH: # %bb.0:524; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma525; ZVFH-NEXT: vfslide1up.vf v9, v8, fa0, v0.t526; ZVFH-NEXT: vmv1r.v v8, v9527; ZVFH-NEXT: ret528;529; ZVFHMIN-LABEL: test_vp_splice_nxv2f16_with_firstelt:530; ZVFHMIN: # %bb.0:531; ZVFHMIN-NEXT: fmv.x.h a1, fa0532; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma533; ZVFHMIN-NEXT: vslide1up.vx v9, v8, a1, v0.t534; ZVFHMIN-NEXT: vmv1r.v v8, v9535; ZVFHMIN-NEXT: ret536 %va = insertelement <4 x half> poison, half %first, i32 0537 %v = call <4 x half> @llvm.experimental.vp.splice.nxv2f16(<4 x half> %va, <4 x half> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)538 ret <4 x half> %v539}540 541define <8 x bfloat> @test_vp_splice_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {542; NOVLDEP-LABEL: test_vp_splice_v8bf16:543; NOVLDEP: # %bb.0:544; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma545; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5546; NOVLDEP-NEXT: addi a0, a0, -5547; NOVLDEP-NEXT: vslideup.vx v8, v9, a0548; NOVLDEP-NEXT: ret549;550; VLDEP-LABEL: test_vp_splice_v8bf16:551; VLDEP: # %bb.0:552; VLDEP-NEXT: addi a0, a0, -5553; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma554; VLDEP-NEXT: vslidedown.vi v8, v8, 5555; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma556; VLDEP-NEXT: vslideup.vx v8, v9, a0557; VLDEP-NEXT: ret558 559 %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)560 ret <8 x bfloat> %v561}562 563define <8 x bfloat> @test_vp_splice_v8bf16_negative_offset(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {564; NOVLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:565; NOVLDEP: # %bb.0:566; NOVLDEP-NEXT: addi a0, a0, -5567; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma568; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0569; NOVLDEP-NEXT: vslideup.vi v8, v9, 5570; NOVLDEP-NEXT: ret571;572; VLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:573; VLDEP: # %bb.0:574; VLDEP-NEXT: addi a0, a0, -5575; VLDEP-NEXT: vsetivli zero, 5, e16, m1, ta, ma576; VLDEP-NEXT: vslidedown.vx v8, v8, a0577; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma578; VLDEP-NEXT: vslideup.vi v8, v9, 5579; VLDEP-NEXT: ret580 581 %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)582 ret <8 x bfloat> %v583}584 585define <8 x bfloat> @test_vp_splice_v8bf16_masked(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {586; NOVLDEP-LABEL: test_vp_splice_v8bf16_masked:587; NOVLDEP: # %bb.0:588; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma589; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t590; NOVLDEP-NEXT: addi a0, a0, -5591; NOVLDEP-NEXT: vsetvli zero, zero, e16, m1, ta, mu592; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t593; NOVLDEP-NEXT: ret594;595; VLDEP-LABEL: test_vp_splice_v8bf16_masked:596; VLDEP: # %bb.0:597; VLDEP-NEXT: addi a0, a0, -5598; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma599; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t600; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, mu601; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t602; VLDEP-NEXT: ret603 %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)604 ret <8 x bfloat> %v605}606