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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV324; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV646; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV328; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV6410 11define <2 x i8> @vpgather_v2i8(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {12; RV32-LABEL: vpgather_v2i8:13; RV32: # %bb.0:14; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t16; RV32-NEXT: vmv1r.v v8, v917; RV32-NEXT: ret18;19; RV64-LABEL: vpgather_v2i8:20; RV64: # %bb.0:21; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma22; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t23; RV64-NEXT: vmv1r.v v8, v924; RV64-NEXT: ret25 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)26 ret <2 x i8> %v27}28 29define <2 x i16> @vpgather_v2i8_sextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {30; RV32-LABEL: vpgather_v2i8_sextload_v2i16:31; RV32: # %bb.0:32; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma33; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t34; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma35; RV32-NEXT: vsext.vf2 v8, v936; RV32-NEXT: ret37;38; RV64-LABEL: vpgather_v2i8_sextload_v2i16:39; RV64: # %bb.0:40; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma41; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t42; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma43; RV64-NEXT: vsext.vf2 v8, v944; RV64-NEXT: ret45 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)46 %ev = sext <2 x i8> %v to <2 x i16>47 ret <2 x i16> %ev48}49 50define <2 x i16> @vpgather_v2i8_zextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {51; RV32-LABEL: vpgather_v2i8_zextload_v2i16:52; RV32: # %bb.0:53; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma54; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t55; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma56; RV32-NEXT: vzext.vf2 v8, v957; RV32-NEXT: ret58;59; RV64-LABEL: vpgather_v2i8_zextload_v2i16:60; RV64: # %bb.0:61; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma62; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t63; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma64; RV64-NEXT: vzext.vf2 v8, v965; RV64-NEXT: ret66 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)67 %ev = zext <2 x i8> %v to <2 x i16>68 ret <2 x i16> %ev69}70 71define <2 x i32> @vpgather_v2i8_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {72; RV32-LABEL: vpgather_v2i8_sextload_v2i32:73; RV32: # %bb.0:74; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma75; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t76; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma77; RV32-NEXT: vsext.vf4 v8, v978; RV32-NEXT: ret79;80; RV64-LABEL: vpgather_v2i8_sextload_v2i32:81; RV64: # %bb.0:82; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma83; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t84; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma85; RV64-NEXT: vsext.vf4 v8, v986; RV64-NEXT: ret87 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)88 %ev = sext <2 x i8> %v to <2 x i32>89 ret <2 x i32> %ev90}91 92define <2 x i32> @vpgather_v2i8_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {93; RV32-LABEL: vpgather_v2i8_zextload_v2i32:94; RV32: # %bb.0:95; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma96; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t97; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma98; RV32-NEXT: vzext.vf4 v8, v999; RV32-NEXT: ret100;101; RV64-LABEL: vpgather_v2i8_zextload_v2i32:102; RV64: # %bb.0:103; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma104; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t105; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma106; RV64-NEXT: vzext.vf4 v8, v9107; RV64-NEXT: ret108 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)109 %ev = zext <2 x i8> %v to <2 x i32>110 ret <2 x i32> %ev111}112 113define <2 x i64> @vpgather_v2i8_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {114; RV32-LABEL: vpgather_v2i8_sextload_v2i64:115; RV32: # %bb.0:116; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma117; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t118; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma119; RV32-NEXT: vsext.vf8 v8, v9120; RV32-NEXT: ret121;122; RV64-LABEL: vpgather_v2i8_sextload_v2i64:123; RV64: # %bb.0:124; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma125; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t126; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma127; RV64-NEXT: vsext.vf8 v8, v9128; RV64-NEXT: ret129 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)130 %ev = sext <2 x i8> %v to <2 x i64>131 ret <2 x i64> %ev132}133 134define <2 x i64> @vpgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {135; RV32-LABEL: vpgather_v2i8_zextload_v2i64:136; RV32: # %bb.0:137; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma138; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t139; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma140; RV32-NEXT: vzext.vf8 v8, v9141; RV32-NEXT: ret142;143; RV64-LABEL: vpgather_v2i8_zextload_v2i64:144; RV64: # %bb.0:145; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma146; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t147; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma148; RV64-NEXT: vzext.vf8 v8, v9149; RV64-NEXT: ret150 %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)151 %ev = zext <2 x i8> %v to <2 x i64>152 ret <2 x i64> %ev153}154 155define <3 x i8> @vpgather_v3i8(<3 x ptr> %ptrs, <3 x i1> %m, i32 zeroext %evl) {156; RV32-LABEL: vpgather_v3i8:157; RV32: # %bb.0:158; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma159; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t160; RV32-NEXT: vmv1r.v v8, v9161; RV32-NEXT: ret162;163; RV64-LABEL: vpgather_v3i8:164; RV64: # %bb.0:165; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma166; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t167; RV64-NEXT: vmv1r.v v8, v10168; RV64-NEXT: ret169 %v = call <3 x i8> @llvm.vp.gather.v3i8.v3p0(<3 x ptr> %ptrs, <3 x i1> %m, i32 %evl)170 ret <3 x i8> %v171}172 173define <3 x i8> @vpgather_truemask_v3i8(<3 x ptr> %ptrs, i32 zeroext %evl) {174; RV32-LABEL: vpgather_truemask_v3i8:175; RV32: # %bb.0:176; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma177; RV32-NEXT: vluxei32.v v9, (zero), v8178; RV32-NEXT: vmv1r.v v8, v9179; RV32-NEXT: ret180;181; RV64-LABEL: vpgather_truemask_v3i8:182; RV64: # %bb.0:183; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma184; RV64-NEXT: vluxei64.v v10, (zero), v8185; RV64-NEXT: vmv1r.v v8, v10186; RV64-NEXT: ret187 %v = call <3 x i8> @llvm.vp.gather.v3i8.v3p0(<3 x ptr> %ptrs, <3 x i1> splat (i1 1), i32 %evl)188 ret <3 x i8> %v189}190 191define <4 x i8> @vpgather_v4i8(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {192; RV32-LABEL: vpgather_v4i8:193; RV32: # %bb.0:194; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma195; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t196; RV32-NEXT: vmv1r.v v8, v9197; RV32-NEXT: ret198;199; RV64-LABEL: vpgather_v4i8:200; RV64: # %bb.0:201; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma202; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t203; RV64-NEXT: vmv1r.v v8, v10204; RV64-NEXT: ret205 %v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)206 ret <4 x i8> %v207}208 209define <4 x i8> @vpgather_truemask_v4i8(<4 x ptr> %ptrs, i32 zeroext %evl) {210; RV32-LABEL: vpgather_truemask_v4i8:211; RV32: # %bb.0:212; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma213; RV32-NEXT: vluxei32.v v9, (zero), v8214; RV32-NEXT: vmv1r.v v8, v9215; RV32-NEXT: ret216;217; RV64-LABEL: vpgather_truemask_v4i8:218; RV64: # %bb.0:219; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma220; RV64-NEXT: vluxei64.v v10, (zero), v8221; RV64-NEXT: vmv1r.v v8, v10222; RV64-NEXT: ret223 %v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)224 ret <4 x i8> %v225}226 227define <8 x i8> @vpgather_v8i8(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {228; RV32-LABEL: vpgather_v8i8:229; RV32: # %bb.0:230; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, ma231; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t232; RV32-NEXT: vmv1r.v v8, v10233; RV32-NEXT: ret234;235; RV64-LABEL: vpgather_v8i8:236; RV64: # %bb.0:237; RV64-NEXT: vsetvli zero, a0, e8, mf2, ta, ma238; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t239; RV64-NEXT: vmv1r.v v8, v12240; RV64-NEXT: ret241 %v = call <8 x i8> @llvm.vp.gather.v8i8.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)242 ret <8 x i8> %v243}244 245define <8 x i8> @vpgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {246; RV32-LABEL: vpgather_baseidx_v8i8:247; RV32: # %bb.0:248; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma249; RV32-NEXT: vsext.vf4 v10, v8250; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma251; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t252; RV32-NEXT: ret253;254; RV64-LABEL: vpgather_baseidx_v8i8:255; RV64: # %bb.0:256; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma257; RV64-NEXT: vsext.vf8 v12, v8258; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma259; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t260; RV64-NEXT: ret261 %ptrs = getelementptr inbounds i8, ptr %base, <8 x i8> %idxs262 %v = call <8 x i8> @llvm.vp.gather.v8i8.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)263 ret <8 x i8> %v264}265 266define <32 x i8> @vpgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {267; RV32-LABEL: vpgather_baseidx_v32i8:268; RV32: # %bb.0:269; RV32-NEXT: li a2, 32270; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma271; RV32-NEXT: vsext.vf4 v16, v8272; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma273; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t274; RV32-NEXT: ret275;276; RV64-LABEL: vpgather_baseidx_v32i8:277; RV64: # %bb.0:278; RV64-NEXT: li a3, 16279; RV64-NEXT: mv a2, a1280; RV64-NEXT: bltu a1, a3, .LBB13_2281; RV64-NEXT: # %bb.1:282; RV64-NEXT: li a2, 16283; RV64-NEXT: .LBB13_2:284; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma285; RV64-NEXT: vsext.vf8 v16, v8286; RV64-NEXT: vsetvli zero, a2, e8, m1, ta, ma287; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t288; RV64-NEXT: addi a2, a1, -16289; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma290; RV64-NEXT: vslidedown.vi v8, v8, 16291; RV64-NEXT: sltu a1, a1, a2292; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma293; RV64-NEXT: vsext.vf8 v16, v8294; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma295; RV64-NEXT: vslidedown.vi v0, v0, 2296; RV64-NEXT: addi a1, a1, -1297; RV64-NEXT: and a1, a1, a2298; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma299; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t300; RV64-NEXT: li a0, 32301; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma302; RV64-NEXT: vslideup.vi v10, v8, 16303; RV64-NEXT: vmv.v.v v8, v10304; RV64-NEXT: ret305 %ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs306 %v = call <32 x i8> @llvm.vp.gather.v32i8.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)307 ret <32 x i8> %v308}309 310define <2 x i16> @vpgather_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {311; RV32-LABEL: vpgather_v2i16:312; RV32: # %bb.0:313; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma314; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t315; RV32-NEXT: vmv1r.v v8, v9316; RV32-NEXT: ret317;318; RV64-LABEL: vpgather_v2i16:319; RV64: # %bb.0:320; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma321; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t322; RV64-NEXT: vmv1r.v v8, v9323; RV64-NEXT: ret324 %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)325 ret <2 x i16> %v326}327 328define <2 x i32> @vpgather_v2i16_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {329; RV32-LABEL: vpgather_v2i16_sextload_v2i32:330; RV32: # %bb.0:331; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma332; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t333; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma334; RV32-NEXT: vsext.vf2 v8, v9335; RV32-NEXT: ret336;337; RV64-LABEL: vpgather_v2i16_sextload_v2i32:338; RV64: # %bb.0:339; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma340; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t341; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma342; RV64-NEXT: vsext.vf2 v8, v9343; RV64-NEXT: ret344 %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)345 %ev = sext <2 x i16> %v to <2 x i32>346 ret <2 x i32> %ev347}348 349define <2 x i32> @vpgather_v2i16_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {350; RV32-LABEL: vpgather_v2i16_zextload_v2i32:351; RV32: # %bb.0:352; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma353; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t354; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma355; RV32-NEXT: vzext.vf2 v8, v9356; RV32-NEXT: ret357;358; RV64-LABEL: vpgather_v2i16_zextload_v2i32:359; RV64: # %bb.0:360; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma361; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t362; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma363; RV64-NEXT: vzext.vf2 v8, v9364; RV64-NEXT: ret365 %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)366 %ev = zext <2 x i16> %v to <2 x i32>367 ret <2 x i32> %ev368}369 370define <2 x i64> @vpgather_v2i16_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {371; RV32-LABEL: vpgather_v2i16_sextload_v2i64:372; RV32: # %bb.0:373; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma374; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t375; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma376; RV32-NEXT: vsext.vf4 v8, v9377; RV32-NEXT: ret378;379; RV64-LABEL: vpgather_v2i16_sextload_v2i64:380; RV64: # %bb.0:381; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma382; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t383; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma384; RV64-NEXT: vsext.vf4 v8, v9385; RV64-NEXT: ret386 %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)387 %ev = sext <2 x i16> %v to <2 x i64>388 ret <2 x i64> %ev389}390 391define <2 x i64> @vpgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {392; RV32-LABEL: vpgather_v2i16_zextload_v2i64:393; RV32: # %bb.0:394; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma395; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t396; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma397; RV32-NEXT: vzext.vf4 v8, v9398; RV32-NEXT: ret399;400; RV64-LABEL: vpgather_v2i16_zextload_v2i64:401; RV64: # %bb.0:402; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma403; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t404; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma405; RV64-NEXT: vzext.vf4 v8, v9406; RV64-NEXT: ret407 %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)408 %ev = zext <2 x i16> %v to <2 x i64>409 ret <2 x i64> %ev410}411 412define <4 x i16> @vpgather_v4i16(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {413; RV32-LABEL: vpgather_v4i16:414; RV32: # %bb.0:415; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma416; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t417; RV32-NEXT: vmv1r.v v8, v9418; RV32-NEXT: ret419;420; RV64-LABEL: vpgather_v4i16:421; RV64: # %bb.0:422; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma423; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t424; RV64-NEXT: vmv1r.v v8, v10425; RV64-NEXT: ret426 %v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)427 ret <4 x i16> %v428}429 430define <4 x i16> @vpgather_truemask_v4i16(<4 x ptr> %ptrs, i32 zeroext %evl) {431; RV32-LABEL: vpgather_truemask_v4i16:432; RV32: # %bb.0:433; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma434; RV32-NEXT: vluxei32.v v9, (zero), v8435; RV32-NEXT: vmv1r.v v8, v9436; RV32-NEXT: ret437;438; RV64-LABEL: vpgather_truemask_v4i16:439; RV64: # %bb.0:440; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma441; RV64-NEXT: vluxei64.v v10, (zero), v8442; RV64-NEXT: vmv1r.v v8, v10443; RV64-NEXT: ret444 %v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)445 ret <4 x i16> %v446}447 448define <8 x i16> @vpgather_v8i16(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {449; RV32-LABEL: vpgather_v8i16:450; RV32: # %bb.0:451; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma452; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t453; RV32-NEXT: vmv.v.v v8, v10454; RV32-NEXT: ret455;456; RV64-LABEL: vpgather_v8i16:457; RV64: # %bb.0:458; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, ma459; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t460; RV64-NEXT: vmv.v.v v8, v12461; RV64-NEXT: ret462 %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)463 ret <8 x i16> %v464}465 466define <8 x i16> @vpgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {467; RV32-LABEL: vpgather_baseidx_v8i8_v8i16:468; RV32: # %bb.0:469; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma470; RV32-NEXT: vsext.vf4 v10, v8471; RV32-NEXT: vadd.vv v10, v10, v10472; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma473; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t474; RV32-NEXT: ret475;476; RV64-LABEL: vpgather_baseidx_v8i8_v8i16:477; RV64: # %bb.0:478; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma479; RV64-NEXT: vsext.vf8 v12, v8480; RV64-NEXT: vadd.vv v12, v12, v12481; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma482; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t483; RV64-NEXT: ret484 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i8> %idxs485 %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)486 ret <8 x i16> %v487}488 489define <8 x i16> @vpgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {490; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i16:491; RV32: # %bb.0:492; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma493; RV32-NEXT: vsext.vf4 v10, v8494; RV32-NEXT: vadd.vv v10, v10, v10495; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma496; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t497; RV32-NEXT: ret498;499; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i16:500; RV64: # %bb.0:501; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma502; RV64-NEXT: vsext.vf8 v12, v8503; RV64-NEXT: vadd.vv v12, v12, v12504; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma505; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t506; RV64-NEXT: ret507 %eidxs = sext <8 x i8> %idxs to <8 x i16>508 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs509 %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)510 ret <8 x i16> %v511}512 513define <8 x i16> @vpgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {514; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i16:515; RV32: # %bb.0:516; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma517; RV32-NEXT: vwaddu.vv v9, v8, v8518; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma519; RV32-NEXT: vluxei16.v v8, (a0), v9, v0.t520; RV32-NEXT: ret521;522; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i16:523; RV64: # %bb.0:524; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma525; RV64-NEXT: vwaddu.vv v9, v8, v8526; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma527; RV64-NEXT: vluxei16.v v8, (a0), v9, v0.t528; RV64-NEXT: ret529 %eidxs = zext <8 x i8> %idxs to <8 x i16>530 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs531 %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)532 ret <8 x i16> %v533}534 535define <8 x i16> @vpgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {536; RV32-LABEL: vpgather_baseidx_v8i16:537; RV32: # %bb.0:538; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma539; RV32-NEXT: vwadd.vv v10, v8, v8540; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma541; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t542; RV32-NEXT: ret543;544; RV64-LABEL: vpgather_baseidx_v8i16:545; RV64: # %bb.0:546; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma547; RV64-NEXT: vsext.vf4 v12, v8548; RV64-NEXT: vadd.vv v12, v12, v12549; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma550; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t551; RV64-NEXT: ret552 %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %idxs553 %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)554 ret <8 x i16> %v555}556 557define <2 x i32> @vpgather_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {558; RV32-LABEL: vpgather_v2i32:559; RV32: # %bb.0:560; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma561; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t562; RV32-NEXT: ret563;564; RV64-LABEL: vpgather_v2i32:565; RV64: # %bb.0:566; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma567; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t568; RV64-NEXT: vmv1r.v v8, v9569; RV64-NEXT: ret570 %v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)571 ret <2 x i32> %v572}573 574define <2 x i64> @vpgather_v2i32_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {575; RV32-LABEL: vpgather_v2i32_sextload_v2i64:576; RV32: # %bb.0:577; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma578; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t579; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma580; RV32-NEXT: vsext.vf2 v8, v9581; RV32-NEXT: ret582;583; RV64-LABEL: vpgather_v2i32_sextload_v2i64:584; RV64: # %bb.0:585; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma586; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t587; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma588; RV64-NEXT: vsext.vf2 v8, v9589; RV64-NEXT: ret590 %v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)591 %ev = sext <2 x i32> %v to <2 x i64>592 ret <2 x i64> %ev593}594 595define <2 x i64> @vpgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {596; RV32-LABEL: vpgather_v2i32_zextload_v2i64:597; RV32: # %bb.0:598; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma599; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t600; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma601; RV32-NEXT: vzext.vf2 v8, v9602; RV32-NEXT: ret603;604; RV64-LABEL: vpgather_v2i32_zextload_v2i64:605; RV64: # %bb.0:606; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma607; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t608; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma609; RV64-NEXT: vzext.vf2 v8, v9610; RV64-NEXT: ret611 %v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)612 %ev = zext <2 x i32> %v to <2 x i64>613 ret <2 x i64> %ev614}615 616define <4 x i32> @vpgather_v4i32(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {617; RV32-LABEL: vpgather_v4i32:618; RV32: # %bb.0:619; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma620; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t621; RV32-NEXT: ret622;623; RV64-LABEL: vpgather_v4i32:624; RV64: # %bb.0:625; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma626; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t627; RV64-NEXT: vmv.v.v v8, v10628; RV64-NEXT: ret629 %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)630 ret <4 x i32> %v631}632 633define <4 x i32> @vpgather_truemask_v4i32(<4 x ptr> %ptrs, i32 zeroext %evl) {634; RV32-LABEL: vpgather_truemask_v4i32:635; RV32: # %bb.0:636; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma637; RV32-NEXT: vluxei32.v v8, (zero), v8638; RV32-NEXT: ret639;640; RV64-LABEL: vpgather_truemask_v4i32:641; RV64: # %bb.0:642; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma643; RV64-NEXT: vluxei64.v v10, (zero), v8644; RV64-NEXT: vmv.v.v v8, v10645; RV64-NEXT: ret646 %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)647 ret <4 x i32> %v648}649 650define <8 x i32> @vpgather_v8i32(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {651; RV32-LABEL: vpgather_v8i32:652; RV32: # %bb.0:653; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma654; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t655; RV32-NEXT: ret656;657; RV64-LABEL: vpgather_v8i32:658; RV64: # %bb.0:659; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, ma660; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t661; RV64-NEXT: vmv.v.v v8, v12662; RV64-NEXT: ret663 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)664 ret <8 x i32> %v665}666 667define <8 x i32> @vpgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {668; RV32-LABEL: vpgather_baseidx_v8i8_v8i32:669; RV32: # %bb.0:670; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma671; RV32-NEXT: vsext.vf4 v10, v8672; RV32-NEXT: vsll.vi v8, v10, 2673; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma674; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t675; RV32-NEXT: ret676;677; RV64-LABEL: vpgather_baseidx_v8i8_v8i32:678; RV64: # %bb.0:679; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma680; RV64-NEXT: vsext.vf8 v12, v8681; RV64-NEXT: vsll.vi v12, v12, 2682; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma683; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t684; RV64-NEXT: ret685 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i8> %idxs686 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)687 ret <8 x i32> %v688}689 690define <8 x i32> @vpgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {691; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i32:692; RV32: # %bb.0:693; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma694; RV32-NEXT: vsext.vf4 v10, v8695; RV32-NEXT: vsll.vi v8, v10, 2696; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma697; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t698; RV32-NEXT: ret699;700; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i32:701; RV64: # %bb.0:702; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma703; RV64-NEXT: vsext.vf8 v12, v8704; RV64-NEXT: vsll.vi v12, v12, 2705; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma706; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t707; RV64-NEXT: ret708 %eidxs = sext <8 x i8> %idxs to <8 x i32>709 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs710 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)711 ret <8 x i32> %v712}713 714define <8 x i32> @vpgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {715; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i32:716; RV32: # %bb.0:717; RV32-NEXT: li a2, 4718; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma719; RV32-NEXT: vwmulu.vx v10, v8, a2720; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma721; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t722; RV32-NEXT: ret723;724; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i32:725; RV64: # %bb.0:726; RV64-NEXT: li a2, 4727; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma728; RV64-NEXT: vwmulu.vx v10, v8, a2729; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma730; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t731; RV64-NEXT: ret732 %eidxs = zext <8 x i8> %idxs to <8 x i32>733 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs734 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)735 ret <8 x i32> %v736}737 738define <8 x i32> @vpgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {739; RV32-LABEL: vpgather_baseidx_v8i16_v8i32:740; RV32: # %bb.0:741; RV32-NEXT: li a2, 4742; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma743; RV32-NEXT: vwmulsu.vx v10, v8, a2744; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma745; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t746; RV32-NEXT: ret747;748; RV64-LABEL: vpgather_baseidx_v8i16_v8i32:749; RV64: # %bb.0:750; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma751; RV64-NEXT: vsext.vf4 v12, v8752; RV64-NEXT: vsll.vi v12, v12, 2753; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma754; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t755; RV64-NEXT: ret756 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i16> %idxs757 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)758 ret <8 x i32> %v759}760 761define <8 x i32> @vpgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {762; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i32:763; RV32: # %bb.0:764; RV32-NEXT: li a2, 4765; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma766; RV32-NEXT: vwmulsu.vx v10, v8, a2767; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma768; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t769; RV32-NEXT: ret770;771; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i32:772; RV64: # %bb.0:773; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma774; RV64-NEXT: vsext.vf4 v12, v8775; RV64-NEXT: vsll.vi v12, v12, 2776; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma777; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t778; RV64-NEXT: ret779 %eidxs = sext <8 x i16> %idxs to <8 x i32>780 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs781 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)782 ret <8 x i32> %v783}784 785define <8 x i32> @vpgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {786; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i32:787; RV32: # %bb.0:788; RV32-NEXT: li a2, 4789; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma790; RV32-NEXT: vwmulu.vx v10, v8, a2791; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma792; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t793; RV32-NEXT: ret794;795; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i32:796; RV64: # %bb.0:797; RV64-NEXT: li a2, 4798; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma799; RV64-NEXT: vwmulu.vx v10, v8, a2800; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma801; RV64-NEXT: vluxei32.v v8, (a0), v10, v0.t802; RV64-NEXT: ret803 %eidxs = zext <8 x i16> %idxs to <8 x i32>804 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs805 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)806 ret <8 x i32> %v807}808 809define <8 x i32> @vpgather_baseidx_v8i32(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {810; RV32-LABEL: vpgather_baseidx_v8i32:811; RV32: # %bb.0:812; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma813; RV32-NEXT: vsll.vi v8, v8, 2814; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma815; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t816; RV32-NEXT: ret817;818; RV64-LABEL: vpgather_baseidx_v8i32:819; RV64: # %bb.0:820; RV64-NEXT: li a2, 4821; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma822; RV64-NEXT: vwmulsu.vx v12, v8, a2823; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma824; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t825; RV64-NEXT: ret826 %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %idxs827 %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)828 ret <8 x i32> %v829}830 831define <2 x i64> @vpgather_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {832; RV32-LABEL: vpgather_v2i64:833; RV32: # %bb.0:834; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma835; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t836; RV32-NEXT: vmv.v.v v8, v9837; RV32-NEXT: ret838;839; RV64-LABEL: vpgather_v2i64:840; RV64: # %bb.0:841; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma842; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t843; RV64-NEXT: ret844 %v = call <2 x i64> @llvm.vp.gather.v2i64.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)845 ret <2 x i64> %v846}847 848define <4 x i64> @vpgather_v4i64(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {849; RV32-LABEL: vpgather_v4i64:850; RV32: # %bb.0:851; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma852; RV32-NEXT: vmv1r.v v10, v8853; RV32-NEXT: vluxei32.v v8, (zero), v10, v0.t854; RV32-NEXT: ret855;856; RV64-LABEL: vpgather_v4i64:857; RV64: # %bb.0:858; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma859; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t860; RV64-NEXT: ret861 %v = call <4 x i64> @llvm.vp.gather.v4i64.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)862 ret <4 x i64> %v863}864 865define <4 x i64> @vpgather_truemask_v4i64(<4 x ptr> %ptrs, i32 zeroext %evl) {866; RV32-LABEL: vpgather_truemask_v4i64:867; RV32: # %bb.0:868; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma869; RV32-NEXT: vmv1r.v v10, v8870; RV32-NEXT: vluxei32.v v8, (zero), v10871; RV32-NEXT: ret872;873; RV64-LABEL: vpgather_truemask_v4i64:874; RV64: # %bb.0:875; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma876; RV64-NEXT: vluxei64.v v8, (zero), v8877; RV64-NEXT: ret878 %v = call <4 x i64> @llvm.vp.gather.v4i64.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)879 ret <4 x i64> %v880}881 882define <8 x i64> @vpgather_v8i64(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {883; RV32-LABEL: vpgather_v8i64:884; RV32: # %bb.0:885; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma886; RV32-NEXT: vmv2r.v v12, v8887; RV32-NEXT: vluxei32.v v8, (zero), v12, v0.t888; RV32-NEXT: ret889;890; RV64-LABEL: vpgather_v8i64:891; RV64: # %bb.0:892; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma893; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t894; RV64-NEXT: ret895 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)896 ret <8 x i64> %v897}898 899define <8 x i64> @vpgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {900; RV32-LABEL: vpgather_baseidx_v8i8_v8i64:901; RV32: # %bb.0:902; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma903; RV32-NEXT: vsext.vf4 v10, v8904; RV32-NEXT: vsll.vi v12, v10, 3905; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma906; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t907; RV32-NEXT: ret908;909; RV64-LABEL: vpgather_baseidx_v8i8_v8i64:910; RV64: # %bb.0:911; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma912; RV64-NEXT: vsext.vf8 v12, v8913; RV64-NEXT: vsll.vi v8, v12, 3914; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma915; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t916; RV64-NEXT: ret917 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i8> %idxs918 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)919 ret <8 x i64> %v920}921 922define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {923; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i64:924; RV32: # %bb.0:925; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma926; RV32-NEXT: vsext.vf4 v10, v8927; RV32-NEXT: vsll.vi v12, v10, 3928; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma929; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t930; RV32-NEXT: ret931;932; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i64:933; RV64: # %bb.0:934; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma935; RV64-NEXT: vsext.vf8 v12, v8936; RV64-NEXT: vsll.vi v8, v12, 3937; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma938; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t939; RV64-NEXT: ret940 %eidxs = sext <8 x i8> %idxs to <8 x i64>941 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs942 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)943 ret <8 x i64> %v944}945 946define <8 x i64> @vpgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {947; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i64:948; RV32: # %bb.0:949; RV32-NEXT: li a2, 8950; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma951; RV32-NEXT: vwmulu.vx v12, v8, a2952; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma953; RV32-NEXT: vluxei16.v v8, (a0), v12, v0.t954; RV32-NEXT: ret955;956; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i64:957; RV64: # %bb.0:958; RV64-NEXT: li a2, 8959; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma960; RV64-NEXT: vwmulu.vx v12, v8, a2961; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma962; RV64-NEXT: vluxei16.v v8, (a0), v12, v0.t963; RV64-NEXT: ret964 %eidxs = zext <8 x i8> %idxs to <8 x i64>965 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs966 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)967 ret <8 x i64> %v968}969 970define <8 x i64> @vpgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {971; RV32-LABEL: vpgather_baseidx_v8i16_v8i64:972; RV32: # %bb.0:973; RV32-NEXT: li a2, 8974; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma975; RV32-NEXT: vwmulsu.vx v12, v8, a2976; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma977; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t978; RV32-NEXT: ret979;980; RV64-LABEL: vpgather_baseidx_v8i16_v8i64:981; RV64: # %bb.0:982; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma983; RV64-NEXT: vsext.vf4 v12, v8984; RV64-NEXT: vsll.vi v8, v12, 3985; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma986; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t987; RV64-NEXT: ret988 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i16> %idxs989 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)990 ret <8 x i64> %v991}992 993define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {994; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i64:995; RV32: # %bb.0:996; RV32-NEXT: li a2, 8997; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma998; RV32-NEXT: vwmulsu.vx v12, v8, a2999; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1000; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1001; RV32-NEXT: ret1002;1003; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i64:1004; RV64: # %bb.0:1005; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1006; RV64-NEXT: vsext.vf4 v12, v81007; RV64-NEXT: vsll.vi v8, v12, 31008; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1009; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1010; RV64-NEXT: ret1011 %eidxs = sext <8 x i16> %idxs to <8 x i64>1012 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs1013 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1014 ret <8 x i64> %v1015}1016 1017define <8 x i64> @vpgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1018; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i64:1019; RV32: # %bb.0:1020; RV32-NEXT: li a2, 81021; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1022; RV32-NEXT: vwmulu.vx v12, v8, a21023; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1024; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1025; RV32-NEXT: ret1026;1027; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i64:1028; RV64: # %bb.0:1029; RV64-NEXT: li a2, 81030; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma1031; RV64-NEXT: vwmulu.vx v12, v8, a21032; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1033; RV64-NEXT: vluxei32.v v8, (a0), v12, v0.t1034; RV64-NEXT: ret1035 %eidxs = zext <8 x i16> %idxs to <8 x i64>1036 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs1037 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1038 ret <8 x i64> %v1039}1040 1041define <8 x i64> @vpgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1042; RV32-LABEL: vpgather_baseidx_v8i32_v8i64:1043; RV32: # %bb.0:1044; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1045; RV32-NEXT: vsll.vi v12, v8, 31046; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1047; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1048; RV32-NEXT: ret1049;1050; RV64-LABEL: vpgather_baseidx_v8i32_v8i64:1051; RV64: # %bb.0:1052; RV64-NEXT: li a2, 81053; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1054; RV64-NEXT: vwmulsu.vx v12, v8, a21055; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1056; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1057; RV64-NEXT: ret1058 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i32> %idxs1059 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1060 ret <8 x i64> %v1061}1062 1063define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1064; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8i64:1065; RV32: # %bb.0:1066; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1067; RV32-NEXT: vsll.vi v12, v8, 31068; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1069; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1070; RV32-NEXT: ret1071;1072; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8i64:1073; RV64: # %bb.0:1074; RV64-NEXT: li a2, 81075; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1076; RV64-NEXT: vwmulsu.vx v12, v8, a21077; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1078; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1079; RV64-NEXT: ret1080 %eidxs = sext <8 x i32> %idxs to <8 x i64>1081 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs1082 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1083 ret <8 x i64> %v1084}1085 1086define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1087; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8i64:1088; RV32: # %bb.0:1089; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1090; RV32-NEXT: vsll.vi v12, v8, 31091; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1092; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1093; RV32-NEXT: ret1094;1095; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8i64:1096; RV64: # %bb.0:1097; RV64-NEXT: li a2, 81098; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1099; RV64-NEXT: vwmulu.vx v12, v8, a21100; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1101; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1102; RV64-NEXT: ret1103 %eidxs = zext <8 x i32> %idxs to <8 x i64>1104 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %eidxs1105 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1106 ret <8 x i64> %v1107}1108 1109define <8 x i64> @vpgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) {1110; RV32-LABEL: vpgather_baseidx_v8i64:1111; RV32: # %bb.0:1112; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1113; RV32-NEXT: vnsrl.wi v12, v8, 01114; RV32-NEXT: vsll.vi v12, v12, 31115; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1116; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1117; RV32-NEXT: ret1118;1119; RV64-LABEL: vpgather_baseidx_v8i64:1120; RV64: # %bb.0:1121; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1122; RV64-NEXT: vsll.vi v8, v8, 31123; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1124; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1125; RV64-NEXT: ret1126 %ptrs = getelementptr inbounds i64, ptr %base, <8 x i64> %idxs1127 %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1128 ret <8 x i64> %v1129}1130 1131define <2 x bfloat> @vpgather_v2bf16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {1132; RV32-LABEL: vpgather_v2bf16:1133; RV32: # %bb.0:1134; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1135; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t1136; RV32-NEXT: vmv1r.v v8, v91137; RV32-NEXT: ret1138;1139; RV64-LABEL: vpgather_v2bf16:1140; RV64: # %bb.0:1141; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1142; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t1143; RV64-NEXT: vmv1r.v v8, v91144; RV64-NEXT: ret1145 %v = call <2 x bfloat> @llvm.vp.gather.v2bf16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)1146 ret <2 x bfloat> %v1147}1148 1149define <4 x bfloat> @vpgather_v4bf16(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {1150; RV32-LABEL: vpgather_v4bf16:1151; RV32: # %bb.0:1152; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1153; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t1154; RV32-NEXT: vmv1r.v v8, v91155; RV32-NEXT: ret1156;1157; RV64-LABEL: vpgather_v4bf16:1158; RV64: # %bb.0:1159; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1160; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t1161; RV64-NEXT: vmv1r.v v8, v101162; RV64-NEXT: ret1163 %v = call <4 x bfloat> @llvm.vp.gather.v4bf16.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)1164 ret <4 x bfloat> %v1165}1166 1167define <4 x bfloat> @vpgather_truemask_v4bf16(<4 x ptr> %ptrs, i32 zeroext %evl) {1168; RV32-LABEL: vpgather_truemask_v4bf16:1169; RV32: # %bb.0:1170; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1171; RV32-NEXT: vluxei32.v v9, (zero), v81172; RV32-NEXT: vmv1r.v v8, v91173; RV32-NEXT: ret1174;1175; RV64-LABEL: vpgather_truemask_v4bf16:1176; RV64: # %bb.0:1177; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1178; RV64-NEXT: vluxei64.v v10, (zero), v81179; RV64-NEXT: vmv1r.v v8, v101180; RV64-NEXT: ret1181 %v = call <4 x bfloat> @llvm.vp.gather.v4bf16.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)1182 ret <4 x bfloat> %v1183}1184 1185define <8 x bfloat> @vpgather_v8bf16(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {1186; RV32-LABEL: vpgather_v8bf16:1187; RV32: # %bb.0:1188; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma1189; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t1190; RV32-NEXT: vmv.v.v v8, v101191; RV32-NEXT: ret1192;1193; RV64-LABEL: vpgather_v8bf16:1194; RV64: # %bb.0:1195; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, ma1196; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t1197; RV64-NEXT: vmv.v.v v8, v121198; RV64-NEXT: ret1199 %v = call <8 x bfloat> @llvm.vp.gather.v8bf16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1200 ret <8 x bfloat> %v1201}1202 1203define <8 x bfloat> @vpgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1204; RV32-LABEL: vpgather_baseidx_v8i8_v8bf16:1205; RV32: # %bb.0:1206; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1207; RV32-NEXT: vsext.vf4 v10, v81208; RV32-NEXT: vadd.vv v10, v10, v101209; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1210; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1211; RV32-NEXT: ret1212;1213; RV64-LABEL: vpgather_baseidx_v8i8_v8bf16:1214; RV64: # %bb.0:1215; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1216; RV64-NEXT: vsext.vf8 v12, v81217; RV64-NEXT: vadd.vv v12, v12, v121218; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1219; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1220; RV64-NEXT: ret1221 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i8> %idxs1222 %v = call <8 x bfloat> @llvm.vp.gather.v8bf16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1223 ret <8 x bfloat> %v1224}1225 1226define <8 x bfloat> @vpgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1227; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8bf16:1228; RV32: # %bb.0:1229; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1230; RV32-NEXT: vsext.vf4 v10, v81231; RV32-NEXT: vadd.vv v10, v10, v101232; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1233; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1234; RV32-NEXT: ret1235;1236; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8bf16:1237; RV64: # %bb.0:1238; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1239; RV64-NEXT: vsext.vf8 v12, v81240; RV64-NEXT: vadd.vv v12, v12, v121241; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1242; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1243; RV64-NEXT: ret1244 %eidxs = sext <8 x i8> %idxs to <8 x i16>1245 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs1246 %v = call <8 x bfloat> @llvm.vp.gather.v8bf16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1247 ret <8 x bfloat> %v1248}1249 1250define <8 x bfloat> @vpgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1251; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8bf16:1252; RV32: # %bb.0:1253; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1254; RV32-NEXT: vwaddu.vv v9, v8, v81255; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1256; RV32-NEXT: vluxei16.v v8, (a0), v9, v0.t1257; RV32-NEXT: ret1258;1259; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8bf16:1260; RV64: # %bb.0:1261; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1262; RV64-NEXT: vwaddu.vv v9, v8, v81263; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1264; RV64-NEXT: vluxei16.v v8, (a0), v9, v0.t1265; RV64-NEXT: ret1266 %eidxs = zext <8 x i8> %idxs to <8 x i16>1267 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs1268 %v = call <8 x bfloat> @llvm.vp.gather.v8bf16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1269 ret <8 x bfloat> %v1270}1271 1272define <8 x bfloat> @vpgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1273; RV32-LABEL: vpgather_baseidx_v8bf16:1274; RV32: # %bb.0:1275; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1276; RV32-NEXT: vwadd.vv v10, v8, v81277; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1278; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1279; RV32-NEXT: ret1280;1281; RV64-LABEL: vpgather_baseidx_v8bf16:1282; RV64: # %bb.0:1283; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1284; RV64-NEXT: vsext.vf4 v12, v81285; RV64-NEXT: vadd.vv v12, v12, v121286; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1287; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1288; RV64-NEXT: ret1289 %ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %idxs1290 %v = call <8 x bfloat> @llvm.vp.gather.v8bf16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1291 ret <8 x bfloat> %v1292}1293 1294define <2 x half> @vpgather_v2f16(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {1295; RV32-LABEL: vpgather_v2f16:1296; RV32: # %bb.0:1297; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1298; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t1299; RV32-NEXT: vmv1r.v v8, v91300; RV32-NEXT: ret1301;1302; RV64-LABEL: vpgather_v2f16:1303; RV64: # %bb.0:1304; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1305; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t1306; RV64-NEXT: vmv1r.v v8, v91307; RV64-NEXT: ret1308 %v = call <2 x half> @llvm.vp.gather.v2f16.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)1309 ret <2 x half> %v1310}1311 1312define <4 x half> @vpgather_v4f16(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {1313; RV32-LABEL: vpgather_v4f16:1314; RV32: # %bb.0:1315; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1316; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t1317; RV32-NEXT: vmv1r.v v8, v91318; RV32-NEXT: ret1319;1320; RV64-LABEL: vpgather_v4f16:1321; RV64: # %bb.0:1322; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1323; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t1324; RV64-NEXT: vmv1r.v v8, v101325; RV64-NEXT: ret1326 %v = call <4 x half> @llvm.vp.gather.v4f16.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)1327 ret <4 x half> %v1328}1329 1330define <4 x half> @vpgather_truemask_v4f16(<4 x ptr> %ptrs, i32 zeroext %evl) {1331; RV32-LABEL: vpgather_truemask_v4f16:1332; RV32: # %bb.0:1333; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1334; RV32-NEXT: vluxei32.v v9, (zero), v81335; RV32-NEXT: vmv1r.v v8, v91336; RV32-NEXT: ret1337;1338; RV64-LABEL: vpgather_truemask_v4f16:1339; RV64: # %bb.0:1340; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1341; RV64-NEXT: vluxei64.v v10, (zero), v81342; RV64-NEXT: vmv1r.v v8, v101343; RV64-NEXT: ret1344 %v = call <4 x half> @llvm.vp.gather.v4f16.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)1345 ret <4 x half> %v1346}1347 1348define <8 x half> @vpgather_v8f16(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {1349; RV32-LABEL: vpgather_v8f16:1350; RV32: # %bb.0:1351; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma1352; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t1353; RV32-NEXT: vmv.v.v v8, v101354; RV32-NEXT: ret1355;1356; RV64-LABEL: vpgather_v8f16:1357; RV64: # %bb.0:1358; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, ma1359; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t1360; RV64-NEXT: vmv.v.v v8, v121361; RV64-NEXT: ret1362 %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1363 ret <8 x half> %v1364}1365 1366define <8 x half> @vpgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1367; RV32-LABEL: vpgather_baseidx_v8i8_v8f16:1368; RV32: # %bb.0:1369; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1370; RV32-NEXT: vsext.vf4 v10, v81371; RV32-NEXT: vadd.vv v10, v10, v101372; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1373; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1374; RV32-NEXT: ret1375;1376; RV64-LABEL: vpgather_baseidx_v8i8_v8f16:1377; RV64: # %bb.0:1378; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1379; RV64-NEXT: vsext.vf8 v12, v81380; RV64-NEXT: vadd.vv v12, v12, v121381; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1382; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1383; RV64-NEXT: ret1384 %ptrs = getelementptr inbounds half, ptr %base, <8 x i8> %idxs1385 %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1386 ret <8 x half> %v1387}1388 1389define <8 x half> @vpgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1390; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f16:1391; RV32: # %bb.0:1392; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1393; RV32-NEXT: vsext.vf4 v10, v81394; RV32-NEXT: vadd.vv v10, v10, v101395; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1396; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1397; RV32-NEXT: ret1398;1399; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f16:1400; RV64: # %bb.0:1401; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1402; RV64-NEXT: vsext.vf8 v12, v81403; RV64-NEXT: vadd.vv v12, v12, v121404; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1405; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1406; RV64-NEXT: ret1407 %eidxs = sext <8 x i8> %idxs to <8 x i16>1408 %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs1409 %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1410 ret <8 x half> %v1411}1412 1413define <8 x half> @vpgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1414; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f16:1415; RV32: # %bb.0:1416; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1417; RV32-NEXT: vwaddu.vv v9, v8, v81418; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1419; RV32-NEXT: vluxei16.v v8, (a0), v9, v0.t1420; RV32-NEXT: ret1421;1422; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f16:1423; RV64: # %bb.0:1424; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1425; RV64-NEXT: vwaddu.vv v9, v8, v81426; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1427; RV64-NEXT: vluxei16.v v8, (a0), v9, v0.t1428; RV64-NEXT: ret1429 %eidxs = zext <8 x i8> %idxs to <8 x i16>1430 %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs1431 %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1432 ret <8 x half> %v1433}1434 1435define <8 x half> @vpgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1436; RV32-LABEL: vpgather_baseidx_v8f16:1437; RV32: # %bb.0:1438; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1439; RV32-NEXT: vwadd.vv v10, v8, v81440; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1441; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1442; RV32-NEXT: ret1443;1444; RV64-LABEL: vpgather_baseidx_v8f16:1445; RV64: # %bb.0:1446; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1447; RV64-NEXT: vsext.vf4 v12, v81448; RV64-NEXT: vadd.vv v12, v12, v121449; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1450; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1451; RV64-NEXT: ret1452 %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %idxs1453 %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1454 ret <8 x half> %v1455}1456 1457define <2 x float> @vpgather_v2f32(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {1458; RV32-LABEL: vpgather_v2f32:1459; RV32: # %bb.0:1460; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1461; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t1462; RV32-NEXT: ret1463;1464; RV64-LABEL: vpgather_v2f32:1465; RV64: # %bb.0:1466; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1467; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t1468; RV64-NEXT: vmv1r.v v8, v91469; RV64-NEXT: ret1470 %v = call <2 x float> @llvm.vp.gather.v2f32.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)1471 ret <2 x float> %v1472}1473 1474define <4 x float> @vpgather_v4f32(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {1475; RV32-LABEL: vpgather_v4f32:1476; RV32: # %bb.0:1477; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma1478; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t1479; RV32-NEXT: ret1480;1481; RV64-LABEL: vpgather_v4f32:1482; RV64: # %bb.0:1483; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma1484; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t1485; RV64-NEXT: vmv.v.v v8, v101486; RV64-NEXT: ret1487 %v = call <4 x float> @llvm.vp.gather.v4f32.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)1488 ret <4 x float> %v1489}1490 1491define <4 x float> @vpgather_truemask_v4f32(<4 x ptr> %ptrs, i32 zeroext %evl) {1492; RV32-LABEL: vpgather_truemask_v4f32:1493; RV32: # %bb.0:1494; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma1495; RV32-NEXT: vluxei32.v v8, (zero), v81496; RV32-NEXT: ret1497;1498; RV64-LABEL: vpgather_truemask_v4f32:1499; RV64: # %bb.0:1500; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma1501; RV64-NEXT: vluxei64.v v10, (zero), v81502; RV64-NEXT: vmv.v.v v8, v101503; RV64-NEXT: ret1504 %v = call <4 x float> @llvm.vp.gather.v4f32.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)1505 ret <4 x float> %v1506}1507 1508define <8 x float> @vpgather_v8f32(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {1509; RV32-LABEL: vpgather_v8f32:1510; RV32: # %bb.0:1511; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma1512; RV32-NEXT: vluxei32.v v8, (zero), v8, v0.t1513; RV32-NEXT: ret1514;1515; RV64-LABEL: vpgather_v8f32:1516; RV64: # %bb.0:1517; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, ma1518; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t1519; RV64-NEXT: vmv.v.v v8, v121520; RV64-NEXT: ret1521 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1522 ret <8 x float> %v1523}1524 1525define <8 x float> @vpgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1526; RV32-LABEL: vpgather_baseidx_v8i8_v8f32:1527; RV32: # %bb.0:1528; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1529; RV32-NEXT: vsext.vf4 v10, v81530; RV32-NEXT: vsll.vi v8, v10, 21531; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1532; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t1533; RV32-NEXT: ret1534;1535; RV64-LABEL: vpgather_baseidx_v8i8_v8f32:1536; RV64: # %bb.0:1537; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1538; RV64-NEXT: vsext.vf8 v12, v81539; RV64-NEXT: vsll.vi v12, v12, 21540; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1541; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1542; RV64-NEXT: ret1543 %ptrs = getelementptr inbounds float, ptr %base, <8 x i8> %idxs1544 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1545 ret <8 x float> %v1546}1547 1548define <8 x float> @vpgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1549; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f32:1550; RV32: # %bb.0:1551; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1552; RV32-NEXT: vsext.vf4 v10, v81553; RV32-NEXT: vsll.vi v8, v10, 21554; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1555; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t1556; RV32-NEXT: ret1557;1558; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f32:1559; RV64: # %bb.0:1560; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1561; RV64-NEXT: vsext.vf8 v12, v81562; RV64-NEXT: vsll.vi v12, v12, 21563; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1564; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1565; RV64-NEXT: ret1566 %eidxs = sext <8 x i8> %idxs to <8 x i32>1567 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs1568 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1569 ret <8 x float> %v1570}1571 1572define <8 x float> @vpgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1573; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f32:1574; RV32: # %bb.0:1575; RV32-NEXT: li a2, 41576; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1577; RV32-NEXT: vwmulu.vx v10, v8, a21578; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1579; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t1580; RV32-NEXT: ret1581;1582; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f32:1583; RV64: # %bb.0:1584; RV64-NEXT: li a2, 41585; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1586; RV64-NEXT: vwmulu.vx v10, v8, a21587; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1588; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t1589; RV64-NEXT: ret1590 %eidxs = zext <8 x i8> %idxs to <8 x i32>1591 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs1592 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1593 ret <8 x float> %v1594}1595 1596define <8 x float> @vpgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1597; RV32-LABEL: vpgather_baseidx_v8i16_v8f32:1598; RV32: # %bb.0:1599; RV32-NEXT: li a2, 41600; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1601; RV32-NEXT: vwmulsu.vx v10, v8, a21602; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1603; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1604; RV32-NEXT: ret1605;1606; RV64-LABEL: vpgather_baseidx_v8i16_v8f32:1607; RV64: # %bb.0:1608; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1609; RV64-NEXT: vsext.vf4 v12, v81610; RV64-NEXT: vsll.vi v12, v12, 21611; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1612; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1613; RV64-NEXT: ret1614 %ptrs = getelementptr inbounds float, ptr %base, <8 x i16> %idxs1615 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1616 ret <8 x float> %v1617}1618 1619define <8 x float> @vpgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1620; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f32:1621; RV32: # %bb.0:1622; RV32-NEXT: li a2, 41623; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1624; RV32-NEXT: vwmulsu.vx v10, v8, a21625; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1626; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1627; RV32-NEXT: ret1628;1629; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f32:1630; RV64: # %bb.0:1631; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1632; RV64-NEXT: vsext.vf4 v12, v81633; RV64-NEXT: vsll.vi v12, v12, 21634; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1635; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1636; RV64-NEXT: ret1637 %eidxs = sext <8 x i16> %idxs to <8 x i32>1638 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs1639 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1640 ret <8 x float> %v1641}1642 1643define <8 x float> @vpgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1644; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f32:1645; RV32: # %bb.0:1646; RV32-NEXT: li a2, 41647; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1648; RV32-NEXT: vwmulu.vx v10, v8, a21649; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1650; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t1651; RV32-NEXT: ret1652;1653; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f32:1654; RV64: # %bb.0:1655; RV64-NEXT: li a2, 41656; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma1657; RV64-NEXT: vwmulu.vx v10, v8, a21658; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1659; RV64-NEXT: vluxei32.v v8, (a0), v10, v0.t1660; RV64-NEXT: ret1661 %eidxs = zext <8 x i16> %idxs to <8 x i32>1662 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs1663 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1664 ret <8 x float> %v1665}1666 1667define <8 x float> @vpgather_baseidx_v8f32(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1668; RV32-LABEL: vpgather_baseidx_v8f32:1669; RV32: # %bb.0:1670; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1671; RV32-NEXT: vsll.vi v8, v8, 21672; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma1673; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t1674; RV32-NEXT: ret1675;1676; RV64-LABEL: vpgather_baseidx_v8f32:1677; RV64: # %bb.0:1678; RV64-NEXT: li a2, 41679; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1680; RV64-NEXT: vwmulsu.vx v12, v8, a21681; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1682; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1683; RV64-NEXT: ret1684 %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %idxs1685 %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1686 ret <8 x float> %v1687}1688 1689define <2 x double> @vpgather_v2f64(<2 x ptr> %ptrs, <2 x i1> %m, i32 zeroext %evl) {1690; RV32-LABEL: vpgather_v2f64:1691; RV32: # %bb.0:1692; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1693; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t1694; RV32-NEXT: vmv.v.v v8, v91695; RV32-NEXT: ret1696;1697; RV64-LABEL: vpgather_v2f64:1698; RV64: # %bb.0:1699; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1700; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t1701; RV64-NEXT: ret1702 %v = call <2 x double> @llvm.vp.gather.v2f64.v2p0(<2 x ptr> %ptrs, <2 x i1> %m, i32 %evl)1703 ret <2 x double> %v1704}1705 1706define <4 x double> @vpgather_v4f64(<4 x ptr> %ptrs, <4 x i1> %m, i32 zeroext %evl) {1707; RV32-LABEL: vpgather_v4f64:1708; RV32: # %bb.0:1709; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1710; RV32-NEXT: vmv1r.v v10, v81711; RV32-NEXT: vluxei32.v v8, (zero), v10, v0.t1712; RV32-NEXT: ret1713;1714; RV64-LABEL: vpgather_v4f64:1715; RV64: # %bb.0:1716; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1717; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t1718; RV64-NEXT: ret1719 %v = call <4 x double> @llvm.vp.gather.v4f64.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 %evl)1720 ret <4 x double> %v1721}1722 1723define <4 x double> @vpgather_truemask_v4f64(<4 x ptr> %ptrs, i32 zeroext %evl) {1724; RV32-LABEL: vpgather_truemask_v4f64:1725; RV32: # %bb.0:1726; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1727; RV32-NEXT: vmv1r.v v10, v81728; RV32-NEXT: vluxei32.v v8, (zero), v101729; RV32-NEXT: ret1730;1731; RV64-LABEL: vpgather_truemask_v4f64:1732; RV64: # %bb.0:1733; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1734; RV64-NEXT: vluxei64.v v8, (zero), v81735; RV64-NEXT: ret1736 %v = call <4 x double> @llvm.vp.gather.v4f64.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl)1737 ret <4 x double> %v1738}1739 1740define <8 x double> @vpgather_v8f64(<8 x ptr> %ptrs, <8 x i1> %m, i32 zeroext %evl) {1741; RV32-LABEL: vpgather_v8f64:1742; RV32: # %bb.0:1743; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1744; RV32-NEXT: vmv2r.v v12, v81745; RV32-NEXT: vluxei32.v v8, (zero), v12, v0.t1746; RV32-NEXT: ret1747;1748; RV64-LABEL: vpgather_v8f64:1749; RV64: # %bb.0:1750; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma1751; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t1752; RV64-NEXT: ret1753 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1754 ret <8 x double> %v1755}1756 1757define <8 x double> @vpgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1758; RV32-LABEL: vpgather_baseidx_v8i8_v8f64:1759; RV32: # %bb.0:1760; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1761; RV32-NEXT: vsext.vf4 v10, v81762; RV32-NEXT: vsll.vi v12, v10, 31763; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1764; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1765; RV32-NEXT: ret1766;1767; RV64-LABEL: vpgather_baseidx_v8i8_v8f64:1768; RV64: # %bb.0:1769; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1770; RV64-NEXT: vsext.vf8 v12, v81771; RV64-NEXT: vsll.vi v8, v12, 31772; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1773; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1774; RV64-NEXT: ret1775 %ptrs = getelementptr inbounds double, ptr %base, <8 x i8> %idxs1776 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1777 ret <8 x double> %v1778}1779 1780define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1781; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f64:1782; RV32: # %bb.0:1783; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1784; RV32-NEXT: vsext.vf4 v10, v81785; RV32-NEXT: vsll.vi v12, v10, 31786; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1787; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1788; RV32-NEXT: ret1789;1790; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f64:1791; RV64: # %bb.0:1792; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1793; RV64-NEXT: vsext.vf8 v12, v81794; RV64-NEXT: vsll.vi v8, v12, 31795; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1796; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1797; RV64-NEXT: ret1798 %eidxs = sext <8 x i8> %idxs to <8 x i64>1799 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs1800 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1801 ret <8 x double> %v1802}1803 1804define <8 x double> @vpgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x i1> %m, i32 zeroext %evl) {1805; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f64:1806; RV32: # %bb.0:1807; RV32-NEXT: li a2, 81808; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1809; RV32-NEXT: vwmulu.vx v12, v8, a21810; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1811; RV32-NEXT: vluxei16.v v8, (a0), v12, v0.t1812; RV32-NEXT: ret1813;1814; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f64:1815; RV64: # %bb.0:1816; RV64-NEXT: li a2, 81817; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma1818; RV64-NEXT: vwmulu.vx v12, v8, a21819; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1820; RV64-NEXT: vluxei16.v v8, (a0), v12, v0.t1821; RV64-NEXT: ret1822 %eidxs = zext <8 x i8> %idxs to <8 x i64>1823 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs1824 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1825 ret <8 x double> %v1826}1827 1828define <8 x double> @vpgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1829; RV32-LABEL: vpgather_baseidx_v8i16_v8f64:1830; RV32: # %bb.0:1831; RV32-NEXT: li a2, 81832; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1833; RV32-NEXT: vwmulsu.vx v12, v8, a21834; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1835; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1836; RV32-NEXT: ret1837;1838; RV64-LABEL: vpgather_baseidx_v8i16_v8f64:1839; RV64: # %bb.0:1840; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1841; RV64-NEXT: vsext.vf4 v12, v81842; RV64-NEXT: vsll.vi v8, v12, 31843; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1844; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1845; RV64-NEXT: ret1846 %ptrs = getelementptr inbounds double, ptr %base, <8 x i16> %idxs1847 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1848 ret <8 x double> %v1849}1850 1851define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1852; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f64:1853; RV32: # %bb.0:1854; RV32-NEXT: li a2, 81855; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1856; RV32-NEXT: vwmulsu.vx v12, v8, a21857; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1858; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1859; RV32-NEXT: ret1860;1861; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f64:1862; RV64: # %bb.0:1863; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1864; RV64-NEXT: vsext.vf4 v12, v81865; RV64-NEXT: vsll.vi v8, v12, 31866; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1867; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1868; RV64-NEXT: ret1869 %eidxs = sext <8 x i16> %idxs to <8 x i64>1870 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs1871 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1872 ret <8 x double> %v1873}1874 1875define <8 x double> @vpgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8 x i1> %m, i32 zeroext %evl) {1876; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f64:1877; RV32: # %bb.0:1878; RV32-NEXT: li a2, 81879; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma1880; RV32-NEXT: vwmulu.vx v12, v8, a21881; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1882; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1883; RV32-NEXT: ret1884;1885; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f64:1886; RV64: # %bb.0:1887; RV64-NEXT: li a2, 81888; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma1889; RV64-NEXT: vwmulu.vx v12, v8, a21890; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1891; RV64-NEXT: vluxei32.v v8, (a0), v12, v0.t1892; RV64-NEXT: ret1893 %eidxs = zext <8 x i16> %idxs to <8 x i64>1894 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs1895 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1896 ret <8 x double> %v1897}1898 1899define <8 x double> @vpgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1900; RV32-LABEL: vpgather_baseidx_v8i32_v8f64:1901; RV32: # %bb.0:1902; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1903; RV32-NEXT: vsll.vi v12, v8, 31904; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1905; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1906; RV32-NEXT: ret1907;1908; RV64-LABEL: vpgather_baseidx_v8i32_v8f64:1909; RV64: # %bb.0:1910; RV64-NEXT: li a2, 81911; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1912; RV64-NEXT: vwmulsu.vx v12, v8, a21913; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1914; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1915; RV64-NEXT: ret1916 %ptrs = getelementptr inbounds double, ptr %base, <8 x i32> %idxs1917 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1918 ret <8 x double> %v1919}1920 1921define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1922; RV32-LABEL: vpgather_baseidx_sext_v8i32_v8f64:1923; RV32: # %bb.0:1924; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1925; RV32-NEXT: vsll.vi v12, v8, 31926; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1927; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1928; RV32-NEXT: ret1929;1930; RV64-LABEL: vpgather_baseidx_sext_v8i32_v8f64:1931; RV64: # %bb.0:1932; RV64-NEXT: li a2, 81933; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1934; RV64-NEXT: vwmulsu.vx v12, v8, a21935; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1936; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1937; RV64-NEXT: ret1938 %eidxs = sext <8 x i32> %idxs to <8 x i64>1939 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs1940 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1941 ret <8 x double> %v1942}1943 1944define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8 x i1> %m, i32 zeroext %evl) {1945; RV32-LABEL: vpgather_baseidx_zext_v8i32_v8f64:1946; RV32: # %bb.0:1947; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1948; RV32-NEXT: vsll.vi v12, v8, 31949; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1950; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1951; RV32-NEXT: ret1952;1953; RV64-LABEL: vpgather_baseidx_zext_v8i32_v8f64:1954; RV64: # %bb.0:1955; RV64-NEXT: li a2, 81956; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma1957; RV64-NEXT: vwmulu.vx v12, v8, a21958; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1959; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t1960; RV64-NEXT: ret1961 %eidxs = zext <8 x i32> %idxs to <8 x i64>1962 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs1963 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1964 ret <8 x double> %v1965}1966 1967define <8 x double> @vpgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1> %m, i32 zeroext %evl) {1968; RV32-LABEL: vpgather_baseidx_v8f64:1969; RV32: # %bb.0:1970; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1971; RV32-NEXT: vnsrl.wi v12, v8, 01972; RV32-NEXT: vsll.vi v12, v12, 31973; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma1974; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t1975; RV32-NEXT: ret1976;1977; RV64-LABEL: vpgather_baseidx_v8f64:1978; RV64: # %bb.0:1979; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1980; RV64-NEXT: vsll.vi v8, v8, 31981; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1982; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t1983; RV64-NEXT: ret1984 %ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %idxs1985 %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0(<8 x ptr> %ptrs, <8 x i1> %m, i32 %evl)1986 ret <8 x double> %v1987}1988 1989define <32 x double> @vpgather_v32f64(<32 x ptr> %ptrs, <32 x i1> %m, i32 zeroext %evl) {1990; RV32-LABEL: vpgather_v32f64:1991; RV32: # %bb.0:1992; RV32-NEXT: li a2, 161993; RV32-NEXT: mv a1, a01994; RV32-NEXT: bltu a0, a2, .LBB94_21995; RV32-NEXT: # %bb.1:1996; RV32-NEXT: li a1, 161997; RV32-NEXT: .LBB94_2:1998; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma1999; RV32-NEXT: vluxei32.v v24, (zero), v8, v0.t2000; RV32-NEXT: addi a1, a0, -162001; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2002; RV32-NEXT: vslidedown.vi v0, v0, 22003; RV32-NEXT: sltu a0, a0, a12004; RV32-NEXT: addi a0, a0, -12005; RV32-NEXT: and a0, a0, a12006; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2007; RV32-NEXT: vslidedown.vi v8, v8, 162008; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2009; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t2010; RV32-NEXT: vmv8r.v v8, v242011; RV32-NEXT: ret2012;2013; RV64-LABEL: vpgather_v32f64:2014; RV64: # %bb.0:2015; RV64-NEXT: li a2, 162016; RV64-NEXT: mv a1, a02017; RV64-NEXT: bltu a0, a2, .LBB94_22018; RV64-NEXT: # %bb.1:2019; RV64-NEXT: li a1, 162020; RV64-NEXT: .LBB94_2:2021; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2022; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t2023; RV64-NEXT: addi a1, a0, -162024; RV64-NEXT: sltu a0, a0, a12025; RV64-NEXT: addi a0, a0, -12026; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2027; RV64-NEXT: vslidedown.vi v0, v0, 22028; RV64-NEXT: and a0, a0, a12029; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2030; RV64-NEXT: vluxei64.v v16, (zero), v16, v0.t2031; RV64-NEXT: ret2032 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2033 ret <32 x double> %v2034}2035 2036define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {2037; RV32-LABEL: vpgather_baseidx_v32i8_v32f64:2038; RV32: # %bb.0:2039; RV32-NEXT: li a2, 322040; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma2041; RV32-NEXT: vsext.vf4 v16, v82042; RV32-NEXT: li a3, 162043; RV32-NEXT: vsll.vi v16, v16, 32044; RV32-NEXT: mv a2, a12045; RV32-NEXT: bltu a1, a3, .LBB95_22046; RV32-NEXT: # %bb.1:2047; RV32-NEXT: li a2, 162048; RV32-NEXT: .LBB95_2:2049; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2050; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2051; RV32-NEXT: addi a2, a1, -162052; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2053; RV32-NEXT: vslidedown.vi v0, v0, 22054; RV32-NEXT: sltu a1, a1, a22055; RV32-NEXT: addi a1, a1, -12056; RV32-NEXT: and a1, a1, a22057; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2058; RV32-NEXT: vslidedown.vi v24, v16, 162059; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2060; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2061; RV32-NEXT: ret2062;2063; RV64-LABEL: vpgather_baseidx_v32i8_v32f64:2064; RV64: # %bb.0:2065; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma2066; RV64-NEXT: vslidedown.vi v16, v8, 162067; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2068; RV64-NEXT: vsext.vf8 v24, v82069; RV64-NEXT: li a3, 162070; RV64-NEXT: vsext.vf8 v8, v162071; RV64-NEXT: vsll.vi v16, v8, 32072; RV64-NEXT: vsll.vi v8, v24, 32073; RV64-NEXT: mv a2, a12074; RV64-NEXT: bltu a1, a3, .LBB95_22075; RV64-NEXT: # %bb.1:2076; RV64-NEXT: li a2, 162077; RV64-NEXT: .LBB95_2:2078; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2079; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t2080; RV64-NEXT: addi a2, a1, -162081; RV64-NEXT: sltu a1, a1, a22082; RV64-NEXT: addi a1, a1, -12083; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2084; RV64-NEXT: vslidedown.vi v0, v0, 22085; RV64-NEXT: and a1, a1, a22086; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2087; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2088; RV64-NEXT: ret2089 %ptrs = getelementptr inbounds double, ptr %base, <32 x i8> %idxs2090 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2091 ret <32 x double> %v2092}2093 2094define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {2095; RV32-LABEL: vpgather_baseidx_sext_v32i8_v32f64:2096; RV32: # %bb.0:2097; RV32-NEXT: li a2, 322098; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma2099; RV32-NEXT: vsext.vf4 v16, v82100; RV32-NEXT: li a3, 162101; RV32-NEXT: vsll.vi v16, v16, 32102; RV32-NEXT: mv a2, a12103; RV32-NEXT: bltu a1, a3, .LBB96_22104; RV32-NEXT: # %bb.1:2105; RV32-NEXT: li a2, 162106; RV32-NEXT: .LBB96_2:2107; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2108; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2109; RV32-NEXT: addi a2, a1, -162110; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2111; RV32-NEXT: vslidedown.vi v0, v0, 22112; RV32-NEXT: sltu a1, a1, a22113; RV32-NEXT: addi a1, a1, -12114; RV32-NEXT: and a1, a1, a22115; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2116; RV32-NEXT: vslidedown.vi v24, v16, 162117; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2118; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2119; RV32-NEXT: ret2120;2121; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64:2122; RV64: # %bb.0:2123; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2124; RV64-NEXT: vsext.vf8 v24, v82125; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma2126; RV64-NEXT: vslidedown.vi v16, v8, 162127; RV64-NEXT: li a3, 162128; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2129; RV64-NEXT: vsext.vf8 v8, v162130; RV64-NEXT: vsll.vi v16, v8, 32131; RV64-NEXT: vsll.vi v8, v24, 32132; RV64-NEXT: mv a2, a12133; RV64-NEXT: bltu a1, a3, .LBB96_22134; RV64-NEXT: # %bb.1:2135; RV64-NEXT: li a2, 162136; RV64-NEXT: .LBB96_2:2137; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2138; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t2139; RV64-NEXT: addi a2, a1, -162140; RV64-NEXT: sltu a1, a1, a22141; RV64-NEXT: addi a1, a1, -12142; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2143; RV64-NEXT: vslidedown.vi v0, v0, 22144; RV64-NEXT: and a1, a1, a22145; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2146; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2147; RV64-NEXT: ret2148 %eidxs = sext <32 x i8> %idxs to <32 x i64>2149 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs2150 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2151 ret <32 x double> %v2152}2153 2154define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {2155; RV32-LABEL: vpgather_baseidx_zext_v32i8_v32f64:2156; RV32: # %bb.0:2157; RV32-NEXT: li a2, 322158; RV32-NEXT: li a3, 82159; RV32-NEXT: li a4, 162160; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma2161; RV32-NEXT: vwmulu.vx v16, v8, a32162; RV32-NEXT: mv a2, a12163; RV32-NEXT: bltu a1, a4, .LBB97_22164; RV32-NEXT: # %bb.1:2165; RV32-NEXT: li a2, 162166; RV32-NEXT: .LBB97_2:2167; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2168; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t2169; RV32-NEXT: vsetivli zero, 16, e16, m4, ta, ma2170; RV32-NEXT: vslidedown.vi v24, v16, 162171; RV32-NEXT: addi a2, a1, -162172; RV32-NEXT: sltu a1, a1, a22173; RV32-NEXT: addi a1, a1, -12174; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2175; RV32-NEXT: vslidedown.vi v0, v0, 22176; RV32-NEXT: and a1, a1, a22177; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2178; RV32-NEXT: vluxei16.v v16, (a0), v24, v0.t2179; RV32-NEXT: ret2180;2181; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64:2182; RV64: # %bb.0:2183; RV64-NEXT: li a2, 322184; RV64-NEXT: li a3, 82185; RV64-NEXT: li a4, 162186; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma2187; RV64-NEXT: vwmulu.vx v16, v8, a32188; RV64-NEXT: mv a2, a12189; RV64-NEXT: bltu a1, a4, .LBB97_22190; RV64-NEXT: # %bb.1:2191; RV64-NEXT: li a2, 162192; RV64-NEXT: .LBB97_2:2193; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2194; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t2195; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma2196; RV64-NEXT: vslidedown.vi v24, v16, 162197; RV64-NEXT: addi a2, a1, -162198; RV64-NEXT: sltu a1, a1, a22199; RV64-NEXT: addi a1, a1, -12200; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2201; RV64-NEXT: vslidedown.vi v0, v0, 22202; RV64-NEXT: and a1, a1, a22203; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2204; RV64-NEXT: vluxei16.v v16, (a0), v24, v0.t2205; RV64-NEXT: ret2206 %eidxs = zext <32 x i8> %idxs to <32 x i64>2207 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs2208 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2209 ret <32 x double> %v2210}2211 2212define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {2213; RV32-LABEL: vpgather_baseidx_v32i16_v32f64:2214; RV32: # %bb.0:2215; RV32-NEXT: li a2, 322216; RV32-NEXT: li a3, 82217; RV32-NEXT: li a4, 162218; RV32-NEXT: vsetvli zero, a2, e16, m4, ta, ma2219; RV32-NEXT: vwmulsu.vx v16, v8, a32220; RV32-NEXT: mv a2, a12221; RV32-NEXT: bltu a1, a4, .LBB98_22222; RV32-NEXT: # %bb.1:2223; RV32-NEXT: li a2, 162224; RV32-NEXT: .LBB98_2:2225; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2226; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2227; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2228; RV32-NEXT: vslidedown.vi v24, v16, 162229; RV32-NEXT: addi a2, a1, -162230; RV32-NEXT: sltu a1, a1, a22231; RV32-NEXT: addi a1, a1, -12232; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2233; RV32-NEXT: vslidedown.vi v0, v0, 22234; RV32-NEXT: and a1, a1, a22235; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2236; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2237; RV32-NEXT: ret2238;2239; RV64-LABEL: vpgather_baseidx_v32i16_v32f64:2240; RV64: # %bb.0:2241; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma2242; RV64-NEXT: vslidedown.vi v16, v8, 162243; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2244; RV64-NEXT: vsext.vf4 v24, v82245; RV64-NEXT: li a3, 162246; RV64-NEXT: vsext.vf4 v8, v162247; RV64-NEXT: vsll.vi v16, v8, 32248; RV64-NEXT: vsll.vi v8, v24, 32249; RV64-NEXT: mv a2, a12250; RV64-NEXT: bltu a1, a3, .LBB98_22251; RV64-NEXT: # %bb.1:2252; RV64-NEXT: li a2, 162253; RV64-NEXT: .LBB98_2:2254; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2255; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t2256; RV64-NEXT: addi a2, a1, -162257; RV64-NEXT: sltu a1, a1, a22258; RV64-NEXT: addi a1, a1, -12259; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2260; RV64-NEXT: vslidedown.vi v0, v0, 22261; RV64-NEXT: and a1, a1, a22262; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2263; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2264; RV64-NEXT: ret2265 %ptrs = getelementptr inbounds double, ptr %base, <32 x i16> %idxs2266 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2267 ret <32 x double> %v2268}2269 2270define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {2271; RV32-LABEL: vpgather_baseidx_sext_v32i16_v32f64:2272; RV32: # %bb.0:2273; RV32-NEXT: li a2, 322274; RV32-NEXT: li a3, 82275; RV32-NEXT: li a4, 162276; RV32-NEXT: vsetvli zero, a2, e16, m4, ta, ma2277; RV32-NEXT: vwmulsu.vx v16, v8, a32278; RV32-NEXT: mv a2, a12279; RV32-NEXT: bltu a1, a4, .LBB99_22280; RV32-NEXT: # %bb.1:2281; RV32-NEXT: li a2, 162282; RV32-NEXT: .LBB99_2:2283; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2284; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2285; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2286; RV32-NEXT: vslidedown.vi v24, v16, 162287; RV32-NEXT: addi a2, a1, -162288; RV32-NEXT: sltu a1, a1, a22289; RV32-NEXT: addi a1, a1, -12290; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2291; RV32-NEXT: vslidedown.vi v0, v0, 22292; RV32-NEXT: and a1, a1, a22293; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2294; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2295; RV32-NEXT: ret2296;2297; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64:2298; RV64: # %bb.0:2299; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2300; RV64-NEXT: vsext.vf4 v24, v82301; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma2302; RV64-NEXT: vslidedown.vi v16, v8, 162303; RV64-NEXT: li a3, 162304; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2305; RV64-NEXT: vsext.vf4 v8, v162306; RV64-NEXT: vsll.vi v16, v8, 32307; RV64-NEXT: vsll.vi v8, v24, 32308; RV64-NEXT: mv a2, a12309; RV64-NEXT: bltu a1, a3, .LBB99_22310; RV64-NEXT: # %bb.1:2311; RV64-NEXT: li a2, 162312; RV64-NEXT: .LBB99_2:2313; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2314; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t2315; RV64-NEXT: addi a2, a1, -162316; RV64-NEXT: sltu a1, a1, a22317; RV64-NEXT: addi a1, a1, -12318; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2319; RV64-NEXT: vslidedown.vi v0, v0, 22320; RV64-NEXT: and a1, a1, a22321; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2322; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2323; RV64-NEXT: ret2324 %eidxs = sext <32 x i16> %idxs to <32 x i64>2325 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs2326 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2327 ret <32 x double> %v2328}2329 2330define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {2331; RV32-LABEL: vpgather_baseidx_zext_v32i16_v32f64:2332; RV32: # %bb.0:2333; RV32-NEXT: li a2, 322334; RV32-NEXT: li a3, 82335; RV32-NEXT: li a4, 162336; RV32-NEXT: vsetvli zero, a2, e16, m4, ta, ma2337; RV32-NEXT: vwmulu.vx v16, v8, a32338; RV32-NEXT: mv a2, a12339; RV32-NEXT: bltu a1, a4, .LBB100_22340; RV32-NEXT: # %bb.1:2341; RV32-NEXT: li a2, 162342; RV32-NEXT: .LBB100_2:2343; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2344; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2345; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2346; RV32-NEXT: vslidedown.vi v24, v16, 162347; RV32-NEXT: addi a2, a1, -162348; RV32-NEXT: sltu a1, a1, a22349; RV32-NEXT: addi a1, a1, -12350; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2351; RV32-NEXT: vslidedown.vi v0, v0, 22352; RV32-NEXT: and a1, a1, a22353; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2354; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2355; RV32-NEXT: ret2356;2357; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64:2358; RV64: # %bb.0:2359; RV64-NEXT: li a2, 322360; RV64-NEXT: li a3, 82361; RV64-NEXT: li a4, 162362; RV64-NEXT: vsetvli zero, a2, e16, m4, ta, ma2363; RV64-NEXT: vwmulu.vx v16, v8, a32364; RV64-NEXT: mv a2, a12365; RV64-NEXT: bltu a1, a4, .LBB100_22366; RV64-NEXT: # %bb.1:2367; RV64-NEXT: li a2, 162368; RV64-NEXT: .LBB100_2:2369; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2370; RV64-NEXT: vluxei32.v v8, (a0), v16, v0.t2371; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma2372; RV64-NEXT: vslidedown.vi v24, v16, 162373; RV64-NEXT: addi a2, a1, -162374; RV64-NEXT: sltu a1, a1, a22375; RV64-NEXT: addi a1, a1, -12376; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2377; RV64-NEXT: vslidedown.vi v0, v0, 22378; RV64-NEXT: and a1, a1, a22379; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2380; RV64-NEXT: vluxei32.v v16, (a0), v24, v0.t2381; RV64-NEXT: ret2382 %eidxs = zext <32 x i16> %idxs to <32 x i64>2383 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs2384 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2385 ret <32 x double> %v2386}2387 2388define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {2389; RV32-LABEL: vpgather_baseidx_v32i32_v32f64:2390; RV32: # %bb.0:2391; RV32-NEXT: li a2, 322392; RV32-NEXT: li a3, 162393; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma2394; RV32-NEXT: vsll.vi v16, v8, 32395; RV32-NEXT: mv a2, a12396; RV32-NEXT: bltu a1, a3, .LBB101_22397; RV32-NEXT: # %bb.1:2398; RV32-NEXT: li a2, 162399; RV32-NEXT: .LBB101_2:2400; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2401; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2402; RV32-NEXT: addi a2, a1, -162403; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2404; RV32-NEXT: vslidedown.vi v0, v0, 22405; RV32-NEXT: sltu a1, a1, a22406; RV32-NEXT: addi a1, a1, -12407; RV32-NEXT: and a1, a1, a22408; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2409; RV32-NEXT: vslidedown.vi v24, v16, 162410; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2411; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2412; RV32-NEXT: ret2413;2414; RV64-LABEL: vpgather_baseidx_v32i32_v32f64:2415; RV64: # %bb.0:2416; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma2417; RV64-NEXT: vslidedown.vi v24, v8, 162418; RV64-NEXT: li a2, 82419; RV64-NEXT: li a3, 162420; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma2421; RV64-NEXT: vwmulsu.vx v16, v24, a22422; RV64-NEXT: vwmulsu.vx v24, v8, a22423; RV64-NEXT: mv a2, a12424; RV64-NEXT: bltu a1, a3, .LBB101_22425; RV64-NEXT: # %bb.1:2426; RV64-NEXT: li a2, 162427; RV64-NEXT: .LBB101_2:2428; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2429; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t2430; RV64-NEXT: addi a2, a1, -162431; RV64-NEXT: sltu a1, a1, a22432; RV64-NEXT: addi a1, a1, -12433; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2434; RV64-NEXT: vslidedown.vi v0, v0, 22435; RV64-NEXT: and a1, a1, a22436; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2437; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2438; RV64-NEXT: ret2439 %ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs2440 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2441 ret <32 x double> %v2442}2443 2444define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {2445; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64:2446; RV32: # %bb.0:2447; RV32-NEXT: li a2, 322448; RV32-NEXT: li a3, 162449; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma2450; RV32-NEXT: vsll.vi v16, v8, 32451; RV32-NEXT: mv a2, a12452; RV32-NEXT: bltu a1, a3, .LBB102_22453; RV32-NEXT: # %bb.1:2454; RV32-NEXT: li a2, 162455; RV32-NEXT: .LBB102_2:2456; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2457; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2458; RV32-NEXT: addi a2, a1, -162459; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2460; RV32-NEXT: vslidedown.vi v0, v0, 22461; RV32-NEXT: sltu a1, a1, a22462; RV32-NEXT: addi a1, a1, -12463; RV32-NEXT: and a1, a1, a22464; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2465; RV32-NEXT: vslidedown.vi v24, v16, 162466; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2467; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2468; RV32-NEXT: ret2469;2470; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:2471; RV64: # %bb.0:2472; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma2473; RV64-NEXT: vslidedown.vi v24, v8, 162474; RV64-NEXT: li a2, 82475; RV64-NEXT: li a3, 162476; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma2477; RV64-NEXT: vwmulsu.vx v16, v24, a22478; RV64-NEXT: vwmulsu.vx v24, v8, a22479; RV64-NEXT: mv a2, a12480; RV64-NEXT: bltu a1, a3, .LBB102_22481; RV64-NEXT: # %bb.1:2482; RV64-NEXT: li a2, 162483; RV64-NEXT: .LBB102_2:2484; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2485; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t2486; RV64-NEXT: addi a2, a1, -162487; RV64-NEXT: sltu a1, a1, a22488; RV64-NEXT: addi a1, a1, -12489; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2490; RV64-NEXT: vslidedown.vi v0, v0, 22491; RV64-NEXT: and a1, a1, a22492; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2493; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2494; RV64-NEXT: ret2495 %eidxs = sext <32 x i32> %idxs to <32 x i64>2496 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs2497 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2498 ret <32 x double> %v2499}2500 2501define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {2502; RV32-LABEL: vpgather_baseidx_zext_v32i32_v32f64:2503; RV32: # %bb.0:2504; RV32-NEXT: li a2, 322505; RV32-NEXT: li a3, 162506; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma2507; RV32-NEXT: vsll.vi v16, v8, 32508; RV32-NEXT: mv a2, a12509; RV32-NEXT: bltu a1, a3, .LBB103_22510; RV32-NEXT: # %bb.1:2511; RV32-NEXT: li a2, 162512; RV32-NEXT: .LBB103_2:2513; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2514; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2515; RV32-NEXT: addi a2, a1, -162516; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2517; RV32-NEXT: vslidedown.vi v0, v0, 22518; RV32-NEXT: sltu a1, a1, a22519; RV32-NEXT: addi a1, a1, -12520; RV32-NEXT: and a1, a1, a22521; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2522; RV32-NEXT: vslidedown.vi v24, v16, 162523; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2524; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2525; RV32-NEXT: ret2526;2527; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:2528; RV64: # %bb.0:2529; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma2530; RV64-NEXT: vslidedown.vi v24, v8, 162531; RV64-NEXT: li a2, 82532; RV64-NEXT: li a3, 162533; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma2534; RV64-NEXT: vwmulu.vx v16, v24, a22535; RV64-NEXT: vwmulu.vx v24, v8, a22536; RV64-NEXT: mv a2, a12537; RV64-NEXT: bltu a1, a3, .LBB103_22538; RV64-NEXT: # %bb.1:2539; RV64-NEXT: li a2, 162540; RV64-NEXT: .LBB103_2:2541; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2542; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t2543; RV64-NEXT: addi a2, a1, -162544; RV64-NEXT: sltu a1, a1, a22545; RV64-NEXT: addi a1, a1, -12546; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2547; RV64-NEXT: vslidedown.vi v0, v0, 22548; RV64-NEXT: and a1, a1, a22549; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2550; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2551; RV64-NEXT: ret2552 %eidxs = zext <32 x i32> %idxs to <32 x i64>2553 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs2554 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2555 ret <32 x double> %v2556}2557 2558define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) {2559; RV32-LABEL: vpgather_baseidx_v32f64:2560; RV32: # %bb.0:2561; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma2562; RV32-NEXT: vnsrl.wi v24, v16, 02563; RV32-NEXT: vnsrl.wi v16, v8, 02564; RV32-NEXT: li a2, 322565; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma2566; RV32-NEXT: vslideup.vi v16, v24, 162567; RV32-NEXT: li a3, 162568; RV32-NEXT: vsll.vi v16, v16, 32569; RV32-NEXT: mv a2, a12570; RV32-NEXT: bltu a1, a3, .LBB104_22571; RV32-NEXT: # %bb.1:2572; RV32-NEXT: li a2, 162573; RV32-NEXT: .LBB104_2:2574; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma2575; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t2576; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma2577; RV32-NEXT: vslidedown.vi v24, v16, 162578; RV32-NEXT: addi a2, a1, -162579; RV32-NEXT: sltu a1, a1, a22580; RV32-NEXT: addi a1, a1, -12581; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2582; RV32-NEXT: vslidedown.vi v0, v0, 22583; RV32-NEXT: and a1, a1, a22584; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma2585; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t2586; RV32-NEXT: ret2587;2588; RV64-LABEL: vpgather_baseidx_v32f64:2589; RV64: # %bb.0:2590; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma2591; RV64-NEXT: vsll.vi v16, v16, 32592; RV64-NEXT: li a3, 162593; RV64-NEXT: vsll.vi v8, v8, 32594; RV64-NEXT: mv a2, a12595; RV64-NEXT: bltu a1, a3, .LBB104_22596; RV64-NEXT: # %bb.1:2597; RV64-NEXT: li a2, 162598; RV64-NEXT: .LBB104_2:2599; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma2600; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t2601; RV64-NEXT: addi a2, a1, -162602; RV64-NEXT: sltu a1, a1, a22603; RV64-NEXT: addi a1, a1, -12604; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma2605; RV64-NEXT: vslidedown.vi v0, v0, 22606; RV64-NEXT: and a1, a1, a22607; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma2608; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t2609; RV64-NEXT: ret2610 %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %idxs2611 %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)2612 ret <32 x double> %v2613}2614