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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <2 x i8> @vpload_v2i8(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vpload_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vle8.v v8, (a0), v0.t12; CHECK-NEXT: ret13 %load = call <2 x i8> @llvm.vp.load.v2i8.p0(ptr %ptr, <2 x i1> %m, i32 %evl)14 ret <2 x i8> %load15}16 17define <3 x i8> @vpload_v3i8(ptr %ptr, <3 x i1> %m, i32 zeroext %evl) {18; CHECK-LABEL: vpload_v3i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma21; CHECK-NEXT: vle8.v v8, (a0), v0.t22; CHECK-NEXT: ret23 %load = call <3 x i8> @llvm.vp.load.v3i8.p0(ptr %ptr, <3 x i1> %m, i32 %evl)24 ret <3 x i8> %load25}26 27define <4 x i8> @vpload_v4i8(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {28; CHECK-LABEL: vpload_v4i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma31; CHECK-NEXT: vle8.v v8, (a0), v0.t32; CHECK-NEXT: ret33 %load = call <4 x i8> @llvm.vp.load.v4i8.p0(ptr %ptr, <4 x i1> %m, i32 %evl)34 ret <4 x i8> %load35}36 37define <4 x i8> @vpload_v4i8_allones_mask(ptr %ptr, i32 zeroext %evl) {38; CHECK-LABEL: vpload_v4i8_allones_mask:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma41; CHECK-NEXT: vle8.v v8, (a0)42; CHECK-NEXT: ret43 %load = call <4 x i8> @llvm.vp.load.v4i8.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)44 ret <4 x i8> %load45}46 47define <8 x i8> @vpload_v8i8(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {48; CHECK-LABEL: vpload_v8i8:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma51; CHECK-NEXT: vle8.v v8, (a0), v0.t52; CHECK-NEXT: ret53 %load = call <8 x i8> @llvm.vp.load.v8i8.p0(ptr %ptr, <8 x i1> %m, i32 %evl)54 ret <8 x i8> %load55}56 57define <2 x i16> @vpload_v2i16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {58; CHECK-LABEL: vpload_v2i16:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma61; CHECK-NEXT: vle16.v v8, (a0), v0.t62; CHECK-NEXT: ret63 %load = call <2 x i16> @llvm.vp.load.v2i16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)64 ret <2 x i16> %load65}66 67define <4 x i16> @vpload_v4i16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {68; CHECK-LABEL: vpload_v4i16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma71; CHECK-NEXT: vle16.v v8, (a0), v0.t72; CHECK-NEXT: ret73 %load = call <4 x i16> @llvm.vp.load.v4i16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)74 ret <4 x i16> %load75}76 77define <8 x i16> @vpload_v8i16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {78; CHECK-LABEL: vpload_v8i16:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma81; CHECK-NEXT: vle16.v v8, (a0), v0.t82; CHECK-NEXT: ret83 %load = call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)84 ret <8 x i16> %load85}86 87define <8 x i16> @vpload_v8i16_allones_mask(ptr %ptr, i32 zeroext %evl) {88; CHECK-LABEL: vpload_v8i16_allones_mask:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma91; CHECK-NEXT: vle16.v v8, (a0)92; CHECK-NEXT: ret93 %load = call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)94 ret <8 x i16> %load95}96 97define <2 x i32> @vpload_v2i32(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {98; CHECK-LABEL: vpload_v2i32:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma101; CHECK-NEXT: vle32.v v8, (a0), v0.t102; CHECK-NEXT: ret103 %load = call <2 x i32> @llvm.vp.load.v2i32.p0(ptr %ptr, <2 x i1> %m, i32 %evl)104 ret <2 x i32> %load105}106 107define <4 x i32> @vpload_v4i32(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {108; CHECK-LABEL: vpload_v4i32:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma111; CHECK-NEXT: vle32.v v8, (a0), v0.t112; CHECK-NEXT: ret113 %load = call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %ptr, <4 x i1> %m, i32 %evl)114 ret <4 x i32> %load115}116 117define <6 x i32> @vpload_v6i32(ptr %ptr, <6 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: vpload_v6i32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma121; CHECK-NEXT: vle32.v v8, (a0), v0.t122; CHECK-NEXT: ret123 %load = call <6 x i32> @llvm.vp.load.v6i32.p0(ptr %ptr, <6 x i1> %m, i32 %evl)124 ret <6 x i32> %load125}126 127define <6 x i32> @vpload_v6i32_allones_mask(ptr %ptr, i32 zeroext %evl) {128; CHECK-LABEL: vpload_v6i32_allones_mask:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma131; CHECK-NEXT: vle32.v v8, (a0)132; CHECK-NEXT: ret133 %load = call <6 x i32> @llvm.vp.load.v6i32.p0(ptr %ptr, <6 x i1> splat (i1 true), i32 %evl)134 ret <6 x i32> %load135}136 137define <8 x i32> @vpload_v8i32(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {138; CHECK-LABEL: vpload_v8i32:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma141; CHECK-NEXT: vle32.v v8, (a0), v0.t142; CHECK-NEXT: ret143 %load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %m, i32 %evl)144 ret <8 x i32> %load145}146 147define <8 x i32> @vpload_v8i32_allones_mask(ptr %ptr, i32 zeroext %evl) {148; CHECK-LABEL: vpload_v8i32_allones_mask:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma151; CHECK-NEXT: vle32.v v8, (a0)152; CHECK-NEXT: ret153 %load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)154 ret <8 x i32> %load155}156 157define <2 x i64> @vpload_v2i64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {158; CHECK-LABEL: vpload_v2i64:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma161; CHECK-NEXT: vle64.v v8, (a0), v0.t162; CHECK-NEXT: ret163 %load = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)164 ret <2 x i64> %load165}166 167define <4 x i64> @vpload_v4i64(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {168; CHECK-LABEL: vpload_v4i64:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma171; CHECK-NEXT: vle64.v v8, (a0), v0.t172; CHECK-NEXT: ret173 %load = call <4 x i64> @llvm.vp.load.v4i64.p0(ptr %ptr, <4 x i1> %m, i32 %evl)174 ret <4 x i64> %load175}176 177define <4 x i64> @vpload_v4i64_allones_mask(ptr %ptr, i32 zeroext %evl) {178; CHECK-LABEL: vpload_v4i64_allones_mask:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma181; CHECK-NEXT: vle64.v v8, (a0)182; CHECK-NEXT: ret183 %load = call <4 x i64> @llvm.vp.load.v4i64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)184 ret <4 x i64> %load185}186 187define <8 x i64> @vpload_v8i64(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {188; CHECK-LABEL: vpload_v8i64:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma191; CHECK-NEXT: vle64.v v8, (a0), v0.t192; CHECK-NEXT: ret193 %load = call <8 x i64> @llvm.vp.load.v8i64.p0(ptr %ptr, <8 x i1> %m, i32 %evl)194 ret <8 x i64> %load195}196 197define <2 x half> @vpload_v2f16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {198; CHECK-LABEL: vpload_v2f16:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma201; CHECK-NEXT: vle16.v v8, (a0), v0.t202; CHECK-NEXT: ret203 %load = call <2 x half> @llvm.vp.load.v2f16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)204 ret <2 x half> %load205}206 207define <2 x half> @vpload_v2f16_allones_mask(ptr %ptr, i32 zeroext %evl) {208; CHECK-LABEL: vpload_v2f16_allones_mask:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma211; CHECK-NEXT: vle16.v v8, (a0)212; CHECK-NEXT: ret213 %load = call <2 x half> @llvm.vp.load.v2f16.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)214 ret <2 x half> %load215}216 217define <4 x half> @vpload_v4f16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {218; CHECK-LABEL: vpload_v4f16:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma221; CHECK-NEXT: vle16.v v8, (a0), v0.t222; CHECK-NEXT: ret223 %load = call <4 x half> @llvm.vp.load.v4f16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)224 ret <4 x half> %load225}226 227define <8 x half> @vpload_v8f16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vpload_v8f16:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma231; CHECK-NEXT: vle16.v v8, (a0), v0.t232; CHECK-NEXT: ret233 %load = call <8 x half> @llvm.vp.load.v8f16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)234 ret <8 x half> %load235}236 237define <2 x float> @vpload_v2f32(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {238; CHECK-LABEL: vpload_v2f32:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma241; CHECK-NEXT: vle32.v v8, (a0), v0.t242; CHECK-NEXT: ret243 %load = call <2 x float> @llvm.vp.load.v2f32.p0(ptr %ptr, <2 x i1> %m, i32 %evl)244 ret <2 x float> %load245}246 247define <4 x float> @vpload_v4f32(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {248; CHECK-LABEL: vpload_v4f32:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma251; CHECK-NEXT: vle32.v v8, (a0), v0.t252; CHECK-NEXT: ret253 %load = call <4 x float> @llvm.vp.load.v4f32.p0(ptr %ptr, <4 x i1> %m, i32 %evl)254 ret <4 x float> %load255}256 257define <8 x float> @vpload_v8f32(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {258; CHECK-LABEL: vpload_v8f32:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma261; CHECK-NEXT: vle32.v v8, (a0), v0.t262; CHECK-NEXT: ret263 %load = call <8 x float> @llvm.vp.load.v8f32.p0(ptr %ptr, <8 x i1> %m, i32 %evl)264 ret <8 x float> %load265}266 267define <8 x float> @vpload_v8f32_allones_mask(ptr %ptr, i32 zeroext %evl) {268; CHECK-LABEL: vpload_v8f32_allones_mask:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma271; CHECK-NEXT: vle32.v v8, (a0)272; CHECK-NEXT: ret273 %load = call <8 x float> @llvm.vp.load.v8f32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)274 ret <8 x float> %load275}276 277define <2 x double> @vpload_v2f64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {278; CHECK-LABEL: vpload_v2f64:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma281; CHECK-NEXT: vle64.v v8, (a0), v0.t282; CHECK-NEXT: ret283 %load = call <2 x double> @llvm.vp.load.v2f64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)284 ret <2 x double> %load285}286 287define <4 x double> @vpload_v4f64(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {288; CHECK-LABEL: vpload_v4f64:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma291; CHECK-NEXT: vle64.v v8, (a0), v0.t292; CHECK-NEXT: ret293 %load = call <4 x double> @llvm.vp.load.v4f64.p0(ptr %ptr, <4 x i1> %m, i32 %evl)294 ret <4 x double> %load295}296 297define <4 x double> @vpload_v4f64_allones_mask(ptr %ptr, i32 zeroext %evl) {298; CHECK-LABEL: vpload_v4f64_allones_mask:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma301; CHECK-NEXT: vle64.v v8, (a0)302; CHECK-NEXT: ret303 %load = call <4 x double> @llvm.vp.load.v4f64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)304 ret <4 x double> %load305}306 307define <8 x double> @vpload_v8f64(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {308; CHECK-LABEL: vpload_v8f64:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma311; CHECK-NEXT: vle64.v v8, (a0), v0.t312; CHECK-NEXT: ret313 %load = call <8 x double> @llvm.vp.load.v8f64.p0(ptr %ptr, <8 x i1> %m, i32 %evl)314 ret <8 x double> %load315}316 317define <32 x double> @vpload_v32f64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {318; CHECK-LABEL: vpload_v32f64:319; CHECK: # %bb.0:320; CHECK-NEXT: li a3, 16321; CHECK-NEXT: mv a2, a1322; CHECK-NEXT: bltu a1, a3, .LBB31_2323; CHECK-NEXT: # %bb.1:324; CHECK-NEXT: li a2, 16325; CHECK-NEXT: .LBB31_2:326; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma327; CHECK-NEXT: vle64.v v8, (a0), v0.t328; CHECK-NEXT: addi a2, a1, -16329; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma330; CHECK-NEXT: vslidedown.vi v0, v0, 2331; CHECK-NEXT: sltu a1, a1, a2332; CHECK-NEXT: addi a1, a1, -1333; CHECK-NEXT: and a1, a1, a2334; CHECK-NEXT: addi a0, a0, 128335; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma336; CHECK-NEXT: vle64.v v16, (a0), v0.t337; CHECK-NEXT: ret338 %load = call <32 x double> @llvm.vp.load.v32f64.p0(ptr %ptr, <32 x i1> %m, i32 %evl)339 ret <32 x double> %load340}341 342; Widen to v64f64 then split into 4 x v16f64, of which 1 is empty.343 344define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {345; CHECK-LABEL: vpload_v33f64:346; CHECK: # %bb.0:347; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma348; CHECK-NEXT: vmv1r.v v8, v0349; CHECK-NEXT: li a4, 32350; CHECK-NEXT: mv a3, a2351; CHECK-NEXT: bltu a2, a4, .LBB32_2352; CHECK-NEXT: # %bb.1:353; CHECK-NEXT: li a3, 32354; CHECK-NEXT: .LBB32_2:355; CHECK-NEXT: addi a5, a3, -16356; CHECK-NEXT: addi a4, a1, 128357; CHECK-NEXT: addi a7, a2, -32358; CHECK-NEXT: sltu a3, a3, a5359; CHECK-NEXT: addi a3, a3, -1360; CHECK-NEXT: and a6, a3, a5361; CHECK-NEXT: sltu a3, a2, a7362; CHECK-NEXT: addi a3, a3, -1363; CHECK-NEXT: and a5, a3, a7364; CHECK-NEXT: li a3, 16365; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma366; CHECK-NEXT: vslidedown.vi v0, v8, 2367; CHECK-NEXT: bltu a5, a3, .LBB32_4368; CHECK-NEXT: # %bb.3:369; CHECK-NEXT: li a5, 16370; CHECK-NEXT: .LBB32_4:371; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma372; CHECK-NEXT: vle64.v v16, (a4), v0.t373; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma374; CHECK-NEXT: vslidedown.vi v0, v8, 4375; CHECK-NEXT: addi a4, a1, 256376; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma377; CHECK-NEXT: vle64.v v24, (a4), v0.t378; CHECK-NEXT: bltu a2, a3, .LBB32_6379; CHECK-NEXT: # %bb.5:380; CHECK-NEXT: li a2, 16381; CHECK-NEXT: .LBB32_6:382; CHECK-NEXT: vmv1r.v v0, v8383; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma384; CHECK-NEXT: vle64.v v8, (a1), v0.t385; CHECK-NEXT: addi a1, a0, 128386; CHECK-NEXT: addi a2, a0, 256387; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma388; CHECK-NEXT: vse64.v v8, (a0)389; CHECK-NEXT: vse64.v v16, (a1)390; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma391; CHECK-NEXT: vse64.v v24, (a2)392; CHECK-NEXT: ret393 %load = call <33 x double> @llvm.vp.load.v33f64.p0(ptr %ptr, <33 x i1> %m, i32 %evl)394 ret <33 x double> %load395}396