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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define { <2 x i8>, i32 } @vploadff_v2i8(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vploadff_v2i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma15; CHECK-NEXT: vle8ff.v v8, (a0), v0.t16; CHECK-NEXT: csrr a0, vl17; CHECK-NEXT: ret18 %load = call { <2 x i8>, i32 } @llvm.vp.load.ff.v2i8.p0(ptr %ptr, <2 x i1> %m, i32 %evl)19 ret { <2 x i8>, i32 } %load20}21 22define { <2 x i8>, i32 } @vploadff_v2i8_allones_mask(ptr %ptr, i32 zeroext %evl) {23; CHECK-LABEL: vploadff_v2i8_allones_mask:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma26; CHECK-NEXT: vle8ff.v v8, (a0)27; CHECK-NEXT: csrr a0, vl28; CHECK-NEXT: ret29 %load = call { <2 x i8>, i32 } @llvm.vp.load.ff.v2i8.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)30 ret { <2 x i8>, i32 } %load31}32 33define { <4 x i8>, i32 } @vploadff_v4i8(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vploadff_v4i8:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma37; CHECK-NEXT: vle8ff.v v8, (a0), v0.t38; CHECK-NEXT: csrr a0, vl39; CHECK-NEXT: ret40 %load = call { <4 x i8>, i32 } @llvm.vp.load.ff.v4i8.p0(ptr %ptr, <4 x i1> %m, i32 %evl)41 ret { <4 x i8>, i32 } %load42}43 44define { <4 x i8>, i32 } @vploadff_v4i8_allones_mask(ptr %ptr, i32 zeroext %evl) {45; CHECK-LABEL: vploadff_v4i8_allones_mask:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma48; CHECK-NEXT: vle8ff.v v8, (a0)49; CHECK-NEXT: csrr a0, vl50; CHECK-NEXT: ret51 %load = call { <4 x i8>, i32 } @llvm.vp.load.ff.v4i8.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)52 ret { <4 x i8>, i32 } %load53}54 55define { <8 x i8>, i32 } @vploadff_v8i8(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {56; CHECK-LABEL: vploadff_v8i8:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma59; CHECK-NEXT: vle8ff.v v8, (a0), v0.t60; CHECK-NEXT: csrr a0, vl61; CHECK-NEXT: ret62 %load = call { <8 x i8>, i32 } @llvm.vp.load.ff.v8i8.p0(ptr %ptr, <8 x i1> %m, i32 %evl)63 ret { <8 x i8>, i32 } %load64}65 66define { <8 x i8>, i32 } @vploadff_v8i8_allones_mask(ptr %ptr, i32 zeroext %evl) {67; CHECK-LABEL: vploadff_v8i8_allones_mask:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma70; CHECK-NEXT: vle8ff.v v8, (a0)71; CHECK-NEXT: csrr a0, vl72; CHECK-NEXT: ret73 %load = call { <8 x i8>, i32 } @llvm.vp.load.ff.v8i8.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)74 ret { <8 x i8>, i32 } %load75}76 77define { <2 x i16>, i32 } @vploadff_v2i16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {78; CHECK-LABEL: vploadff_v2i16:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma81; CHECK-NEXT: vle16ff.v v8, (a0), v0.t82; CHECK-NEXT: csrr a0, vl83; CHECK-NEXT: ret84 %load = call { <2 x i16>, i32 } @llvm.vp.load.ff.v2i16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)85 ret { <2 x i16>, i32 } %load86}87 88define { <2 x i16>, i32 } @vploadff_v2i16_allones_mask(ptr %ptr, i32 zeroext %evl) {89; CHECK-LABEL: vploadff_v2i16_allones_mask:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma92; CHECK-NEXT: vle16ff.v v8, (a0)93; CHECK-NEXT: csrr a0, vl94; CHECK-NEXT: ret95 %load = call { <2 x i16>, i32 } @llvm.vp.load.ff.v2i16.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)96 ret { <2 x i16>, i32 } %load97}98 99define { <4 x i16>, i32 } @vploadff_v4i16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {100; CHECK-LABEL: vploadff_v4i16:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma103; CHECK-NEXT: vle16ff.v v8, (a0), v0.t104; CHECK-NEXT: csrr a0, vl105; CHECK-NEXT: ret106 %load = call { <4 x i16>, i32 } @llvm.vp.load.ff.v4i16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)107 ret { <4 x i16>, i32 } %load108}109 110define { <4 x i16>, i32 } @vploadff_v4i16_allones_mask(ptr %ptr, i32 zeroext %evl) {111; CHECK-LABEL: vploadff_v4i16_allones_mask:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma114; CHECK-NEXT: vle16ff.v v8, (a0)115; CHECK-NEXT: csrr a0, vl116; CHECK-NEXT: ret117 %load = call { <4 x i16>, i32 } @llvm.vp.load.ff.v4i16.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)118 ret { <4 x i16>, i32 } %load119}120 121define { <8 x i16>, i32 } @vploadff_v8i16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: vploadff_v8i16:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma125; CHECK-NEXT: vle16ff.v v8, (a0), v0.t126; CHECK-NEXT: csrr a0, vl127; CHECK-NEXT: ret128 %load = call { <8 x i16>, i32 } @llvm.vp.load.ff.v8i16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)129 ret { <8 x i16>, i32 } %load130}131 132define { <8 x i16>, i32 } @vploadff_v8i16_allones_mask(ptr %ptr, i32 zeroext %evl) {133; CHECK-LABEL: vploadff_v8i16_allones_mask:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma136; CHECK-NEXT: vle16ff.v v8, (a0)137; CHECK-NEXT: csrr a0, vl138; CHECK-NEXT: ret139 %load = call { <8 x i16>, i32 } @llvm.vp.load.ff.v8i16.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)140 ret { <8 x i16>, i32 } %load141}142 143define { <2 x i32>, i32 } @vploadff_v2i32(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {144; CHECK-LABEL: vploadff_v2i32:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma147; CHECK-NEXT: vle32ff.v v8, (a0), v0.t148; CHECK-NEXT: csrr a0, vl149; CHECK-NEXT: ret150 %load = call { <2 x i32>, i32 } @llvm.vp.load.ff.v2i32.p0(ptr %ptr, <2 x i1> %m, i32 %evl)151 ret { <2 x i32>, i32 } %load152}153 154define { <2 x i32>, i32 } @vploadff_v2i32_allones_mask(ptr %ptr, i32 zeroext %evl) {155; CHECK-LABEL: vploadff_v2i32_allones_mask:156; CHECK: # %bb.0:157; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma158; CHECK-NEXT: vle32ff.v v8, (a0)159; CHECK-NEXT: csrr a0, vl160; CHECK-NEXT: ret161 %load = call { <2 x i32>, i32 } @llvm.vp.load.ff.v2i32.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)162 ret { <2 x i32>, i32 } %load163}164 165define { <4 x i32>, i32 } @vploadff_v4i32(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {166; CHECK-LABEL: vploadff_v4i32:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma169; CHECK-NEXT: vle32ff.v v8, (a0), v0.t170; CHECK-NEXT: csrr a0, vl171; CHECK-NEXT: ret172 %load = call { <4 x i32>, i32 } @llvm.vp.load.ff.v4i32.p0(ptr %ptr, <4 x i1> %m, i32 %evl)173 ret { <4 x i32>, i32 } %load174}175 176define { <4 x i32>, i32 } @vploadff_v4i32_allones_mask(ptr %ptr, i32 zeroext %evl) {177; CHECK-LABEL: vploadff_v4i32_allones_mask:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma180; CHECK-NEXT: vle32ff.v v8, (a0)181; CHECK-NEXT: csrr a0, vl182; CHECK-NEXT: ret183 %load = call { <4 x i32>, i32 } @llvm.vp.load.ff.v4i32.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)184 ret { <4 x i32>, i32 } %load185}186 187define { <8 x i32>, i32 } @vploadff_v8i32(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {188; CHECK-LABEL: vploadff_v8i32:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma191; CHECK-NEXT: vle32ff.v v8, (a0), v0.t192; CHECK-NEXT: csrr a0, vl193; CHECK-NEXT: ret194 %load = call { <8 x i32>, i32 } @llvm.vp.load.ff.v8i32.p0(ptr %ptr, <8 x i1> %m, i32 %evl)195 ret { <8 x i32>, i32 } %load196}197 198define { <8 x i32>, i32 } @vploadff_v8i32_allones_mask(ptr %ptr, i32 zeroext %evl) {199; CHECK-LABEL: vploadff_v8i32_allones_mask:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma202; CHECK-NEXT: vle32ff.v v8, (a0)203; CHECK-NEXT: csrr a0, vl204; CHECK-NEXT: ret205 %load = call { <8 x i32>, i32 } @llvm.vp.load.ff.v8i32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)206 ret { <8 x i32>, i32 } %load207}208 209define { <2 x i64>, i32 } @vploadff_v2i64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {210; CHECK-LABEL: vploadff_v2i64:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma213; CHECK-NEXT: vle64ff.v v8, (a0), v0.t214; CHECK-NEXT: csrr a0, vl215; CHECK-NEXT: ret216 %load = call { <2 x i64>, i32 } @llvm.vp.load.ff.v2i64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)217 ret { <2 x i64>, i32 } %load218}219 220define { <2 x i64>, i32 } @vploadff_v2i64_allones_mask(ptr %ptr, i32 zeroext %evl) {221; CHECK-LABEL: vploadff_v2i64_allones_mask:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma224; CHECK-NEXT: vle64ff.v v8, (a0)225; CHECK-NEXT: csrr a0, vl226; CHECK-NEXT: ret227 %load = call { <2 x i64>, i32 } @llvm.vp.load.ff.v2i64.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)228 ret { <2 x i64>, i32 } %load229}230 231define { <4 x i64>, i32 } @vploadff_v4i64(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: vploadff_v4i64:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma235; CHECK-NEXT: vle64ff.v v8, (a0), v0.t236; CHECK-NEXT: csrr a0, vl237; CHECK-NEXT: ret238 %load = call { <4 x i64>, i32 } @llvm.vp.load.ff.v4i64.p0(ptr %ptr, <4 x i1> %m, i32 %evl)239 ret { <4 x i64>, i32 } %load240}241 242define { <4 x i64>, i32 } @vploadff_v4i64_allones_mask(ptr %ptr, i32 zeroext %evl) {243; CHECK-LABEL: vploadff_v4i64_allones_mask:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma246; CHECK-NEXT: vle64ff.v v8, (a0)247; CHECK-NEXT: csrr a0, vl248; CHECK-NEXT: ret249 %load = call { <4 x i64>, i32 } @llvm.vp.load.ff.v4i64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)250 ret { <4 x i64>, i32 } %load251}252 253define { <8 x i64>, i32 } @vploadff_v8i64(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {254; CHECK-LABEL: vploadff_v8i64:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma257; CHECK-NEXT: vle64ff.v v8, (a0), v0.t258; CHECK-NEXT: csrr a0, vl259; CHECK-NEXT: ret260 %load = call { <8 x i64>, i32 } @llvm.vp.load.ff.v8i64.p0(ptr %ptr, <8 x i1> %m, i32 %evl)261 ret { <8 x i64>, i32 } %load262}263 264define { <8 x i64>, i32 } @vploadff_v8i64_allones_mask(ptr %ptr, i32 zeroext %evl) {265; CHECK-LABEL: vploadff_v8i64_allones_mask:266; CHECK: # %bb.0:267; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma268; CHECK-NEXT: vle64ff.v v8, (a0)269; CHECK-NEXT: csrr a0, vl270; CHECK-NEXT: ret271 %load = call { <8 x i64>, i32 } @llvm.vp.load.ff.v8i64.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)272 ret { <8 x i64>, i32 } %load273}274 275define { <32 x i64>, i32 } @vploadff_v32i64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {276; CHECK-LABEL: vploadff_v32i64:277; CHECK: # %bb.0:278; CHECK-NEXT: li a3, 16279; CHECK-NEXT: bltu a2, a3, .LBB24_2280; CHECK-NEXT: # %bb.1:281; CHECK-NEXT: li a2, 16282; CHECK-NEXT: .LBB24_2:283; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma284; CHECK-NEXT: vle64ff.v v8, (a1), v0.t285; CHECK-NEXT: csrr a1, vl286; CHECK-NEXT: sw a1, 256(a0)287; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma288; CHECK-NEXT: vse64.v v8, (a0)289; CHECK-NEXT: ret290 %load = call { <32 x i64>, i32 } @llvm.vp.load.ff.v32i64.p0(ptr %ptr, <32 x i1> %m, i32 %evl)291 ret { <32 x i64>, i32 } %load292}293 294define { <32 x i64>, i32 } @vploadff_v32i64_allones_mask(ptr %ptr, i32 zeroext %evl) {295; CHECK-LABEL: vploadff_v32i64_allones_mask:296; CHECK: # %bb.0:297; CHECK-NEXT: li a3, 16298; CHECK-NEXT: bltu a2, a3, .LBB25_2299; CHECK-NEXT: # %bb.1:300; CHECK-NEXT: li a2, 16301; CHECK-NEXT: .LBB25_2:302; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma303; CHECK-NEXT: vle64ff.v v8, (a1)304; CHECK-NEXT: csrr a1, vl305; CHECK-NEXT: sw a1, 256(a0)306; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma307; CHECK-NEXT: vse64.v v8, (a0)308; CHECK-NEXT: ret309 %load = call { <32 x i64>, i32 } @llvm.vp.load.ff.v32i64.p0(ptr %ptr, <32 x i1> splat (i1 true), i32 %evl)310 ret { <32 x i64>, i32 } %load311}312 313define { <2 x half>, i32 } @vploadff_v2f16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {314; CHECK-LABEL: vploadff_v2f16:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma317; CHECK-NEXT: vle16ff.v v8, (a0), v0.t318; CHECK-NEXT: csrr a0, vl319; CHECK-NEXT: ret320 %load = call { <2 x half>, i32 } @llvm.vp.load.ff.v2f16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)321 ret { <2 x half>, i32 } %load322}323 324define { <2 x half>, i32 } @vploadff_v2f16_allones_mask(ptr %ptr, i32 zeroext %evl) {325; CHECK-LABEL: vploadff_v2f16_allones_mask:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma328; CHECK-NEXT: vle16ff.v v8, (a0)329; CHECK-NEXT: csrr a0, vl330; CHECK-NEXT: ret331 %load = call { <2 x half>, i32 } @llvm.vp.load.ff.v2f16.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)332 ret { <2 x half>, i32 } %load333}334 335define { <4 x half>, i32 } @vploadff_v4f16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {336; CHECK-LABEL: vploadff_v4f16:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma339; CHECK-NEXT: vle16ff.v v8, (a0), v0.t340; CHECK-NEXT: csrr a0, vl341; CHECK-NEXT: ret342 %load = call { <4 x half>, i32 } @llvm.vp.load.ff.v4f16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)343 ret { <4 x half>, i32 } %load344}345 346define { <4 x half>, i32 } @vploadff_v4f16_allones_mask(ptr %ptr, i32 zeroext %evl) {347; CHECK-LABEL: vploadff_v4f16_allones_mask:348; CHECK: # %bb.0:349; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma350; CHECK-NEXT: vle16ff.v v8, (a0)351; CHECK-NEXT: csrr a0, vl352; CHECK-NEXT: ret353 %load = call { <4 x half>, i32 } @llvm.vp.load.ff.v4f16.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)354 ret { <4 x half>, i32 } %load355}356 357define { <8 x half>, i32 } @vploadff_v8f16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {358; CHECK-LABEL: vploadff_v8f16:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma361; CHECK-NEXT: vle16ff.v v8, (a0), v0.t362; CHECK-NEXT: csrr a0, vl363; CHECK-NEXT: ret364 %load = call { <8 x half>, i32 } @llvm.vp.load.ff.v8f16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)365 ret { <8 x half>, i32 } %load366}367 368define { <8 x half>, i32 } @vploadff_v8f16_allones_mask(ptr %ptr, i32 zeroext %evl) {369; CHECK-LABEL: vploadff_v8f16_allones_mask:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma372; CHECK-NEXT: vle16ff.v v8, (a0)373; CHECK-NEXT: csrr a0, vl374; CHECK-NEXT: ret375 %load = call { <8 x half>, i32 } @llvm.vp.load.ff.v8f16.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)376 ret { <8 x half>, i32 } %load377}378 379define { <2 x float>, i32 } @vploadff_v2f32(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {380; CHECK-LABEL: vploadff_v2f32:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma383; CHECK-NEXT: vle32ff.v v8, (a0), v0.t384; CHECK-NEXT: csrr a0, vl385; CHECK-NEXT: ret386 %load = call { <2 x float>, i32 } @llvm.vp.load.ff.v2f32.p0(ptr %ptr, <2 x i1> %m, i32 %evl)387 ret { <2 x float>, i32 } %load388}389 390define { <2 x float>, i32 } @vploadff_v2f32_allones_mask(ptr %ptr, i32 zeroext %evl) {391; CHECK-LABEL: vploadff_v2f32_allones_mask:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma394; CHECK-NEXT: vle32ff.v v8, (a0)395; CHECK-NEXT: csrr a0, vl396; CHECK-NEXT: ret397 %load = call { <2 x float>, i32 } @llvm.vp.load.ff.v2f32.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)398 ret { <2 x float>, i32 } %load399}400 401define { <4 x float>, i32 } @vploadff_v4f32(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {402; CHECK-LABEL: vploadff_v4f32:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma405; CHECK-NEXT: vle32ff.v v8, (a0), v0.t406; CHECK-NEXT: csrr a0, vl407; CHECK-NEXT: ret408 %load = call { <4 x float>, i32 } @llvm.vp.load.ff.v4f32.p0(ptr %ptr, <4 x i1> %m, i32 %evl)409 ret { <4 x float>, i32 } %load410}411 412define { <4 x float>, i32 } @vploadff_v4f32_allones_mask(ptr %ptr, i32 zeroext %evl) {413; CHECK-LABEL: vploadff_v4f32_allones_mask:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma416; CHECK-NEXT: vle32ff.v v8, (a0)417; CHECK-NEXT: csrr a0, vl418; CHECK-NEXT: ret419 %load = call { <4 x float>, i32 } @llvm.vp.load.ff.v4f32.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)420 ret { <4 x float>, i32 } %load421}422 423define { <8 x float>, i32 } @vploadff_v8f32(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {424; CHECK-LABEL: vploadff_v8f32:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma427; CHECK-NEXT: vle32ff.v v8, (a0), v0.t428; CHECK-NEXT: csrr a0, vl429; CHECK-NEXT: ret430 %load = call { <8 x float>, i32 } @llvm.vp.load.ff.v8f32.p0(ptr %ptr, <8 x i1> %m, i32 %evl)431 ret { <8 x float>, i32 } %load432}433 434define { <8 x float>, i32 } @vploadff_v8f32_allones_mask(ptr %ptr, i32 zeroext %evl) {435; CHECK-LABEL: vploadff_v8f32_allones_mask:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma438; CHECK-NEXT: vle32ff.v v8, (a0)439; CHECK-NEXT: csrr a0, vl440; CHECK-NEXT: ret441 %load = call { <8 x float>, i32 } @llvm.vp.load.ff.v8f32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)442 ret { <8 x float>, i32 } %load443}444 445define { <2 x double>, i32 } @vploadff_v2f64(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {446; CHECK-LABEL: vploadff_v2f64:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma449; CHECK-NEXT: vle64ff.v v8, (a0), v0.t450; CHECK-NEXT: csrr a0, vl451; CHECK-NEXT: ret452 %load = call { <2 x double>, i32 } @llvm.vp.load.ff.v2f64.p0(ptr %ptr, <2 x i1> %m, i32 %evl)453 ret { <2 x double>, i32 } %load454}455 456define { <2 x double>, i32 } @vploadff_v2f64_allones_mask(ptr %ptr, i32 zeroext %evl) {457; CHECK-LABEL: vploadff_v2f64_allones_mask:458; CHECK: # %bb.0:459; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma460; CHECK-NEXT: vle64ff.v v8, (a0)461; CHECK-NEXT: csrr a0, vl462; CHECK-NEXT: ret463 %load = call { <2 x double>, i32 } @llvm.vp.load.ff.v2f64.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)464 ret { <2 x double>, i32 } %load465}466 467define { <4 x double>, i32 } @vploadff_v4f64(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {468; CHECK-LABEL: vploadff_v4f64:469; CHECK: # %bb.0:470; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma471; CHECK-NEXT: vle64ff.v v8, (a0), v0.t472; CHECK-NEXT: csrr a0, vl473; CHECK-NEXT: ret474 %load = call { <4 x double>, i32 } @llvm.vp.load.ff.v4f64.p0(ptr %ptr, <4 x i1> %m, i32 %evl)475 ret { <4 x double>, i32 } %load476}477 478define { <4 x double>, i32 } @vploadff_v4f64_allones_mask(ptr %ptr, i32 zeroext %evl) {479; CHECK-LABEL: vploadff_v4f64_allones_mask:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma482; CHECK-NEXT: vle64ff.v v8, (a0)483; CHECK-NEXT: csrr a0, vl484; CHECK-NEXT: ret485 %load = call { <4 x double>, i32 } @llvm.vp.load.ff.v4f64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)486 ret { <4 x double>, i32 } %load487}488 489define { <8 x double>, i32 } @vploadff_v8f64(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {490; CHECK-LABEL: vploadff_v8f64:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma493; CHECK-NEXT: vle64ff.v v8, (a0), v0.t494; CHECK-NEXT: csrr a0, vl495; CHECK-NEXT: ret496 %load = call { <8 x double>, i32 } @llvm.vp.load.ff.v8f64.p0(ptr %ptr, <8 x i1> %m, i32 %evl)497 ret { <8 x double>, i32 } %load498}499 500define { <8 x double>, i32 } @vploadff_v8f64_allones_mask(ptr %ptr, i32 zeroext %evl) {501; CHECK-LABEL: vploadff_v8f64_allones_mask:502; CHECK: # %bb.0:503; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma504; CHECK-NEXT: vle64ff.v v8, (a0)505; CHECK-NEXT: csrr a0, vl506; CHECK-NEXT: ret507 %load = call { <8 x double>, i32 } @llvm.vp.load.ff.v8f64.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)508 ret { <8 x double>, i32 } %load509}510 511define { <2 x bfloat>, i32 } @vploadff_v2bf16(ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {512; CHECK-LABEL: vploadff_v2bf16:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma515; CHECK-NEXT: vle16ff.v v8, (a0), v0.t516; CHECK-NEXT: csrr a0, vl517; CHECK-NEXT: ret518 %load = call { <2 x bfloat>, i32 } @llvm.vp.load.ff.v2bf16.p0(ptr %ptr, <2 x i1> %m, i32 %evl)519 ret { <2 x bfloat>, i32 } %load520}521 522define { <2 x bfloat>, i32 } @vploadff_v2bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {523; CHECK-LABEL: vploadff_v2bf16_allones_mask:524; CHECK: # %bb.0:525; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma526; CHECK-NEXT: vle16ff.v v8, (a0)527; CHECK-NEXT: csrr a0, vl528; CHECK-NEXT: ret529 %load = call { <2 x bfloat>, i32 } @llvm.vp.load.ff.v2bf16.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)530 ret { <2 x bfloat>, i32 } %load531}532 533define { <4 x bfloat>, i32 } @vploadff_v4bf16(ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {534; CHECK-LABEL: vploadff_v4bf16:535; CHECK: # %bb.0:536; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma537; CHECK-NEXT: vle16ff.v v8, (a0), v0.t538; CHECK-NEXT: csrr a0, vl539; CHECK-NEXT: ret540 %load = call { <4 x bfloat>, i32 } @llvm.vp.load.ff.v4bf16.p0(ptr %ptr, <4 x i1> %m, i32 %evl)541 ret { <4 x bfloat>, i32 } %load542}543 544define { <4 x bfloat>, i32 } @vploadff_v4bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {545; CHECK-LABEL: vploadff_v4bf16_allones_mask:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma548; CHECK-NEXT: vle16ff.v v8, (a0)549; CHECK-NEXT: csrr a0, vl550; CHECK-NEXT: ret551 %load = call { <4 x bfloat>, i32 } @llvm.vp.load.ff.v4bf16.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl)552 ret { <4 x bfloat>, i32 } %load553}554 555define { <8 x bfloat>, i32 } @vploadff_v8bf16(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {556; CHECK-LABEL: vploadff_v8bf16:557; CHECK: # %bb.0:558; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma559; CHECK-NEXT: vle16ff.v v8, (a0), v0.t560; CHECK-NEXT: csrr a0, vl561; CHECK-NEXT: ret562 %load = call { <8 x bfloat>, i32 } @llvm.vp.load.ff.v8bf16.p0(ptr %ptr, <8 x i1> %m, i32 %evl)563 ret { <8 x bfloat>, i32 } %load564}565 566define { <8 x bfloat>, i32 } @vploadff_v8bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {567; CHECK-LABEL: vploadff_v8bf16_allones_mask:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma570; CHECK-NEXT: vle16ff.v v8, (a0)571; CHECK-NEXT: csrr a0, vl572; CHECK-NEXT: ret573 %load = call { <8 x bfloat>, i32 } @llvm.vp.load.ff.v8bf16.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl)574 ret { <8 x bfloat>, i32 } %load575}576 577define { <7 x i8>, i32 } @vploadff_v7i8(ptr %ptr, <7 x i1> %m, i32 zeroext %evl) {578; CHECK-LABEL: vploadff_v7i8:579; CHECK: # %bb.0:580; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma581; CHECK-NEXT: vle8ff.v v8, (a0), v0.t582; CHECK-NEXT: csrr a0, vl583; CHECK-NEXT: ret584 %load = call { <7 x i8>, i32 } @llvm.vp.load.ff.v7i8.p0(ptr %ptr, <7 x i1> %m, i32 %evl)585 ret { <7 x i8>, i32 } %load586}587