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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define bfloat @vpreduce_fmin_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vpreduce_fmin_nxv4bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma11; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v812; CHECK-NEXT: fcvt.s.bf16 fa5, fa013; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma14; CHECK-NEXT: vfmv.s.f v8, fa515; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma16; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t17; CHECK-NEXT: vfmv.f.s fa5, v818; CHECK-NEXT: fcvt.bf16.s fa0, fa519; CHECK-NEXT: ret20 %s = call bfloat @llvm.vp.reduce.fmin.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)21 ret bfloat %s22}23 24define bfloat @vpreduce_fmax_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {25; CHECK-LABEL: vpreduce_fmax_nxv4bf16:26; CHECK: # %bb.0:27; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma28; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v829; CHECK-NEXT: fcvt.s.bf16 fa5, fa030; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma31; CHECK-NEXT: vfmv.s.f v8, fa532; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma33; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t34; CHECK-NEXT: vfmv.f.s fa5, v835; CHECK-NEXT: fcvt.bf16.s fa0, fa536; CHECK-NEXT: ret37 %s = call bfloat @llvm.vp.reduce.fmax.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)38 ret bfloat %s39}40 41define bfloat @vpreduce_fmin_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {42; CHECK-LABEL: vpreduce_fmin_nnan_nxv4bf16:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma45; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v846; CHECK-NEXT: fcvt.s.bf16 fa5, fa047; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma48; CHECK-NEXT: vfmv.s.f v8, fa549; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma50; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t51; CHECK-NEXT: vfmv.f.s fa5, v852; CHECK-NEXT: fcvt.bf16.s fa0, fa553; CHECK-NEXT: ret54 %s = call nnan bfloat @llvm.vp.reduce.fmin.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)55 ret bfloat %s56}57 58define bfloat @vpreduce_fmax_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {59; CHECK-LABEL: vpreduce_fmax_nnan_nxv4bf16:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma62; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v863; CHECK-NEXT: fcvt.s.bf16 fa5, fa064; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma65; CHECK-NEXT: vfmv.s.f v8, fa566; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma67; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t68; CHECK-NEXT: vfmv.f.s fa5, v869; CHECK-NEXT: fcvt.bf16.s fa0, fa570; CHECK-NEXT: ret71 %s = call nnan bfloat @llvm.vp.reduce.fmax.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)72 ret bfloat %s73}74 75define bfloat @vpreduce_fminimum_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {76; CHECK-LABEL: vpreduce_fminimum_nxv4bf16:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma79; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v880; CHECK-NEXT: fcvt.s.bf16 fa5, fa081; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma82; CHECK-NEXT: vmfne.vv v8, v9, v9, v0.t83; CHECK-NEXT: feq.s a1, fa5, fa584; CHECK-NEXT: vcpop.m a2, v8, v0.t85; CHECK-NEXT: xori a1, a1, 186; CHECK-NEXT: or a1, a2, a187; CHECK-NEXT: beqz a1, .LBB4_288; CHECK-NEXT: # %bb.1:89; CHECK-NEXT: lui a0, 52326490; CHECK-NEXT: fmv.w.x fa5, a091; CHECK-NEXT: fcvt.bf16.s fa0, fa592; CHECK-NEXT: ret93; CHECK-NEXT: .LBB4_2:94; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma95; CHECK-NEXT: vfmv.s.f v8, fa596; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma97; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t98; CHECK-NEXT: vfmv.f.s fa5, v899; CHECK-NEXT: fcvt.bf16.s fa0, fa5100; CHECK-NEXT: ret101 %s = call bfloat @llvm.vp.reduce.fminimum.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)102 ret bfloat %s103}104 105define bfloat @vpreduce_fmaximum_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {106; CHECK-LABEL: vpreduce_fmaximum_nxv4bf16:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma109; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8110; CHECK-NEXT: fcvt.s.bf16 fa5, fa0111; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma112; CHECK-NEXT: vmfne.vv v8, v9, v9, v0.t113; CHECK-NEXT: feq.s a1, fa5, fa5114; CHECK-NEXT: vcpop.m a2, v8, v0.t115; CHECK-NEXT: xori a1, a1, 1116; CHECK-NEXT: or a1, a2, a1117; CHECK-NEXT: beqz a1, .LBB5_2118; CHECK-NEXT: # %bb.1:119; CHECK-NEXT: lui a0, 523264120; CHECK-NEXT: fmv.w.x fa5, a0121; CHECK-NEXT: fcvt.bf16.s fa0, fa5122; CHECK-NEXT: ret123; CHECK-NEXT: .LBB5_2:124; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma125; CHECK-NEXT: vfmv.s.f v8, fa5126; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma127; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t128; CHECK-NEXT: vfmv.f.s fa5, v8129; CHECK-NEXT: fcvt.bf16.s fa0, fa5130; CHECK-NEXT: ret131 %s = call bfloat @llvm.vp.reduce.fmaximum.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)132 ret bfloat %s133}134 135define bfloat @vpreduce_fminimum_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {136; CHECK-LABEL: vpreduce_fminimum_nnan_nxv4bf16:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma139; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8140; CHECK-NEXT: fcvt.s.bf16 fa5, fa0141; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma142; CHECK-NEXT: vfmv.s.f v8, fa5143; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma144; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t145; CHECK-NEXT: vfmv.f.s fa5, v8146; CHECK-NEXT: fcvt.bf16.s fa0, fa5147; CHECK-NEXT: ret148 %s = call nnan bfloat @llvm.vp.reduce.fminimum.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)149 ret bfloat %s150}151 152define bfloat @vpreduce_fmaximum_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 zeroext %evl) {153; CHECK-LABEL: vpreduce_fmaximum_nnan_nxv4bf16:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma156; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8157; CHECK-NEXT: fcvt.s.bf16 fa5, fa0158; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma159; CHECK-NEXT: vfmv.s.f v8, fa5160; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma161; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t162; CHECK-NEXT: vfmv.f.s fa5, v8163; CHECK-NEXT: fcvt.bf16.s fa0, fa5164; CHECK-NEXT: ret165 %s = call nnan bfloat @llvm.vp.reduce.fmaximum.nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1> %m, i32 %evl)166 ret bfloat %s167}168