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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s4 5define zeroext i1 @vreduce_or_v1i1(<1 x i1> %v) {6; CHECK-LABEL: vreduce_or_v1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vfirst.m a0, v010; CHECK-NEXT: seqz a0, a011; CHECK-NEXT: ret12 %red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v)13 ret i1 %red14}15 16define zeroext i1 @vreduce_xor_v1i1(<1 x i1> %v) {17; CHECK-LABEL: vreduce_xor_v1i1:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma20; CHECK-NEXT: vfirst.m a0, v021; CHECK-NEXT: seqz a0, a022; CHECK-NEXT: ret23 %red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v)24 ret i1 %red25}26 27define zeroext i1 @vreduce_and_v1i1(<1 x i1> %v) {28; CHECK-LABEL: vreduce_and_v1i1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-NEXT: vfirst.m a0, v032; CHECK-NEXT: seqz a0, a033; CHECK-NEXT: ret34 %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)35 ret i1 %red36}37 38define zeroext i1 @vreduce_umax_v1i1(<1 x i1> %v) {39; CHECK-LABEL: vreduce_umax_v1i1:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma42; CHECK-NEXT: vfirst.m a0, v043; CHECK-NEXT: seqz a0, a044; CHECK-NEXT: ret45 %red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v)46 ret i1 %red47}48 49define zeroext i1 @vreduce_smax_v1i1(<1 x i1> %v) {50; CHECK-LABEL: vreduce_smax_v1i1:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma53; CHECK-NEXT: vfirst.m a0, v054; CHECK-NEXT: seqz a0, a055; CHECK-NEXT: ret56 %red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v)57 ret i1 %red58}59 60define zeroext i1 @vreduce_umin_v1i1(<1 x i1> %v) {61; CHECK-LABEL: vreduce_umin_v1i1:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma64; CHECK-NEXT: vfirst.m a0, v065; CHECK-NEXT: seqz a0, a066; CHECK-NEXT: ret67 %red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v)68 ret i1 %red69}70 71define zeroext i1 @vreduce_smin_v1i1(<1 x i1> %v) {72; CHECK-LABEL: vreduce_smin_v1i1:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma75; CHECK-NEXT: vfirst.m a0, v076; CHECK-NEXT: seqz a0, a077; CHECK-NEXT: ret78 %red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v)79 ret i1 %red80}81 82define zeroext i1 @vreduce_or_v2i1(<2 x i1> %v) {83; CHECK-LABEL: vreduce_or_v2i1:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma86; CHECK-NEXT: vcpop.m a0, v087; CHECK-NEXT: snez a0, a088; CHECK-NEXT: ret89 %red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %v)90 ret i1 %red91}92 93define zeroext i1 @vreduce_xor_v2i1(<2 x i1> %v) {94; CHECK-LABEL: vreduce_xor_v2i1:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma97; CHECK-NEXT: vcpop.m a0, v098; CHECK-NEXT: andi a0, a0, 199; CHECK-NEXT: ret100 %red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %v)101 ret i1 %red102}103 104define zeroext i1 @vreduce_and_v2i1(<2 x i1> %v) {105; CHECK-LABEL: vreduce_and_v2i1:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma108; CHECK-NEXT: vmnot.m v8, v0109; CHECK-NEXT: vcpop.m a0, v8110; CHECK-NEXT: seqz a0, a0111; CHECK-NEXT: ret112 %red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v)113 ret i1 %red114}115 116define zeroext i1 @vreduce_umax_v2i1(<2 x i1> %v) {117; CHECK-LABEL: vreduce_umax_v2i1:118; CHECK: # %bb.0:119; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma120; CHECK-NEXT: vcpop.m a0, v0121; CHECK-NEXT: snez a0, a0122; CHECK-NEXT: ret123 %red = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> %v)124 ret i1 %red125}126 127define zeroext i1 @vreduce_smax_v2i1(<2 x i1> %v) {128; CHECK-LABEL: vreduce_smax_v2i1:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma131; CHECK-NEXT: vmnot.m v8, v0132; CHECK-NEXT: vcpop.m a0, v8133; CHECK-NEXT: seqz a0, a0134; CHECK-NEXT: ret135 %red = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> %v)136 ret i1 %red137}138 139define zeroext i1 @vreduce_umin_v2i1(<2 x i1> %v) {140; CHECK-LABEL: vreduce_umin_v2i1:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma143; CHECK-NEXT: vmnot.m v8, v0144; CHECK-NEXT: vcpop.m a0, v8145; CHECK-NEXT: seqz a0, a0146; CHECK-NEXT: ret147 %red = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> %v)148 ret i1 %red149}150 151define zeroext i1 @vreduce_smin_v2i1(<2 x i1> %v) {152; CHECK-LABEL: vreduce_smin_v2i1:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma155; CHECK-NEXT: vcpop.m a0, v0156; CHECK-NEXT: snez a0, a0157; CHECK-NEXT: ret158 %red = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> %v)159 ret i1 %red160}161 162define zeroext i1 @vreduce_or_v4i1(<4 x i1> %v) {163; CHECK-LABEL: vreduce_or_v4i1:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma166; CHECK-NEXT: vcpop.m a0, v0167; CHECK-NEXT: snez a0, a0168; CHECK-NEXT: ret169 %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %v)170 ret i1 %red171}172 173define zeroext i1 @vreduce_xor_v4i1(<4 x i1> %v) {174; CHECK-LABEL: vreduce_xor_v4i1:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma177; CHECK-NEXT: vcpop.m a0, v0178; CHECK-NEXT: andi a0, a0, 1179; CHECK-NEXT: ret180 %red = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %v)181 ret i1 %red182}183 184define zeroext i1 @vreduce_and_v4i1(<4 x i1> %v) {185; CHECK-LABEL: vreduce_and_v4i1:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma188; CHECK-NEXT: vmnot.m v8, v0189; CHECK-NEXT: vcpop.m a0, v8190; CHECK-NEXT: seqz a0, a0191; CHECK-NEXT: ret192 %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v)193 ret i1 %red194}195 196define zeroext i1 @vreduce_umax_v4i1(<4 x i1> %v) {197; CHECK-LABEL: vreduce_umax_v4i1:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma200; CHECK-NEXT: vcpop.m a0, v0201; CHECK-NEXT: snez a0, a0202; CHECK-NEXT: ret203 %red = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %v)204 ret i1 %red205}206 207define zeroext i1 @vreduce_smax_v4i1(<4 x i1> %v) {208; CHECK-LABEL: vreduce_smax_v4i1:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma211; CHECK-NEXT: vmnot.m v8, v0212; CHECK-NEXT: vcpop.m a0, v8213; CHECK-NEXT: seqz a0, a0214; CHECK-NEXT: ret215 %red = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> %v)216 ret i1 %red217}218 219define zeroext i1 @vreduce_umin_v4i1(<4 x i1> %v) {220; CHECK-LABEL: vreduce_umin_v4i1:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma223; CHECK-NEXT: vmnot.m v8, v0224; CHECK-NEXT: vcpop.m a0, v8225; CHECK-NEXT: seqz a0, a0226; CHECK-NEXT: ret227 %red = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> %v)228 ret i1 %red229}230 231define zeroext i1 @vreduce_smin_v4i1(<4 x i1> %v) {232; CHECK-LABEL: vreduce_smin_v4i1:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma235; CHECK-NEXT: vcpop.m a0, v0236; CHECK-NEXT: snez a0, a0237; CHECK-NEXT: ret238 %red = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> %v)239 ret i1 %red240}241 242define zeroext i1 @vreduce_or_v8i1(<8 x i1> %v) {243; CHECK-LABEL: vreduce_or_v8i1:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma246; CHECK-NEXT: vcpop.m a0, v0247; CHECK-NEXT: snez a0, a0248; CHECK-NEXT: ret249 %red = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %v)250 ret i1 %red251}252 253define zeroext i1 @vreduce_xor_v8i1(<8 x i1> %v) {254; CHECK-LABEL: vreduce_xor_v8i1:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma257; CHECK-NEXT: vcpop.m a0, v0258; CHECK-NEXT: andi a0, a0, 1259; CHECK-NEXT: ret260 %red = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %v)261 ret i1 %red262}263 264define zeroext i1 @vreduce_and_v8i1(<8 x i1> %v) {265; CHECK-LABEL: vreduce_and_v8i1:266; CHECK: # %bb.0:267; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma268; CHECK-NEXT: vmnot.m v8, v0269; CHECK-NEXT: vcpop.m a0, v8270; CHECK-NEXT: seqz a0, a0271; CHECK-NEXT: ret272 %red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v)273 ret i1 %red274}275 276define zeroext i1 @vreduce_umax_v8i1(<8 x i1> %v) {277; CHECK-LABEL: vreduce_umax_v8i1:278; CHECK: # %bb.0:279; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma280; CHECK-NEXT: vcpop.m a0, v0281; CHECK-NEXT: snez a0, a0282; CHECK-NEXT: ret283 %red = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> %v)284 ret i1 %red285}286 287define zeroext i1 @vreduce_smax_v8i1(<8 x i1> %v) {288; CHECK-LABEL: vreduce_smax_v8i1:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma291; CHECK-NEXT: vmnot.m v8, v0292; CHECK-NEXT: vcpop.m a0, v8293; CHECK-NEXT: seqz a0, a0294; CHECK-NEXT: ret295 %red = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> %v)296 ret i1 %red297}298 299define zeroext i1 @vreduce_umin_v8i1(<8 x i1> %v) {300; CHECK-LABEL: vreduce_umin_v8i1:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma303; CHECK-NEXT: vmnot.m v8, v0304; CHECK-NEXT: vcpop.m a0, v8305; CHECK-NEXT: seqz a0, a0306; CHECK-NEXT: ret307 %red = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> %v)308 ret i1 %red309}310 311define zeroext i1 @vreduce_smin_v8i1(<8 x i1> %v) {312; CHECK-LABEL: vreduce_smin_v8i1:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma315; CHECK-NEXT: vcpop.m a0, v0316; CHECK-NEXT: snez a0, a0317; CHECK-NEXT: ret318 %red = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> %v)319 ret i1 %red320}321 322define zeroext i1 @vreduce_or_v16i1(<16 x i1> %v) {323; CHECK-LABEL: vreduce_or_v16i1:324; CHECK: # %bb.0:325; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma326; CHECK-NEXT: vcpop.m a0, v0327; CHECK-NEXT: snez a0, a0328; CHECK-NEXT: ret329 %red = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %v)330 ret i1 %red331}332 333define zeroext i1 @vreduce_xor_v16i1(<16 x i1> %v) {334; CHECK-LABEL: vreduce_xor_v16i1:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma337; CHECK-NEXT: vcpop.m a0, v0338; CHECK-NEXT: andi a0, a0, 1339; CHECK-NEXT: ret340 %red = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %v)341 ret i1 %red342}343 344define zeroext i1 @vreduce_and_v16i1(<16 x i1> %v) {345; CHECK-LABEL: vreduce_and_v16i1:346; CHECK: # %bb.0:347; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma348; CHECK-NEXT: vmnot.m v8, v0349; CHECK-NEXT: vcpop.m a0, v8350; CHECK-NEXT: seqz a0, a0351; CHECK-NEXT: ret352 %red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v)353 ret i1 %red354}355 356define zeroext i1 @vreduce_umax_v16i1(<16 x i1> %v) {357; CHECK-LABEL: vreduce_umax_v16i1:358; CHECK: # %bb.0:359; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma360; CHECK-NEXT: vcpop.m a0, v0361; CHECK-NEXT: snez a0, a0362; CHECK-NEXT: ret363 %red = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> %v)364 ret i1 %red365}366 367define zeroext i1 @vreduce_smax_v16i1(<16 x i1> %v) {368; CHECK-LABEL: vreduce_smax_v16i1:369; CHECK: # %bb.0:370; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma371; CHECK-NEXT: vmnot.m v8, v0372; CHECK-NEXT: vcpop.m a0, v8373; CHECK-NEXT: seqz a0, a0374; CHECK-NEXT: ret375 %red = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> %v)376 ret i1 %red377}378 379define zeroext i1 @vreduce_umin_v16i1(<16 x i1> %v) {380; CHECK-LABEL: vreduce_umin_v16i1:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma383; CHECK-NEXT: vmnot.m v8, v0384; CHECK-NEXT: vcpop.m a0, v8385; CHECK-NEXT: seqz a0, a0386; CHECK-NEXT: ret387 %red = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> %v)388 ret i1 %red389}390 391define zeroext i1 @vreduce_smin_v16i1(<16 x i1> %v) {392; CHECK-LABEL: vreduce_smin_v16i1:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma395; CHECK-NEXT: vcpop.m a0, v0396; CHECK-NEXT: snez a0, a0397; CHECK-NEXT: ret398 %red = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> %v)399 ret i1 %red400}401 402define zeroext i1 @vreduce_or_v32i1(<32 x i1> %v) {403; CHECK-LABEL: vreduce_or_v32i1:404; CHECK: # %bb.0:405; CHECK-NEXT: li a0, 32406; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma407; CHECK-NEXT: vcpop.m a0, v0408; CHECK-NEXT: snez a0, a0409; CHECK-NEXT: ret410 %red = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %v)411 ret i1 %red412}413 414define zeroext i1 @vreduce_xor_v32i1(<32 x i1> %v) {415; CHECK-LABEL: vreduce_xor_v32i1:416; CHECK: # %bb.0:417; CHECK-NEXT: li a0, 32418; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma419; CHECK-NEXT: vcpop.m a0, v0420; CHECK-NEXT: andi a0, a0, 1421; CHECK-NEXT: ret422 %red = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %v)423 ret i1 %red424}425 426define zeroext i1 @vreduce_and_v32i1(<32 x i1> %v) {427; CHECK-LABEL: vreduce_and_v32i1:428; CHECK: # %bb.0:429; CHECK-NEXT: li a0, 32430; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma431; CHECK-NEXT: vmnot.m v8, v0432; CHECK-NEXT: vcpop.m a0, v8433; CHECK-NEXT: seqz a0, a0434; CHECK-NEXT: ret435 %red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v)436 ret i1 %red437}438 439define zeroext i1 @vreduce_umax_v32i1(<32 x i1> %v) {440; CHECK-LABEL: vreduce_umax_v32i1:441; CHECK: # %bb.0:442; CHECK-NEXT: li a0, 32443; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma444; CHECK-NEXT: vcpop.m a0, v0445; CHECK-NEXT: snez a0, a0446; CHECK-NEXT: ret447 %red = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> %v)448 ret i1 %red449}450 451define zeroext i1 @vreduce_smax_v32i1(<32 x i1> %v) {452; CHECK-LABEL: vreduce_smax_v32i1:453; CHECK: # %bb.0:454; CHECK-NEXT: li a0, 32455; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma456; CHECK-NEXT: vmnot.m v8, v0457; CHECK-NEXT: vcpop.m a0, v8458; CHECK-NEXT: seqz a0, a0459; CHECK-NEXT: ret460 %red = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> %v)461 ret i1 %red462}463 464define zeroext i1 @vreduce_umin_v32i1(<32 x i1> %v) {465; CHECK-LABEL: vreduce_umin_v32i1:466; CHECK: # %bb.0:467; CHECK-NEXT: li a0, 32468; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma469; CHECK-NEXT: vmnot.m v8, v0470; CHECK-NEXT: vcpop.m a0, v8471; CHECK-NEXT: seqz a0, a0472; CHECK-NEXT: ret473 %red = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> %v)474 ret i1 %red475}476 477define zeroext i1 @vreduce_smin_v32i1(<32 x i1> %v) {478; CHECK-LABEL: vreduce_smin_v32i1:479; CHECK: # %bb.0:480; CHECK-NEXT: li a0, 32481; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma482; CHECK-NEXT: vcpop.m a0, v0483; CHECK-NEXT: snez a0, a0484; CHECK-NEXT: ret485 %red = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> %v)486 ret i1 %red487}488 489define zeroext i1 @vreduce_or_v64i1(<64 x i1> %v) {490; CHECK-LABEL: vreduce_or_v64i1:491; CHECK: # %bb.0:492; CHECK-NEXT: li a0, 64493; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma494; CHECK-NEXT: vcpop.m a0, v0495; CHECK-NEXT: snez a0, a0496; CHECK-NEXT: ret497 %red = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> %v)498 ret i1 %red499}500 501define zeroext i1 @vreduce_xor_v64i1(<64 x i1> %v) {502; CHECK-LABEL: vreduce_xor_v64i1:503; CHECK: # %bb.0:504; CHECK-NEXT: li a0, 64505; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma506; CHECK-NEXT: vcpop.m a0, v0507; CHECK-NEXT: andi a0, a0, 1508; CHECK-NEXT: ret509 %red = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> %v)510 ret i1 %red511}512 513define zeroext i1 @vreduce_and_v64i1(<64 x i1> %v) {514; CHECK-LABEL: vreduce_and_v64i1:515; CHECK: # %bb.0:516; CHECK-NEXT: li a0, 64517; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma518; CHECK-NEXT: vmnot.m v8, v0519; CHECK-NEXT: vcpop.m a0, v8520; CHECK-NEXT: seqz a0, a0521; CHECK-NEXT: ret522 %red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v)523 ret i1 %red524}525 526define zeroext i1 @vreduce_umax_v64i1(<64 x i1> %v) {527; CHECK-LABEL: vreduce_umax_v64i1:528; CHECK: # %bb.0:529; CHECK-NEXT: li a0, 64530; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma531; CHECK-NEXT: vcpop.m a0, v0532; CHECK-NEXT: snez a0, a0533; CHECK-NEXT: ret534 %red = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> %v)535 ret i1 %red536}537 538define zeroext i1 @vreduce_smax_v64i1(<64 x i1> %v) {539; CHECK-LABEL: vreduce_smax_v64i1:540; CHECK: # %bb.0:541; CHECK-NEXT: li a0, 64542; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma543; CHECK-NEXT: vmnot.m v8, v0544; CHECK-NEXT: vcpop.m a0, v8545; CHECK-NEXT: seqz a0, a0546; CHECK-NEXT: ret547 %red = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> %v)548 ret i1 %red549}550 551define zeroext i1 @vreduce_umin_v64i1(<64 x i1> %v) {552; CHECK-LABEL: vreduce_umin_v64i1:553; CHECK: # %bb.0:554; CHECK-NEXT: li a0, 64555; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma556; CHECK-NEXT: vmnot.m v8, v0557; CHECK-NEXT: vcpop.m a0, v8558; CHECK-NEXT: seqz a0, a0559; CHECK-NEXT: ret560 %red = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> %v)561 ret i1 %red562}563 564define zeroext i1 @vreduce_smin_v64i1(<64 x i1> %v) {565; CHECK-LABEL: vreduce_smin_v64i1:566; CHECK: # %bb.0:567; CHECK-NEXT: li a0, 64568; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma569; CHECK-NEXT: vcpop.m a0, v0570; CHECK-NEXT: snez a0, a0571; CHECK-NEXT: ret572 %red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)573 ret i1 %red574}575 576define zeroext i1 @vreduce_add_v1i1(<1 x i1> %v) {577; CHECK-LABEL: vreduce_add_v1i1:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma580; CHECK-NEXT: vfirst.m a0, v0581; CHECK-NEXT: seqz a0, a0582; CHECK-NEXT: ret583 %red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v)584 ret i1 %red585}586 587define zeroext i1 @vreduce_add_v2i1(<2 x i1> %v) {588; CHECK-LABEL: vreduce_add_v2i1:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma591; CHECK-NEXT: vcpop.m a0, v0592; CHECK-NEXT: andi a0, a0, 1593; CHECK-NEXT: ret594 %red = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> %v)595 ret i1 %red596}597 598define zeroext i1 @vreduce_add_v4i1(<4 x i1> %v) {599; CHECK-LABEL: vreduce_add_v4i1:600; CHECK: # %bb.0:601; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma602; CHECK-NEXT: vcpop.m a0, v0603; CHECK-NEXT: andi a0, a0, 1604; CHECK-NEXT: ret605 %red = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %v)606 ret i1 %red607}608 609define zeroext i1 @vreduce_add_v8i1(<8 x i1> %v) {610; CHECK-LABEL: vreduce_add_v8i1:611; CHECK: # %bb.0:612; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma613; CHECK-NEXT: vcpop.m a0, v0614; CHECK-NEXT: andi a0, a0, 1615; CHECK-NEXT: ret616 %red = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> %v)617 ret i1 %red618}619 620define zeroext i1 @vreduce_add_v16i1(<16 x i1> %v) {621; CHECK-LABEL: vreduce_add_v16i1:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma624; CHECK-NEXT: vcpop.m a0, v0625; CHECK-NEXT: andi a0, a0, 1626; CHECK-NEXT: ret627 %red = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> %v)628 ret i1 %red629}630 631define zeroext i1 @vreduce_add_v32i1(<32 x i1> %v) {632; CHECK-LABEL: vreduce_add_v32i1:633; CHECK: # %bb.0:634; CHECK-NEXT: li a0, 32635; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma636; CHECK-NEXT: vcpop.m a0, v0637; CHECK-NEXT: andi a0, a0, 1638; CHECK-NEXT: ret639 %red = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> %v)640 ret i1 %red641}642 643define zeroext i1 @vreduce_add_v64i1(<64 x i1> %v) {644; CHECK-LABEL: vreduce_add_v64i1:645; CHECK: # %bb.0:646; CHECK-NEXT: li a0, 64647; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma648; CHECK-NEXT: vcpop.m a0, v0649; CHECK-NEXT: andi a0, a0, 1650; CHECK-NEXT: ret651 %red = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> %v)652 ret i1 %red653}654 655define zeroext i1 @vreduce_or_v128i1(<128 x i1> %v) {656; CHECK-LABEL: vreduce_or_v128i1:657; CHECK: # %bb.0:658; CHECK-NEXT: li a0, 128659; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma660; CHECK-NEXT: vcpop.m a0, v0661; CHECK-NEXT: snez a0, a0662; CHECK-NEXT: ret663 %red = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> %v)664 ret i1 %red665}666 667define zeroext i1 @vreduce_xor_v128i1(<128 x i1> %v) {668; CHECK-LABEL: vreduce_xor_v128i1:669; CHECK: # %bb.0:670; CHECK-NEXT: li a0, 128671; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma672; CHECK-NEXT: vcpop.m a0, v0673; CHECK-NEXT: andi a0, a0, 1674; CHECK-NEXT: ret675 %red = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> %v)676 ret i1 %red677}678 679define zeroext i1 @vreduce_and_v128i1(<128 x i1> %v) {680; CHECK-LABEL: vreduce_and_v128i1:681; CHECK: # %bb.0:682; CHECK-NEXT: li a0, 128683; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma684; CHECK-NEXT: vmnot.m v8, v0685; CHECK-NEXT: vcpop.m a0, v8686; CHECK-NEXT: seqz a0, a0687; CHECK-NEXT: ret688 %red = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> %v)689 ret i1 %red690}691 692define zeroext i1 @vreduce_umax_v128i1(<128 x i1> %v) {693; CHECK-LABEL: vreduce_umax_v128i1:694; CHECK: # %bb.0:695; CHECK-NEXT: li a0, 128696; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma697; CHECK-NEXT: vcpop.m a0, v0698; CHECK-NEXT: snez a0, a0699; CHECK-NEXT: ret700 %red = call i1 @llvm.vector.reduce.umax.v128i1(<128 x i1> %v)701 ret i1 %red702}703 704define zeroext i1 @vreduce_smax_v128i1(<128 x i1> %v) {705; CHECK-LABEL: vreduce_smax_v128i1:706; CHECK: # %bb.0:707; CHECK-NEXT: li a0, 128708; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma709; CHECK-NEXT: vmnot.m v8, v0710; CHECK-NEXT: vcpop.m a0, v8711; CHECK-NEXT: seqz a0, a0712; CHECK-NEXT: ret713 %red = call i1 @llvm.vector.reduce.smax.v128i1(<128 x i1> %v)714 ret i1 %red715}716 717define zeroext i1 @vreduce_umin_v128i1(<128 x i1> %v) {718; CHECK-LABEL: vreduce_umin_v128i1:719; CHECK: # %bb.0:720; CHECK-NEXT: li a0, 128721; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma722; CHECK-NEXT: vmnot.m v8, v0723; CHECK-NEXT: vcpop.m a0, v8724; CHECK-NEXT: seqz a0, a0725; CHECK-NEXT: ret726 %red = call i1 @llvm.vector.reduce.umin.v128i1(<128 x i1> %v)727 ret i1 %red728}729 730define zeroext i1 @vreduce_smin_v128i1(<128 x i1> %v) {731; CHECK-LABEL: vreduce_smin_v128i1:732; CHECK: # %bb.0:733; CHECK-NEXT: li a0, 128734; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma735; CHECK-NEXT: vcpop.m a0, v0736; CHECK-NEXT: snez a0, a0737; CHECK-NEXT: ret738 %red = call i1 @llvm.vector.reduce.smin.v128i1(<128 x i1> %v)739 ret i1 %red740}741 742define zeroext i1 @vreduce_or_v256i1(<256 x i1> %v) {743; CHECK-LABEL: vreduce_or_v256i1:744; CHECK: # %bb.0:745; CHECK-NEXT: li a0, 128746; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma747; CHECK-NEXT: vmor.mm v8, v0, v8748; CHECK-NEXT: vcpop.m a0, v8749; CHECK-NEXT: snez a0, a0750; CHECK-NEXT: ret751 %red = call i1 @llvm.vector.reduce.or.v256i1(<256 x i1> %v)752 ret i1 %red753}754 755define zeroext i1 @vreduce_xor_v256i1(<256 x i1> %v) {756; CHECK-LABEL: vreduce_xor_v256i1:757; CHECK: # %bb.0:758; CHECK-NEXT: li a0, 128759; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma760; CHECK-NEXT: vmxor.mm v8, v0, v8761; CHECK-NEXT: vcpop.m a0, v8762; CHECK-NEXT: andi a0, a0, 1763; CHECK-NEXT: ret764 %red = call i1 @llvm.vector.reduce.xor.v256i1(<256 x i1> %v)765 ret i1 %red766}767 768define zeroext i1 @vreduce_and_v256i1(<256 x i1> %v) {769; CHECK-LABEL: vreduce_and_v256i1:770; CHECK: # %bb.0:771; CHECK-NEXT: li a0, 128772; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma773; CHECK-NEXT: vmnand.mm v8, v0, v8774; CHECK-NEXT: vcpop.m a0, v8775; CHECK-NEXT: seqz a0, a0776; CHECK-NEXT: ret777 %red = call i1 @llvm.vector.reduce.and.v256i1(<256 x i1> %v)778 ret i1 %red779}780 781define zeroext i1 @vreduce_umax_v256i1(<256 x i1> %v) {782; CHECK-LABEL: vreduce_umax_v256i1:783; CHECK: # %bb.0:784; CHECK-NEXT: li a0, 128785; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma786; CHECK-NEXT: vmor.mm v8, v0, v8787; CHECK-NEXT: vcpop.m a0, v8788; CHECK-NEXT: snez a0, a0789; CHECK-NEXT: ret790 %red = call i1 @llvm.vector.reduce.umax.v256i1(<256 x i1> %v)791 ret i1 %red792}793 794define zeroext i1 @vreduce_smax_v256i1(<256 x i1> %v) {795; CHECK-LABEL: vreduce_smax_v256i1:796; CHECK: # %bb.0:797; CHECK-NEXT: li a0, 128798; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma799; CHECK-NEXT: vmnand.mm v8, v0, v8800; CHECK-NEXT: vcpop.m a0, v8801; CHECK-NEXT: seqz a0, a0802; CHECK-NEXT: ret803 %red = call i1 @llvm.vector.reduce.smax.v256i1(<256 x i1> %v)804 ret i1 %red805}806 807define zeroext i1 @vreduce_umin_v256i1(<256 x i1> %v) {808; CHECK-LABEL: vreduce_umin_v256i1:809; CHECK: # %bb.0:810; CHECK-NEXT: li a0, 128811; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma812; CHECK-NEXT: vmnand.mm v8, v0, v8813; CHECK-NEXT: vcpop.m a0, v8814; CHECK-NEXT: seqz a0, a0815; CHECK-NEXT: ret816 %red = call i1 @llvm.vector.reduce.umin.v256i1(<256 x i1> %v)817 ret i1 %red818}819 820define zeroext i1 @vreduce_smin_v256i1(<256 x i1> %v) {821; CHECK-LABEL: vreduce_smin_v256i1:822; CHECK: # %bb.0:823; CHECK-NEXT: li a0, 128824; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma825; CHECK-NEXT: vmor.mm v8, v0, v8826; CHECK-NEXT: vcpop.m a0, v8827; CHECK-NEXT: snez a0, a0828; CHECK-NEXT: ret829 %red = call i1 @llvm.vector.reduce.smin.v256i1(<256 x i1> %v)830 ret i1 %red831}832 833define zeroext i1 @vreduce_or_v512i1(<512 x i1> %v) {834; CHECK-LABEL: vreduce_or_v512i1:835; CHECK: # %bb.0:836; CHECK-NEXT: li a0, 128837; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma838; CHECK-NEXT: vmor.mm v8, v8, v10839; CHECK-NEXT: vmor.mm v9, v0, v9840; CHECK-NEXT: vmor.mm v8, v9, v8841; CHECK-NEXT: vcpop.m a0, v8842; CHECK-NEXT: snez a0, a0843; CHECK-NEXT: ret844 %red = call i1 @llvm.vector.reduce.or.v512i1(<512 x i1> %v)845 ret i1 %red846}847 848define zeroext i1 @vreduce_xor_v512i1(<512 x i1> %v) {849; CHECK-LABEL: vreduce_xor_v512i1:850; CHECK: # %bb.0:851; CHECK-NEXT: li a0, 128852; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma853; CHECK-NEXT: vmxor.mm v8, v8, v10854; CHECK-NEXT: vmxor.mm v9, v0, v9855; CHECK-NEXT: vmxor.mm v8, v9, v8856; CHECK-NEXT: vcpop.m a0, v8857; CHECK-NEXT: andi a0, a0, 1858; CHECK-NEXT: ret859 %red = call i1 @llvm.vector.reduce.xor.v512i1(<512 x i1> %v)860 ret i1 %red861}862 863define zeroext i1 @vreduce_and_v512i1(<512 x i1> %v) {864; CHECK-LABEL: vreduce_and_v512i1:865; CHECK: # %bb.0:866; CHECK-NEXT: li a0, 128867; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma868; CHECK-NEXT: vmand.mm v8, v8, v10869; CHECK-NEXT: vmand.mm v9, v0, v9870; CHECK-NEXT: vmnand.mm v8, v9, v8871; CHECK-NEXT: vcpop.m a0, v8872; CHECK-NEXT: seqz a0, a0873; CHECK-NEXT: ret874 %red = call i1 @llvm.vector.reduce.and.v512i1(<512 x i1> %v)875 ret i1 %red876}877 878define zeroext i1 @vreduce_umax_v512i1(<512 x i1> %v) {879; CHECK-LABEL: vreduce_umax_v512i1:880; CHECK: # %bb.0:881; CHECK-NEXT: li a0, 128882; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma883; CHECK-NEXT: vmor.mm v8, v8, v10884; CHECK-NEXT: vmor.mm v9, v0, v9885; CHECK-NEXT: vmor.mm v8, v9, v8886; CHECK-NEXT: vcpop.m a0, v8887; CHECK-NEXT: snez a0, a0888; CHECK-NEXT: ret889 %red = call i1 @llvm.vector.reduce.umax.v512i1(<512 x i1> %v)890 ret i1 %red891}892 893define zeroext i1 @vreduce_smax_v512i1(<512 x i1> %v) {894; CHECK-LABEL: vreduce_smax_v512i1:895; CHECK: # %bb.0:896; CHECK-NEXT: li a0, 128897; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma898; CHECK-NEXT: vmand.mm v8, v8, v10899; CHECK-NEXT: vmand.mm v9, v0, v9900; CHECK-NEXT: vmnand.mm v8, v9, v8901; CHECK-NEXT: vcpop.m a0, v8902; CHECK-NEXT: seqz a0, a0903; CHECK-NEXT: ret904 %red = call i1 @llvm.vector.reduce.smax.v512i1(<512 x i1> %v)905 ret i1 %red906}907 908define zeroext i1 @vreduce_umin_v512i1(<512 x i1> %v) {909; CHECK-LABEL: vreduce_umin_v512i1:910; CHECK: # %bb.0:911; CHECK-NEXT: li a0, 128912; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma913; CHECK-NEXT: vmand.mm v8, v8, v10914; CHECK-NEXT: vmand.mm v9, v0, v9915; CHECK-NEXT: vmnand.mm v8, v9, v8916; CHECK-NEXT: vcpop.m a0, v8917; CHECK-NEXT: seqz a0, a0918; CHECK-NEXT: ret919 %red = call i1 @llvm.vector.reduce.umin.v512i1(<512 x i1> %v)920 ret i1 %red921}922 923define zeroext i1 @vreduce_smin_v512i1(<512 x i1> %v) {924; CHECK-LABEL: vreduce_smin_v512i1:925; CHECK: # %bb.0:926; CHECK-NEXT: li a0, 128927; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma928; CHECK-NEXT: vmor.mm v8, v8, v10929; CHECK-NEXT: vmor.mm v9, v0, v9930; CHECK-NEXT: vmor.mm v8, v9, v8931; CHECK-NEXT: vcpop.m a0, v8932; CHECK-NEXT: snez a0, a0933; CHECK-NEXT: ret934 %red = call i1 @llvm.vector.reduce.smin.v512i1(<512 x i1> %v)935 ret i1 %red936}937 938define zeroext i1 @vreduce_or_v1024i1(<1024 x i1> %v) {939; CHECK-LABEL: vreduce_or_v1024i1:940; CHECK: # %bb.0:941; CHECK-NEXT: li a0, 128942; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma943; CHECK-NEXT: vmor.mm v10, v10, v14944; CHECK-NEXT: vmor.mm v8, v8, v12945; CHECK-NEXT: vmor.mm v9, v9, v13946; CHECK-NEXT: vmor.mm v11, v0, v11947; CHECK-NEXT: vmor.mm v8, v8, v10948; CHECK-NEXT: vmor.mm v9, v11, v9949; CHECK-NEXT: vmor.mm v8, v9, v8950; CHECK-NEXT: vcpop.m a0, v8951; CHECK-NEXT: snez a0, a0952; CHECK-NEXT: ret953 %red = call i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1> %v)954 ret i1 %red955}956 957define zeroext i1 @vreduce_xor_v1024i1(<1024 x i1> %v) {958; CHECK-LABEL: vreduce_xor_v1024i1:959; CHECK: # %bb.0:960; CHECK-NEXT: li a0, 128961; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma962; CHECK-NEXT: vmxor.mm v10, v10, v14963; CHECK-NEXT: vmxor.mm v8, v8, v12964; CHECK-NEXT: vmxor.mm v9, v9, v13965; CHECK-NEXT: vmxor.mm v11, v0, v11966; CHECK-NEXT: vmxor.mm v8, v8, v10967; CHECK-NEXT: vmxor.mm v9, v11, v9968; CHECK-NEXT: vmxor.mm v8, v9, v8969; CHECK-NEXT: vcpop.m a0, v8970; CHECK-NEXT: andi a0, a0, 1971; CHECK-NEXT: ret972 %red = call i1 @llvm.vector.reduce.xor.v1024i1(<1024 x i1> %v)973 ret i1 %red974}975 976define zeroext i1 @vreduce_and_v1024i1(<1024 x i1> %v) {977; CHECK-LABEL: vreduce_and_v1024i1:978; CHECK: # %bb.0:979; CHECK-NEXT: li a0, 128980; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma981; CHECK-NEXT: vmand.mm v10, v10, v14982; CHECK-NEXT: vmand.mm v8, v8, v12983; CHECK-NEXT: vmand.mm v9, v9, v13984; CHECK-NEXT: vmand.mm v11, v0, v11985; CHECK-NEXT: vmand.mm v8, v8, v10986; CHECK-NEXT: vmand.mm v9, v11, v9987; CHECK-NEXT: vmnand.mm v8, v9, v8988; CHECK-NEXT: vcpop.m a0, v8989; CHECK-NEXT: seqz a0, a0990; CHECK-NEXT: ret991 %red = call i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1> %v)992 ret i1 %red993}994 995define zeroext i1 @vreduce_umax_v1024i1(<1024 x i1> %v) {996; CHECK-LABEL: vreduce_umax_v1024i1:997; CHECK: # %bb.0:998; CHECK-NEXT: li a0, 128999; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1000; CHECK-NEXT: vmor.mm v10, v10, v141001; CHECK-NEXT: vmor.mm v8, v8, v121002; CHECK-NEXT: vmor.mm v9, v9, v131003; CHECK-NEXT: vmor.mm v11, v0, v111004; CHECK-NEXT: vmor.mm v8, v8, v101005; CHECK-NEXT: vmor.mm v9, v11, v91006; CHECK-NEXT: vmor.mm v8, v9, v81007; CHECK-NEXT: vcpop.m a0, v81008; CHECK-NEXT: snez a0, a01009; CHECK-NEXT: ret1010 %red = call i1 @llvm.vector.reduce.umax.v1024i1(<1024 x i1> %v)1011 ret i1 %red1012}1013 1014define zeroext i1 @vreduce_smax_v1024i1(<1024 x i1> %v) {1015; CHECK-LABEL: vreduce_smax_v1024i1:1016; CHECK: # %bb.0:1017; CHECK-NEXT: li a0, 1281018; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1019; CHECK-NEXT: vmand.mm v10, v10, v141020; CHECK-NEXT: vmand.mm v8, v8, v121021; CHECK-NEXT: vmand.mm v9, v9, v131022; CHECK-NEXT: vmand.mm v11, v0, v111023; CHECK-NEXT: vmand.mm v8, v8, v101024; CHECK-NEXT: vmand.mm v9, v11, v91025; CHECK-NEXT: vmnand.mm v8, v9, v81026; CHECK-NEXT: vcpop.m a0, v81027; CHECK-NEXT: seqz a0, a01028; CHECK-NEXT: ret1029 %red = call i1 @llvm.vector.reduce.smax.v1024i1(<1024 x i1> %v)1030 ret i1 %red1031}1032 1033define zeroext i1 @vreduce_umin_v1024i1(<1024 x i1> %v) {1034; CHECK-LABEL: vreduce_umin_v1024i1:1035; CHECK: # %bb.0:1036; CHECK-NEXT: li a0, 1281037; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1038; CHECK-NEXT: vmand.mm v10, v10, v141039; CHECK-NEXT: vmand.mm v8, v8, v121040; CHECK-NEXT: vmand.mm v9, v9, v131041; CHECK-NEXT: vmand.mm v11, v0, v111042; CHECK-NEXT: vmand.mm v8, v8, v101043; CHECK-NEXT: vmand.mm v9, v11, v91044; CHECK-NEXT: vmnand.mm v8, v9, v81045; CHECK-NEXT: vcpop.m a0, v81046; CHECK-NEXT: seqz a0, a01047; CHECK-NEXT: ret1048 %red = call i1 @llvm.vector.reduce.umin.v1024i1(<1024 x i1> %v)1049 ret i1 %red1050}1051 1052define zeroext i1 @vreduce_smin_v1024i1(<1024 x i1> %v) {1053; CHECK-LABEL: vreduce_smin_v1024i1:1054; CHECK: # %bb.0:1055; CHECK-NEXT: li a0, 1281056; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1057; CHECK-NEXT: vmor.mm v10, v10, v141058; CHECK-NEXT: vmor.mm v8, v8, v121059; CHECK-NEXT: vmor.mm v9, v9, v131060; CHECK-NEXT: vmor.mm v11, v0, v111061; CHECK-NEXT: vmor.mm v8, v8, v101062; CHECK-NEXT: vmor.mm v9, v11, v91063; CHECK-NEXT: vmor.mm v8, v9, v81064; CHECK-NEXT: vcpop.m a0, v81065; CHECK-NEXT: snez a0, a01066; CHECK-NEXT: ret1067 %red = call i1 @llvm.vector.reduce.smin.v1024i1(<1024 x i1> %v)1068 ret i1 %red1069}1070