894 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vrem_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vrem_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma11; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t12; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t13; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t14; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t15; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t16; CHECK-NEXT: ret17 %v = call <8 x i7> @llvm.vp.srem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)18 ret <8 x i7> %v19}20 21define <2 x i8> @vrem_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: vrem_vv_v2i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma25; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t26; CHECK-NEXT: ret27 %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)28 ret <2 x i8> %v29}30 31define <2 x i8> @vrem_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {32; CHECK-LABEL: vrem_vv_v2i8_unmasked:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma35; CHECK-NEXT: vrem.vv v8, v8, v936; CHECK-NEXT: ret37 %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)38 ret <2 x i8> %v39}40 41define <2 x i8> @vrem_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {42; CHECK-LABEL: vrem_vx_v2i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma45; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t46; CHECK-NEXT: ret47 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 048 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer49 %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)50 ret <2 x i8> %v51}52 53define <2 x i8> @vrem_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {54; CHECK-LABEL: vrem_vx_v2i8_unmasked:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma57; CHECK-NEXT: vrem.vx v8, v8, a058; CHECK-NEXT: ret59 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 060 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer61 %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)62 ret <2 x i8> %v63}64 65define <4 x i8> @vrem_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {66; CHECK-LABEL: vrem_vv_v4i8:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma69; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t70; CHECK-NEXT: ret71 %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)72 ret <4 x i8> %v73}74 75define <4 x i8> @vrem_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {76; CHECK-LABEL: vrem_vv_v4i8_unmasked:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma79; CHECK-NEXT: vrem.vv v8, v8, v980; CHECK-NEXT: ret81 %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)82 ret <4 x i8> %v83}84 85define <4 x i8> @vrem_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: vrem_vx_v4i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma89; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t90; CHECK-NEXT: ret91 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 092 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer93 %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)94 ret <4 x i8> %v95}96 97define <4 x i8> @vrem_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {98; CHECK-LABEL: vrem_vx_v4i8_unmasked:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma101; CHECK-NEXT: vrem.vx v8, v8, a0102; CHECK-NEXT: ret103 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0104 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer105 %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)106 ret <4 x i8> %v107}108 109define <6 x i8> @vrem_vv_v6i8(<6 x i8> %va, <6 x i8> %b, <6 x i1> %m, i32 zeroext %evl) {110; CHECK-LABEL: vrem_vv_v6i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma113; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t114; CHECK-NEXT: ret115 %v = call <6 x i8> @llvm.vp.srem.v6i8(<6 x i8> %va, <6 x i8> %b, <6 x i1> %m, i32 %evl)116 ret <6 x i8> %v117}118 119define <8 x i8> @vrem_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vrem_vv_v8i8:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma123; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t124; CHECK-NEXT: ret125 %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)126 ret <8 x i8> %v127}128 129define <8 x i8> @vrem_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {130; CHECK-LABEL: vrem_vv_v8i8_unmasked:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma133; CHECK-NEXT: vrem.vv v8, v8, v9134; CHECK-NEXT: ret135 %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)136 ret <8 x i8> %v137}138 139define <8 x i8> @vrem_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vrem_vx_v8i8:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma143; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t144; CHECK-NEXT: ret145 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0146 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer147 %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)148 ret <8 x i8> %v149}150 151define <8 x i8> @vrem_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {152; CHECK-LABEL: vrem_vx_v8i8_unmasked:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma155; CHECK-NEXT: vrem.vx v8, v8, a0156; CHECK-NEXT: ret157 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0158 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer159 %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)160 ret <8 x i8> %v161}162 163define <16 x i8> @vrem_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {164; CHECK-LABEL: vrem_vv_v16i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma167; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t168; CHECK-NEXT: ret169 %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)170 ret <16 x i8> %v171}172 173define <16 x i8> @vrem_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {174; CHECK-LABEL: vrem_vv_v16i8_unmasked:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma177; CHECK-NEXT: vrem.vv v8, v8, v9178; CHECK-NEXT: ret179 %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)180 ret <16 x i8> %v181}182 183define <16 x i8> @vrem_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {184; CHECK-LABEL: vrem_vx_v16i8:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma187; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t188; CHECK-NEXT: ret189 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0190 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer191 %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)192 ret <16 x i8> %v193}194 195define <16 x i8> @vrem_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {196; CHECK-LABEL: vrem_vx_v16i8_unmasked:197; CHECK: # %bb.0:198; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma199; CHECK-NEXT: vrem.vx v8, v8, a0200; CHECK-NEXT: ret201 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0202 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer203 %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)204 ret <16 x i8> %v205}206 207define <2 x i16> @vrem_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {208; CHECK-LABEL: vrem_vv_v2i16:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma211; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t212; CHECK-NEXT: ret213 %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)214 ret <2 x i16> %v215}216 217define <2 x i16> @vrem_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {218; CHECK-LABEL: vrem_vv_v2i16_unmasked:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma221; CHECK-NEXT: vrem.vv v8, v8, v9222; CHECK-NEXT: ret223 %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)224 ret <2 x i16> %v225}226 227define <2 x i16> @vrem_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vrem_vx_v2i16:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma231; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t232; CHECK-NEXT: ret233 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0234 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer235 %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)236 ret <2 x i16> %v237}238 239define <2 x i16> @vrem_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {240; CHECK-LABEL: vrem_vx_v2i16_unmasked:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma243; CHECK-NEXT: vrem.vx v8, v8, a0244; CHECK-NEXT: ret245 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0246 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer247 %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)248 ret <2 x i16> %v249}250 251define <4 x i16> @vrem_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vrem_vv_v4i16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma255; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t256; CHECK-NEXT: ret257 %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)258 ret <4 x i16> %v259}260 261define <4 x i16> @vrem_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {262; CHECK-LABEL: vrem_vv_v4i16_unmasked:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma265; CHECK-NEXT: vrem.vv v8, v8, v9266; CHECK-NEXT: ret267 %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)268 ret <4 x i16> %v269}270 271define <4 x i16> @vrem_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vrem_vx_v4i16:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma275; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t276; CHECK-NEXT: ret277 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0278 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer279 %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)280 ret <4 x i16> %v281}282 283define <4 x i16> @vrem_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {284; CHECK-LABEL: vrem_vx_v4i16_unmasked:285; CHECK: # %bb.0:286; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma287; CHECK-NEXT: vrem.vx v8, v8, a0288; CHECK-NEXT: ret289 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0290 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer291 %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)292 ret <4 x i16> %v293}294 295define <8 x i16> @vrem_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {296; CHECK-LABEL: vrem_vv_v8i16:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma299; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t300; CHECK-NEXT: ret301 %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)302 ret <8 x i16> %v303}304 305define <8 x i16> @vrem_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {306; CHECK-LABEL: vrem_vv_v8i16_unmasked:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma309; CHECK-NEXT: vrem.vv v8, v8, v9310; CHECK-NEXT: ret311 %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)312 ret <8 x i16> %v313}314 315define <8 x i16> @vrem_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {316; CHECK-LABEL: vrem_vx_v8i16:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma319; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t320; CHECK-NEXT: ret321 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0322 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer323 %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)324 ret <8 x i16> %v325}326 327define <8 x i16> @vrem_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {328; CHECK-LABEL: vrem_vx_v8i16_unmasked:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma331; CHECK-NEXT: vrem.vx v8, v8, a0332; CHECK-NEXT: ret333 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0334 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer335 %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)336 ret <8 x i16> %v337}338 339define <16 x i16> @vrem_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {340; CHECK-LABEL: vrem_vv_v16i16:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma343; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t344; CHECK-NEXT: ret345 %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)346 ret <16 x i16> %v347}348 349define <16 x i16> @vrem_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {350; CHECK-LABEL: vrem_vv_v16i16_unmasked:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma353; CHECK-NEXT: vrem.vv v8, v8, v10354; CHECK-NEXT: ret355 %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)356 ret <16 x i16> %v357}358 359define <16 x i16> @vrem_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: vrem_vx_v16i16:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma363; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t364; CHECK-NEXT: ret365 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0366 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer367 %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)368 ret <16 x i16> %v369}370 371define <16 x i16> @vrem_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {372; CHECK-LABEL: vrem_vx_v16i16_unmasked:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma375; CHECK-NEXT: vrem.vx v8, v8, a0376; CHECK-NEXT: ret377 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0378 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer379 %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)380 ret <16 x i16> %v381}382 383define <2 x i32> @vrem_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {384; CHECK-LABEL: vrem_vv_v2i32:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma387; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t388; CHECK-NEXT: ret389 %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)390 ret <2 x i32> %v391}392 393define <2 x i32> @vrem_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {394; CHECK-LABEL: vrem_vv_v2i32_unmasked:395; CHECK: # %bb.0:396; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma397; CHECK-NEXT: vrem.vv v8, v8, v9398; CHECK-NEXT: ret399 %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)400 ret <2 x i32> %v401}402 403define <2 x i32> @vrem_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {404; CHECK-LABEL: vrem_vx_v2i32:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma407; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t408; CHECK-NEXT: ret409 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0410 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer411 %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)412 ret <2 x i32> %v413}414 415define <2 x i32> @vrem_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {416; CHECK-LABEL: vrem_vx_v2i32_unmasked:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma419; CHECK-NEXT: vrem.vx v8, v8, a0420; CHECK-NEXT: ret421 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0422 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer423 %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)424 ret <2 x i32> %v425}426 427define <4 x i32> @vrem_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {428; CHECK-LABEL: vrem_vv_v4i32:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma431; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t432; CHECK-NEXT: ret433 %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)434 ret <4 x i32> %v435}436 437define <4 x i32> @vrem_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {438; CHECK-LABEL: vrem_vv_v4i32_unmasked:439; CHECK: # %bb.0:440; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma441; CHECK-NEXT: vrem.vv v8, v8, v9442; CHECK-NEXT: ret443 %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)444 ret <4 x i32> %v445}446 447define <4 x i32> @vrem_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {448; CHECK-LABEL: vrem_vx_v4i32:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma451; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t452; CHECK-NEXT: ret453 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0454 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer455 %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)456 ret <4 x i32> %v457}458 459define <4 x i32> @vrem_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {460; CHECK-LABEL: vrem_vx_v4i32_unmasked:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma463; CHECK-NEXT: vrem.vx v8, v8, a0464; CHECK-NEXT: ret465 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0466 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer467 %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)468 ret <4 x i32> %v469}470 471define <8 x i32> @vrem_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {472; CHECK-LABEL: vrem_vv_v8i32:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma475; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t476; CHECK-NEXT: ret477 %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)478 ret <8 x i32> %v479}480 481define <8 x i32> @vrem_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {482; CHECK-LABEL: vrem_vv_v8i32_unmasked:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma485; CHECK-NEXT: vrem.vv v8, v8, v10486; CHECK-NEXT: ret487 %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)488 ret <8 x i32> %v489}490 491define <8 x i32> @vrem_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {492; CHECK-LABEL: vrem_vx_v8i32:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma495; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t496; CHECK-NEXT: ret497 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0498 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer499 %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)500 ret <8 x i32> %v501}502 503define <8 x i32> @vrem_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {504; CHECK-LABEL: vrem_vx_v8i32_unmasked:505; CHECK: # %bb.0:506; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma507; CHECK-NEXT: vrem.vx v8, v8, a0508; CHECK-NEXT: ret509 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0510 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer511 %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)512 ret <8 x i32> %v513}514 515define <16 x i32> @vrem_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {516; CHECK-LABEL: vrem_vv_v16i32:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma519; CHECK-NEXT: vrem.vv v8, v8, v12, v0.t520; CHECK-NEXT: ret521 %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)522 ret <16 x i32> %v523}524 525define <16 x i32> @vrem_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {526; CHECK-LABEL: vrem_vv_v16i32_unmasked:527; CHECK: # %bb.0:528; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma529; CHECK-NEXT: vrem.vv v8, v8, v12530; CHECK-NEXT: ret531 %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)532 ret <16 x i32> %v533}534 535define <16 x i32> @vrem_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {536; CHECK-LABEL: vrem_vx_v16i32:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma539; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t540; CHECK-NEXT: ret541 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0542 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer543 %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)544 ret <16 x i32> %v545}546 547define <16 x i32> @vrem_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {548; CHECK-LABEL: vrem_vx_v16i32_unmasked:549; CHECK: # %bb.0:550; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma551; CHECK-NEXT: vrem.vx v8, v8, a0552; CHECK-NEXT: ret553 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0554 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer555 %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)556 ret <16 x i32> %v557}558 559define <2 x i64> @vrem_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {560; CHECK-LABEL: vrem_vv_v2i64:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma563; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t564; CHECK-NEXT: ret565 %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)566 ret <2 x i64> %v567}568 569define <2 x i64> @vrem_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {570; CHECK-LABEL: vrem_vv_v2i64_unmasked:571; CHECK: # %bb.0:572; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma573; CHECK-NEXT: vrem.vv v8, v8, v9574; CHECK-NEXT: ret575 %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)576 ret <2 x i64> %v577}578 579define <2 x i64> @vrem_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {580; RV32-LABEL: vrem_vx_v2i64:581; RV32: # %bb.0:582; RV32-NEXT: addi sp, sp, -16583; RV32-NEXT: .cfi_def_cfa_offset 16584; RV32-NEXT: sw a0, 8(sp)585; RV32-NEXT: sw a1, 12(sp)586; RV32-NEXT: addi a0, sp, 8587; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma588; RV32-NEXT: vlse64.v v9, (a0), zero589; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma590; RV32-NEXT: vrem.vv v8, v8, v9, v0.t591; RV32-NEXT: addi sp, sp, 16592; RV32-NEXT: .cfi_def_cfa_offset 0593; RV32-NEXT: ret594;595; RV64-LABEL: vrem_vx_v2i64:596; RV64: # %bb.0:597; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma598; RV64-NEXT: vrem.vx v8, v8, a0, v0.t599; RV64-NEXT: ret600 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0601 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer602 %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)603 ret <2 x i64> %v604}605 606define <2 x i64> @vrem_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {607; RV32-LABEL: vrem_vx_v2i64_unmasked:608; RV32: # %bb.0:609; RV32-NEXT: addi sp, sp, -16610; RV32-NEXT: .cfi_def_cfa_offset 16611; RV32-NEXT: sw a0, 8(sp)612; RV32-NEXT: sw a1, 12(sp)613; RV32-NEXT: addi a0, sp, 8614; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma615; RV32-NEXT: vlse64.v v9, (a0), zero616; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma617; RV32-NEXT: vrem.vv v8, v8, v9618; RV32-NEXT: addi sp, sp, 16619; RV32-NEXT: .cfi_def_cfa_offset 0620; RV32-NEXT: ret621;622; RV64-LABEL: vrem_vx_v2i64_unmasked:623; RV64: # %bb.0:624; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma625; RV64-NEXT: vrem.vx v8, v8, a0626; RV64-NEXT: ret627 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0628 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer629 %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)630 ret <2 x i64> %v631}632 633define <4 x i64> @vrem_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {634; CHECK-LABEL: vrem_vv_v4i64:635; CHECK: # %bb.0:636; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma637; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t638; CHECK-NEXT: ret639 %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)640 ret <4 x i64> %v641}642 643define <4 x i64> @vrem_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {644; CHECK-LABEL: vrem_vv_v4i64_unmasked:645; CHECK: # %bb.0:646; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma647; CHECK-NEXT: vrem.vv v8, v8, v10648; CHECK-NEXT: ret649 %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)650 ret <4 x i64> %v651}652 653define <4 x i64> @vrem_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {654; RV32-LABEL: vrem_vx_v4i64:655; RV32: # %bb.0:656; RV32-NEXT: addi sp, sp, -16657; RV32-NEXT: .cfi_def_cfa_offset 16658; RV32-NEXT: sw a0, 8(sp)659; RV32-NEXT: sw a1, 12(sp)660; RV32-NEXT: addi a0, sp, 8661; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma662; RV32-NEXT: vlse64.v v10, (a0), zero663; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma664; RV32-NEXT: vrem.vv v8, v8, v10, v0.t665; RV32-NEXT: addi sp, sp, 16666; RV32-NEXT: .cfi_def_cfa_offset 0667; RV32-NEXT: ret668;669; RV64-LABEL: vrem_vx_v4i64:670; RV64: # %bb.0:671; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma672; RV64-NEXT: vrem.vx v8, v8, a0, v0.t673; RV64-NEXT: ret674 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0675 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer676 %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)677 ret <4 x i64> %v678}679 680define <4 x i64> @vrem_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {681; RV32-LABEL: vrem_vx_v4i64_unmasked:682; RV32: # %bb.0:683; RV32-NEXT: addi sp, sp, -16684; RV32-NEXT: .cfi_def_cfa_offset 16685; RV32-NEXT: sw a0, 8(sp)686; RV32-NEXT: sw a1, 12(sp)687; RV32-NEXT: addi a0, sp, 8688; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma689; RV32-NEXT: vlse64.v v10, (a0), zero690; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma691; RV32-NEXT: vrem.vv v8, v8, v10692; RV32-NEXT: addi sp, sp, 16693; RV32-NEXT: .cfi_def_cfa_offset 0694; RV32-NEXT: ret695;696; RV64-LABEL: vrem_vx_v4i64_unmasked:697; RV64: # %bb.0:698; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma699; RV64-NEXT: vrem.vx v8, v8, a0700; RV64-NEXT: ret701 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0702 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer703 %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)704 ret <4 x i64> %v705}706 707define <8 x i64> @vrem_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {708; CHECK-LABEL: vrem_vv_v8i64:709; CHECK: # %bb.0:710; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma711; CHECK-NEXT: vrem.vv v8, v8, v12, v0.t712; CHECK-NEXT: ret713 %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)714 ret <8 x i64> %v715}716 717define <8 x i64> @vrem_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {718; CHECK-LABEL: vrem_vv_v8i64_unmasked:719; CHECK: # %bb.0:720; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma721; CHECK-NEXT: vrem.vv v8, v8, v12722; CHECK-NEXT: ret723 %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)724 ret <8 x i64> %v725}726 727define <8 x i64> @vrem_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {728; RV32-LABEL: vrem_vx_v8i64:729; RV32: # %bb.0:730; RV32-NEXT: addi sp, sp, -16731; RV32-NEXT: .cfi_def_cfa_offset 16732; RV32-NEXT: sw a0, 8(sp)733; RV32-NEXT: sw a1, 12(sp)734; RV32-NEXT: addi a0, sp, 8735; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma736; RV32-NEXT: vlse64.v v12, (a0), zero737; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma738; RV32-NEXT: vrem.vv v8, v8, v12, v0.t739; RV32-NEXT: addi sp, sp, 16740; RV32-NEXT: .cfi_def_cfa_offset 0741; RV32-NEXT: ret742;743; RV64-LABEL: vrem_vx_v8i64:744; RV64: # %bb.0:745; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma746; RV64-NEXT: vrem.vx v8, v8, a0, v0.t747; RV64-NEXT: ret748 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0749 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer750 %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)751 ret <8 x i64> %v752}753 754define <8 x i64> @vrem_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {755; RV32-LABEL: vrem_vx_v8i64_unmasked:756; RV32: # %bb.0:757; RV32-NEXT: addi sp, sp, -16758; RV32-NEXT: .cfi_def_cfa_offset 16759; RV32-NEXT: sw a0, 8(sp)760; RV32-NEXT: sw a1, 12(sp)761; RV32-NEXT: addi a0, sp, 8762; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma763; RV32-NEXT: vlse64.v v12, (a0), zero764; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma765; RV32-NEXT: vrem.vv v8, v8, v12766; RV32-NEXT: addi sp, sp, 16767; RV32-NEXT: .cfi_def_cfa_offset 0768; RV32-NEXT: ret769;770; RV64-LABEL: vrem_vx_v8i64_unmasked:771; RV64: # %bb.0:772; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma773; RV64-NEXT: vrem.vx v8, v8, a0774; RV64-NEXT: ret775 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0776 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer777 %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)778 ret <8 x i64> %v779}780 781define <16 x i64> @vrem_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {782; CHECK-LABEL: vrem_vv_v16i64:783; CHECK: # %bb.0:784; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma785; CHECK-NEXT: vrem.vv v8, v8, v16, v0.t786; CHECK-NEXT: ret787 %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)788 ret <16 x i64> %v789}790 791define <16 x i64> @vrem_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {792; CHECK-LABEL: vrem_vv_v16i64_unmasked:793; CHECK: # %bb.0:794; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma795; CHECK-NEXT: vrem.vv v8, v8, v16796; CHECK-NEXT: ret797 %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)798 ret <16 x i64> %v799}800 801define <16 x i64> @vrem_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {802; RV32-LABEL: vrem_vx_v16i64:803; RV32: # %bb.0:804; RV32-NEXT: addi sp, sp, -16805; RV32-NEXT: .cfi_def_cfa_offset 16806; RV32-NEXT: sw a0, 8(sp)807; RV32-NEXT: sw a1, 12(sp)808; RV32-NEXT: addi a0, sp, 8809; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma810; RV32-NEXT: vlse64.v v16, (a0), zero811; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma812; RV32-NEXT: vrem.vv v8, v8, v16, v0.t813; RV32-NEXT: addi sp, sp, 16814; RV32-NEXT: .cfi_def_cfa_offset 0815; RV32-NEXT: ret816;817; RV64-LABEL: vrem_vx_v16i64:818; RV64: # %bb.0:819; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma820; RV64-NEXT: vrem.vx v8, v8, a0, v0.t821; RV64-NEXT: ret822 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0823 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer824 %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)825 ret <16 x i64> %v826}827 828define <16 x i64> @vrem_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {829; RV32-LABEL: vrem_vx_v16i64_unmasked:830; RV32: # %bb.0:831; RV32-NEXT: addi sp, sp, -16832; RV32-NEXT: .cfi_def_cfa_offset 16833; RV32-NEXT: sw a0, 8(sp)834; RV32-NEXT: sw a1, 12(sp)835; RV32-NEXT: addi a0, sp, 8836; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma837; RV32-NEXT: vlse64.v v16, (a0), zero838; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma839; RV32-NEXT: vrem.vv v8, v8, v16840; RV32-NEXT: addi sp, sp, 16841; RV32-NEXT: .cfi_def_cfa_offset 0842; RV32-NEXT: ret843;844; RV64-LABEL: vrem_vx_v16i64_unmasked:845; RV64: # %bb.0:846; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma847; RV64-NEXT: vrem.vx v8, v8, a0848; RV64-NEXT: ret849 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0850 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer851 %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)852 ret <16 x i64> %v853}854 855define <3 x i8> @vrem_vv_v3i8_unmasked(<3 x i8> %va, <3 x i8> %b, i32 zeroext %evl) {856; CHECK-LABEL: vrem_vv_v3i8_unmasked:857; CHECK: # %bb.0:858; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma859; CHECK-NEXT: vrem.vv v8, v8, v9860; CHECK-NEXT: ret861 %v = call <3 x i8> @llvm.vp.srem.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 %evl)862 ret <3 x i8> %v863}864 865define <3 x i8> @vrem_vv_v3i8_unmasked_avl3(<3 x i8> %va, <3 x i8> %b) {866; CHECK-LABEL: vrem_vv_v3i8_unmasked_avl3:867; CHECK: # %bb.0:868; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma869; CHECK-NEXT: vrem.vv v8, v8, v9870; CHECK-NEXT: ret871 %v = call <3 x i8> @llvm.vp.srem.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 3)872 ret <3 x i8> %v873}874 875define <7 x i8> @vrem_vv_v7i8_unmasked(<7 x i8> %va, <7 x i8> %b, i32 zeroext %evl) {876; CHECK-LABEL: vrem_vv_v7i8_unmasked:877; CHECK: # %bb.0:878; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma879; CHECK-NEXT: vrem.vv v8, v8, v9880; CHECK-NEXT: ret881 %v = call <7 x i8> @llvm.vp.srem.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 %evl)882 ret <7 x i8> %v883}884 885define <7 x i8> @vrem_vv_v7i8_unmasked_avl7(<7 x i8> %va, <7 x i8> %b) {886; CHECK-LABEL: vrem_vv_v7i8_unmasked_avl7:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetivli zero, 7, e8, mf2, ta, ma889; CHECK-NEXT: vrem.vv v8, v8, v9890; CHECK-NEXT: ret891 %v = call <7 x i8> @llvm.vp.srem.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 7)892 ret <7 x i8> %v893}894