893 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vremu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vremu_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: li a1, 12711; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma12; CHECK-NEXT: vand.vx v9, v9, a1, v0.t13; CHECK-NEXT: vand.vx v8, v8, a1, v0.t14; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t15; CHECK-NEXT: ret16 %v = call <8 x i7> @llvm.vp.urem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)17 ret <8 x i7> %v18}19 20define <2 x i8> @vremu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {21; CHECK-LABEL: vremu_vv_v2i8:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma24; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t25; CHECK-NEXT: ret26 %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)27 ret <2 x i8> %v28}29 30define <2 x i8> @vremu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {31; CHECK-LABEL: vremu_vv_v2i8_unmasked:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma34; CHECK-NEXT: vremu.vv v8, v8, v935; CHECK-NEXT: ret36 %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)37 ret <2 x i8> %v38}39 40define <2 x i8> @vremu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {41; CHECK-LABEL: vremu_vx_v2i8:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma44; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t45; CHECK-NEXT: ret46 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 047 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer48 %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)49 ret <2 x i8> %v50}51 52define <2 x i8> @vremu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {53; CHECK-LABEL: vremu_vx_v2i8_unmasked:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma56; CHECK-NEXT: vremu.vx v8, v8, a057; CHECK-NEXT: ret58 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 059 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer60 %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)61 ret <2 x i8> %v62}63 64define <4 x i8> @vremu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {65; CHECK-LABEL: vremu_vv_v4i8:66; CHECK: # %bb.0:67; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma68; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t69; CHECK-NEXT: ret70 %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)71 ret <4 x i8> %v72}73 74define <4 x i8> @vremu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {75; CHECK-LABEL: vremu_vv_v4i8_unmasked:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma78; CHECK-NEXT: vremu.vv v8, v8, v979; CHECK-NEXT: ret80 %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)81 ret <4 x i8> %v82}83 84define <4 x i8> @vremu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {85; CHECK-LABEL: vremu_vx_v4i8:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma88; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t89; CHECK-NEXT: ret90 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 091 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer92 %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)93 ret <4 x i8> %v94}95 96define <4 x i8> @vremu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {97; CHECK-LABEL: vremu_vx_v4i8_unmasked:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma100; CHECK-NEXT: vremu.vx v8, v8, a0101; CHECK-NEXT: ret102 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0103 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer104 %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)105 ret <4 x i8> %v106}107 108define <6 x i8> @vremu_vv_v6i8(<6 x i8> %va, <6 x i8> %b, <6 x i1> %m, i32 zeroext %evl) {109; CHECK-LABEL: vremu_vv_v6i8:110; CHECK: # %bb.0:111; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma112; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t113; CHECK-NEXT: ret114 %v = call <6 x i8> @llvm.vp.urem.v6i8(<6 x i8> %va, <6 x i8> %b, <6 x i1> %m, i32 %evl)115 ret <6 x i8> %v116}117 118define <8 x i8> @vremu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {119; CHECK-LABEL: vremu_vv_v8i8:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma122; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t123; CHECK-NEXT: ret124 %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)125 ret <8 x i8> %v126}127 128define <8 x i8> @vremu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {129; CHECK-LABEL: vremu_vv_v8i8_unmasked:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma132; CHECK-NEXT: vremu.vv v8, v8, v9133; CHECK-NEXT: ret134 %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)135 ret <8 x i8> %v136}137 138define <8 x i8> @vremu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {139; CHECK-LABEL: vremu_vx_v8i8:140; CHECK: # %bb.0:141; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma142; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t143; CHECK-NEXT: ret144 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0145 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer146 %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)147 ret <8 x i8> %v148}149 150define <8 x i8> @vremu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {151; CHECK-LABEL: vremu_vx_v8i8_unmasked:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma154; CHECK-NEXT: vremu.vx v8, v8, a0155; CHECK-NEXT: ret156 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0157 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer158 %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)159 ret <8 x i8> %v160}161 162define <16 x i8> @vremu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {163; CHECK-LABEL: vremu_vv_v16i8:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma166; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t167; CHECK-NEXT: ret168 %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)169 ret <16 x i8> %v170}171 172define <16 x i8> @vremu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {173; CHECK-LABEL: vremu_vv_v16i8_unmasked:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma176; CHECK-NEXT: vremu.vv v8, v8, v9177; CHECK-NEXT: ret178 %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)179 ret <16 x i8> %v180}181 182define <16 x i8> @vremu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {183; CHECK-LABEL: vremu_vx_v16i8:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma186; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t187; CHECK-NEXT: ret188 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0189 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer190 %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)191 ret <16 x i8> %v192}193 194define <16 x i8> @vremu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {195; CHECK-LABEL: vremu_vx_v16i8_unmasked:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma198; CHECK-NEXT: vremu.vx v8, v8, a0199; CHECK-NEXT: ret200 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0201 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer202 %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)203 ret <16 x i8> %v204}205 206define <2 x i16> @vremu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {207; CHECK-LABEL: vremu_vv_v2i16:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma210; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t211; CHECK-NEXT: ret212 %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)213 ret <2 x i16> %v214}215 216define <2 x i16> @vremu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {217; CHECK-LABEL: vremu_vv_v2i16_unmasked:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma220; CHECK-NEXT: vremu.vv v8, v8, v9221; CHECK-NEXT: ret222 %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)223 ret <2 x i16> %v224}225 226define <2 x i16> @vremu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {227; CHECK-LABEL: vremu_vx_v2i16:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma230; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t231; CHECK-NEXT: ret232 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0233 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer234 %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)235 ret <2 x i16> %v236}237 238define <2 x i16> @vremu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {239; CHECK-LABEL: vremu_vx_v2i16_unmasked:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma242; CHECK-NEXT: vremu.vx v8, v8, a0243; CHECK-NEXT: ret244 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0245 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer246 %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)247 ret <2 x i16> %v248}249 250define <4 x i16> @vremu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {251; CHECK-LABEL: vremu_vv_v4i16:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma254; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t255; CHECK-NEXT: ret256 %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)257 ret <4 x i16> %v258}259 260define <4 x i16> @vremu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {261; CHECK-LABEL: vremu_vv_v4i16_unmasked:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma264; CHECK-NEXT: vremu.vv v8, v8, v9265; CHECK-NEXT: ret266 %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)267 ret <4 x i16> %v268}269 270define <4 x i16> @vremu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {271; CHECK-LABEL: vremu_vx_v4i16:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma274; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t275; CHECK-NEXT: ret276 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0277 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer278 %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)279 ret <4 x i16> %v280}281 282define <4 x i16> @vremu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {283; CHECK-LABEL: vremu_vx_v4i16_unmasked:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma286; CHECK-NEXT: vremu.vx v8, v8, a0287; CHECK-NEXT: ret288 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0289 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer290 %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)291 ret <4 x i16> %v292}293 294define <8 x i16> @vremu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {295; CHECK-LABEL: vremu_vv_v8i16:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma298; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t299; CHECK-NEXT: ret300 %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)301 ret <8 x i16> %v302}303 304define <8 x i16> @vremu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {305; CHECK-LABEL: vremu_vv_v8i16_unmasked:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma308; CHECK-NEXT: vremu.vv v8, v8, v9309; CHECK-NEXT: ret310 %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)311 ret <8 x i16> %v312}313 314define <8 x i16> @vremu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {315; CHECK-LABEL: vremu_vx_v8i16:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma318; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t319; CHECK-NEXT: ret320 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0321 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer322 %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)323 ret <8 x i16> %v324}325 326define <8 x i16> @vremu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {327; CHECK-LABEL: vremu_vx_v8i16_unmasked:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma330; CHECK-NEXT: vremu.vx v8, v8, a0331; CHECK-NEXT: ret332 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0333 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer334 %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)335 ret <8 x i16> %v336}337 338define <16 x i16> @vremu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {339; CHECK-LABEL: vremu_vv_v16i16:340; CHECK: # %bb.0:341; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma342; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t343; CHECK-NEXT: ret344 %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)345 ret <16 x i16> %v346}347 348define <16 x i16> @vremu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {349; CHECK-LABEL: vremu_vv_v16i16_unmasked:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma352; CHECK-NEXT: vremu.vv v8, v8, v10353; CHECK-NEXT: ret354 %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)355 ret <16 x i16> %v356}357 358define <16 x i16> @vremu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {359; CHECK-LABEL: vremu_vx_v16i16:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma362; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t363; CHECK-NEXT: ret364 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0365 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer366 %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)367 ret <16 x i16> %v368}369 370define <16 x i16> @vremu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {371; CHECK-LABEL: vremu_vx_v16i16_unmasked:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma374; CHECK-NEXT: vremu.vx v8, v8, a0375; CHECK-NEXT: ret376 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0377 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer378 %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)379 ret <16 x i16> %v380}381 382define <2 x i32> @vremu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {383; CHECK-LABEL: vremu_vv_v2i32:384; CHECK: # %bb.0:385; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma386; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t387; CHECK-NEXT: ret388 %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)389 ret <2 x i32> %v390}391 392define <2 x i32> @vremu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {393; CHECK-LABEL: vremu_vv_v2i32_unmasked:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma396; CHECK-NEXT: vremu.vv v8, v8, v9397; CHECK-NEXT: ret398 %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)399 ret <2 x i32> %v400}401 402define <2 x i32> @vremu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {403; CHECK-LABEL: vremu_vx_v2i32:404; CHECK: # %bb.0:405; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma406; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t407; CHECK-NEXT: ret408 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0409 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer410 %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)411 ret <2 x i32> %v412}413 414define <2 x i32> @vremu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {415; CHECK-LABEL: vremu_vx_v2i32_unmasked:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma418; CHECK-NEXT: vremu.vx v8, v8, a0419; CHECK-NEXT: ret420 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0421 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer422 %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)423 ret <2 x i32> %v424}425 426define <4 x i32> @vremu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {427; CHECK-LABEL: vremu_vv_v4i32:428; CHECK: # %bb.0:429; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma430; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t431; CHECK-NEXT: ret432 %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)433 ret <4 x i32> %v434}435 436define <4 x i32> @vremu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {437; CHECK-LABEL: vremu_vv_v4i32_unmasked:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma440; CHECK-NEXT: vremu.vv v8, v8, v9441; CHECK-NEXT: ret442 %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)443 ret <4 x i32> %v444}445 446define <4 x i32> @vremu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {447; CHECK-LABEL: vremu_vx_v4i32:448; CHECK: # %bb.0:449; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma450; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t451; CHECK-NEXT: ret452 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0453 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer454 %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)455 ret <4 x i32> %v456}457 458define <4 x i32> @vremu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {459; CHECK-LABEL: vremu_vx_v4i32_unmasked:460; CHECK: # %bb.0:461; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma462; CHECK-NEXT: vremu.vx v8, v8, a0463; CHECK-NEXT: ret464 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0465 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer466 %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)467 ret <4 x i32> %v468}469 470define <8 x i32> @vremu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {471; CHECK-LABEL: vremu_vv_v8i32:472; CHECK: # %bb.0:473; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma474; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t475; CHECK-NEXT: ret476 %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)477 ret <8 x i32> %v478}479 480define <8 x i32> @vremu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {481; CHECK-LABEL: vremu_vv_v8i32_unmasked:482; CHECK: # %bb.0:483; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma484; CHECK-NEXT: vremu.vv v8, v8, v10485; CHECK-NEXT: ret486 %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)487 ret <8 x i32> %v488}489 490define <8 x i32> @vremu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {491; CHECK-LABEL: vremu_vx_v8i32:492; CHECK: # %bb.0:493; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma494; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t495; CHECK-NEXT: ret496 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0497 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer498 %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)499 ret <8 x i32> %v500}501 502define <8 x i32> @vremu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {503; CHECK-LABEL: vremu_vx_v8i32_unmasked:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma506; CHECK-NEXT: vremu.vx v8, v8, a0507; CHECK-NEXT: ret508 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0509 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer510 %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)511 ret <8 x i32> %v512}513 514define <16 x i32> @vremu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {515; CHECK-LABEL: vremu_vv_v16i32:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma518; CHECK-NEXT: vremu.vv v8, v8, v12, v0.t519; CHECK-NEXT: ret520 %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)521 ret <16 x i32> %v522}523 524define <16 x i32> @vremu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {525; CHECK-LABEL: vremu_vv_v16i32_unmasked:526; CHECK: # %bb.0:527; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma528; CHECK-NEXT: vremu.vv v8, v8, v12529; CHECK-NEXT: ret530 %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)531 ret <16 x i32> %v532}533 534define <16 x i32> @vremu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {535; CHECK-LABEL: vremu_vx_v16i32:536; CHECK: # %bb.0:537; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma538; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t539; CHECK-NEXT: ret540 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0541 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer542 %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)543 ret <16 x i32> %v544}545 546define <16 x i32> @vremu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {547; CHECK-LABEL: vremu_vx_v16i32_unmasked:548; CHECK: # %bb.0:549; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma550; CHECK-NEXT: vremu.vx v8, v8, a0551; CHECK-NEXT: ret552 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0553 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer554 %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)555 ret <16 x i32> %v556}557 558define <2 x i64> @vremu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {559; CHECK-LABEL: vremu_vv_v2i64:560; CHECK: # %bb.0:561; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma562; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t563; CHECK-NEXT: ret564 %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)565 ret <2 x i64> %v566}567 568define <2 x i64> @vremu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {569; CHECK-LABEL: vremu_vv_v2i64_unmasked:570; CHECK: # %bb.0:571; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma572; CHECK-NEXT: vremu.vv v8, v8, v9573; CHECK-NEXT: ret574 %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)575 ret <2 x i64> %v576}577 578define <2 x i64> @vremu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {579; RV32-LABEL: vremu_vx_v2i64:580; RV32: # %bb.0:581; RV32-NEXT: addi sp, sp, -16582; RV32-NEXT: .cfi_def_cfa_offset 16583; RV32-NEXT: sw a0, 8(sp)584; RV32-NEXT: sw a1, 12(sp)585; RV32-NEXT: addi a0, sp, 8586; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma587; RV32-NEXT: vlse64.v v9, (a0), zero588; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma589; RV32-NEXT: vremu.vv v8, v8, v9, v0.t590; RV32-NEXT: addi sp, sp, 16591; RV32-NEXT: .cfi_def_cfa_offset 0592; RV32-NEXT: ret593;594; RV64-LABEL: vremu_vx_v2i64:595; RV64: # %bb.0:596; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma597; RV64-NEXT: vremu.vx v8, v8, a0, v0.t598; RV64-NEXT: ret599 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0600 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer601 %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)602 ret <2 x i64> %v603}604 605define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {606; RV32-LABEL: vremu_vx_v2i64_unmasked:607; RV32: # %bb.0:608; RV32-NEXT: addi sp, sp, -16609; RV32-NEXT: .cfi_def_cfa_offset 16610; RV32-NEXT: sw a0, 8(sp)611; RV32-NEXT: sw a1, 12(sp)612; RV32-NEXT: addi a0, sp, 8613; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma614; RV32-NEXT: vlse64.v v9, (a0), zero615; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma616; RV32-NEXT: vremu.vv v8, v8, v9617; RV32-NEXT: addi sp, sp, 16618; RV32-NEXT: .cfi_def_cfa_offset 0619; RV32-NEXT: ret620;621; RV64-LABEL: vremu_vx_v2i64_unmasked:622; RV64: # %bb.0:623; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma624; RV64-NEXT: vremu.vx v8, v8, a0625; RV64-NEXT: ret626 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0627 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer628 %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)629 ret <2 x i64> %v630}631 632define <4 x i64> @vremu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {633; CHECK-LABEL: vremu_vv_v4i64:634; CHECK: # %bb.0:635; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma636; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t637; CHECK-NEXT: ret638 %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)639 ret <4 x i64> %v640}641 642define <4 x i64> @vremu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {643; CHECK-LABEL: vremu_vv_v4i64_unmasked:644; CHECK: # %bb.0:645; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma646; CHECK-NEXT: vremu.vv v8, v8, v10647; CHECK-NEXT: ret648 %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)649 ret <4 x i64> %v650}651 652define <4 x i64> @vremu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {653; RV32-LABEL: vremu_vx_v4i64:654; RV32: # %bb.0:655; RV32-NEXT: addi sp, sp, -16656; RV32-NEXT: .cfi_def_cfa_offset 16657; RV32-NEXT: sw a0, 8(sp)658; RV32-NEXT: sw a1, 12(sp)659; RV32-NEXT: addi a0, sp, 8660; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma661; RV32-NEXT: vlse64.v v10, (a0), zero662; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma663; RV32-NEXT: vremu.vv v8, v8, v10, v0.t664; RV32-NEXT: addi sp, sp, 16665; RV32-NEXT: .cfi_def_cfa_offset 0666; RV32-NEXT: ret667;668; RV64-LABEL: vremu_vx_v4i64:669; RV64: # %bb.0:670; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma671; RV64-NEXT: vremu.vx v8, v8, a0, v0.t672; RV64-NEXT: ret673 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0674 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer675 %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)676 ret <4 x i64> %v677}678 679define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {680; RV32-LABEL: vremu_vx_v4i64_unmasked:681; RV32: # %bb.0:682; RV32-NEXT: addi sp, sp, -16683; RV32-NEXT: .cfi_def_cfa_offset 16684; RV32-NEXT: sw a0, 8(sp)685; RV32-NEXT: sw a1, 12(sp)686; RV32-NEXT: addi a0, sp, 8687; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma688; RV32-NEXT: vlse64.v v10, (a0), zero689; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma690; RV32-NEXT: vremu.vv v8, v8, v10691; RV32-NEXT: addi sp, sp, 16692; RV32-NEXT: .cfi_def_cfa_offset 0693; RV32-NEXT: ret694;695; RV64-LABEL: vremu_vx_v4i64_unmasked:696; RV64: # %bb.0:697; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma698; RV64-NEXT: vremu.vx v8, v8, a0699; RV64-NEXT: ret700 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0701 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer702 %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)703 ret <4 x i64> %v704}705 706define <8 x i64> @vremu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {707; CHECK-LABEL: vremu_vv_v8i64:708; CHECK: # %bb.0:709; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma710; CHECK-NEXT: vremu.vv v8, v8, v12, v0.t711; CHECK-NEXT: ret712 %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)713 ret <8 x i64> %v714}715 716define <8 x i64> @vremu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {717; CHECK-LABEL: vremu_vv_v8i64_unmasked:718; CHECK: # %bb.0:719; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma720; CHECK-NEXT: vremu.vv v8, v8, v12721; CHECK-NEXT: ret722 %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)723 ret <8 x i64> %v724}725 726define <8 x i64> @vremu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {727; RV32-LABEL: vremu_vx_v8i64:728; RV32: # %bb.0:729; RV32-NEXT: addi sp, sp, -16730; RV32-NEXT: .cfi_def_cfa_offset 16731; RV32-NEXT: sw a0, 8(sp)732; RV32-NEXT: sw a1, 12(sp)733; RV32-NEXT: addi a0, sp, 8734; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma735; RV32-NEXT: vlse64.v v12, (a0), zero736; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma737; RV32-NEXT: vremu.vv v8, v8, v12, v0.t738; RV32-NEXT: addi sp, sp, 16739; RV32-NEXT: .cfi_def_cfa_offset 0740; RV32-NEXT: ret741;742; RV64-LABEL: vremu_vx_v8i64:743; RV64: # %bb.0:744; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma745; RV64-NEXT: vremu.vx v8, v8, a0, v0.t746; RV64-NEXT: ret747 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0748 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer749 %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)750 ret <8 x i64> %v751}752 753define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {754; RV32-LABEL: vremu_vx_v8i64_unmasked:755; RV32: # %bb.0:756; RV32-NEXT: addi sp, sp, -16757; RV32-NEXT: .cfi_def_cfa_offset 16758; RV32-NEXT: sw a0, 8(sp)759; RV32-NEXT: sw a1, 12(sp)760; RV32-NEXT: addi a0, sp, 8761; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma762; RV32-NEXT: vlse64.v v12, (a0), zero763; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma764; RV32-NEXT: vremu.vv v8, v8, v12765; RV32-NEXT: addi sp, sp, 16766; RV32-NEXT: .cfi_def_cfa_offset 0767; RV32-NEXT: ret768;769; RV64-LABEL: vremu_vx_v8i64_unmasked:770; RV64: # %bb.0:771; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma772; RV64-NEXT: vremu.vx v8, v8, a0773; RV64-NEXT: ret774 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0775 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer776 %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)777 ret <8 x i64> %v778}779 780define <16 x i64> @vremu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {781; CHECK-LABEL: vremu_vv_v16i64:782; CHECK: # %bb.0:783; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma784; CHECK-NEXT: vremu.vv v8, v8, v16, v0.t785; CHECK-NEXT: ret786 %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)787 ret <16 x i64> %v788}789 790define <16 x i64> @vremu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {791; CHECK-LABEL: vremu_vv_v16i64_unmasked:792; CHECK: # %bb.0:793; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma794; CHECK-NEXT: vremu.vv v8, v8, v16795; CHECK-NEXT: ret796 %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)797 ret <16 x i64> %v798}799 800define <16 x i64> @vremu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {801; RV32-LABEL: vremu_vx_v16i64:802; RV32: # %bb.0:803; RV32-NEXT: addi sp, sp, -16804; RV32-NEXT: .cfi_def_cfa_offset 16805; RV32-NEXT: sw a0, 8(sp)806; RV32-NEXT: sw a1, 12(sp)807; RV32-NEXT: addi a0, sp, 8808; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma809; RV32-NEXT: vlse64.v v16, (a0), zero810; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma811; RV32-NEXT: vremu.vv v8, v8, v16, v0.t812; RV32-NEXT: addi sp, sp, 16813; RV32-NEXT: .cfi_def_cfa_offset 0814; RV32-NEXT: ret815;816; RV64-LABEL: vremu_vx_v16i64:817; RV64: # %bb.0:818; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma819; RV64-NEXT: vremu.vx v8, v8, a0, v0.t820; RV64-NEXT: ret821 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0822 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer823 %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)824 ret <16 x i64> %v825}826 827define <16 x i64> @vremu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {828; RV32-LABEL: vremu_vx_v16i64_unmasked:829; RV32: # %bb.0:830; RV32-NEXT: addi sp, sp, -16831; RV32-NEXT: .cfi_def_cfa_offset 16832; RV32-NEXT: sw a0, 8(sp)833; RV32-NEXT: sw a1, 12(sp)834; RV32-NEXT: addi a0, sp, 8835; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma836; RV32-NEXT: vlse64.v v16, (a0), zero837; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma838; RV32-NEXT: vremu.vv v8, v8, v16839; RV32-NEXT: addi sp, sp, 16840; RV32-NEXT: .cfi_def_cfa_offset 0841; RV32-NEXT: ret842;843; RV64-LABEL: vremu_vx_v16i64_unmasked:844; RV64: # %bb.0:845; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma846; RV64-NEXT: vremu.vx v8, v8, a0847; RV64-NEXT: ret848 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0849 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer850 %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)851 ret <16 x i64> %v852}853 854define <3 x i8> @vremu_vv_v3i8_unmasked(<3 x i8> %va, <3 x i8> %b, i32 zeroext %evl) {855; CHECK-LABEL: vremu_vv_v3i8_unmasked:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma858; CHECK-NEXT: vremu.vv v8, v8, v9859; CHECK-NEXT: ret860 %v = call <3 x i8> @llvm.vp.urem.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 %evl)861 ret <3 x i8> %v862}863 864define <3 x i8> @vremu_vv_v3i8_unmasked_avl3(<3 x i8> %va, <3 x i8> %b) {865; CHECK-LABEL: vremu_vv_v3i8_unmasked_avl3:866; CHECK: # %bb.0:867; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma868; CHECK-NEXT: vremu.vv v8, v8, v9869; CHECK-NEXT: ret870 %v = call <3 x i8> @llvm.vp.urem.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 3)871 ret <3 x i8> %v872}873 874define <7 x i8> @vremu_vv_v7i8_unmasked(<7 x i8> %va, <7 x i8> %b, i32 zeroext %evl) {875; CHECK-LABEL: vremu_vv_v7i8_unmasked:876; CHECK: # %bb.0:877; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma878; CHECK-NEXT: vremu.vv v8, v8, v9879; CHECK-NEXT: ret880 %v = call <7 x i8> @llvm.vp.urem.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 %evl)881 ret <7 x i8> %v882}883 884define <7 x i8> @vremu_vv_v7i8_unmasked_avl7(<7 x i8> %va, <7 x i8> %b) {885; CHECK-LABEL: vremu_vv_v7i8_unmasked_avl7:886; CHECK: # %bb.0:887; CHECK-NEXT: vsetivli zero, 7, e8, mf2, ta, ma888; CHECK-NEXT: vremu.vv v8, v8, v9889; CHECK-NEXT: ret890 %v = call <7 x i8> @llvm.vp.urem.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 7)891 ret <7 x i8> %v892}893