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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB6 7define <1 x i8> @vrol_vv_v1i8(<1 x i8> %a, <1 x i8> %b) {8; CHECK-LABEL: vrol_vv_v1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma11; CHECK-NEXT: vand.vi v10, v9, 712; CHECK-NEXT: vrsub.vi v9, v9, 013; CHECK-NEXT: vsll.vv v10, v8, v1014; CHECK-NEXT: vand.vi v9, v9, 715; CHECK-NEXT: vsrl.vv v8, v8, v916; CHECK-NEXT: vor.vv v8, v10, v817; CHECK-NEXT: ret18;19; CHECK-ZVKB-LABEL: vrol_vv_v1i8:20; CHECK-ZVKB: # %bb.0:21; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma22; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v923; CHECK-ZVKB-NEXT: ret24 %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b)25 ret <1 x i8> %x26}27 28define <1 x i8> @vrol_vx_v1i8(<1 x i8> %a, i8 %b) {29; CHECK-LABEL: vrol_vx_v1i8:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma32; CHECK-NEXT: vmv.s.x v9, a033; CHECK-NEXT: vand.vi v10, v9, 734; CHECK-NEXT: vrsub.vi v9, v9, 035; CHECK-NEXT: vsll.vv v10, v8, v1036; CHECK-NEXT: vand.vi v9, v9, 737; CHECK-NEXT: vsrl.vv v8, v8, v938; CHECK-NEXT: vor.vv v8, v10, v839; CHECK-NEXT: ret40;41; CHECK-ZVKB-LABEL: vrol_vx_v1i8:42; CHECK-ZVKB: # %bb.0:43; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma44; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a045; CHECK-ZVKB-NEXT: ret46 %b.head = insertelement <1 x i8> poison, i8 %b, i32 047 %b.splat = shufflevector <1 x i8> %b.head, <1 x i8> poison, <1 x i32> zeroinitializer48 %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b.splat)49 ret <1 x i8> %x50}51 52define <2 x i8> @vrol_vv_v2i8(<2 x i8> %a, <2 x i8> %b) {53; CHECK-LABEL: vrol_vv_v2i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma56; CHECK-NEXT: vand.vi v10, v9, 757; CHECK-NEXT: vrsub.vi v9, v9, 058; CHECK-NEXT: vsll.vv v10, v8, v1059; CHECK-NEXT: vand.vi v9, v9, 760; CHECK-NEXT: vsrl.vv v8, v8, v961; CHECK-NEXT: vor.vv v8, v10, v862; CHECK-NEXT: ret63;64; CHECK-ZVKB-LABEL: vrol_vv_v2i8:65; CHECK-ZVKB: # %bb.0:66; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma67; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v968; CHECK-ZVKB-NEXT: ret69 %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b)70 ret <2 x i8> %x71}72 73define <2 x i8> @vrol_vx_v2i8(<2 x i8> %a, i8 %b) {74; CHECK-LABEL: vrol_vx_v2i8:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma77; CHECK-NEXT: vmv.v.x v9, a078; CHECK-NEXT: vand.vi v10, v9, 779; CHECK-NEXT: vrsub.vi v9, v9, 080; CHECK-NEXT: vsll.vv v10, v8, v1081; CHECK-NEXT: vand.vi v9, v9, 782; CHECK-NEXT: vsrl.vv v8, v8, v983; CHECK-NEXT: vor.vv v8, v10, v884; CHECK-NEXT: ret85;86; CHECK-ZVKB-LABEL: vrol_vx_v2i8:87; CHECK-ZVKB: # %bb.0:88; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma89; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a090; CHECK-ZVKB-NEXT: ret91 %b.head = insertelement <2 x i8> poison, i8 %b, i32 092 %b.splat = shufflevector <2 x i8> %b.head, <2 x i8> poison, <2 x i32> zeroinitializer93 %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b.splat)94 ret <2 x i8> %x95}96 97define <4 x i8> @vrol_vv_v4i8(<4 x i8> %a, <4 x i8> %b) {98; CHECK-LABEL: vrol_vv_v4i8:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma101; CHECK-NEXT: vand.vi v10, v9, 7102; CHECK-NEXT: vrsub.vi v9, v9, 0103; CHECK-NEXT: vsll.vv v10, v8, v10104; CHECK-NEXT: vand.vi v9, v9, 7105; CHECK-NEXT: vsrl.vv v8, v8, v9106; CHECK-NEXT: vor.vv v8, v10, v8107; CHECK-NEXT: ret108;109; CHECK-ZVKB-LABEL: vrol_vv_v4i8:110; CHECK-ZVKB: # %bb.0:111; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma112; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9113; CHECK-ZVKB-NEXT: ret114 %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b)115 ret <4 x i8> %x116}117 118define <4 x i8> @vrol_vx_v4i8(<4 x i8> %a, i8 %b) {119; CHECK-LABEL: vrol_vx_v4i8:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma122; CHECK-NEXT: vmv.v.x v9, a0123; CHECK-NEXT: vand.vi v10, v9, 7124; CHECK-NEXT: vrsub.vi v9, v9, 0125; CHECK-NEXT: vsll.vv v10, v8, v10126; CHECK-NEXT: vand.vi v9, v9, 7127; CHECK-NEXT: vsrl.vv v8, v8, v9128; CHECK-NEXT: vor.vv v8, v10, v8129; CHECK-NEXT: ret130;131; CHECK-ZVKB-LABEL: vrol_vx_v4i8:132; CHECK-ZVKB: # %bb.0:133; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma134; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0135; CHECK-ZVKB-NEXT: ret136 %b.head = insertelement <4 x i8> poison, i8 %b, i32 0137 %b.splat = shufflevector <4 x i8> %b.head, <4 x i8> poison, <4 x i32> zeroinitializer138 %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b.splat)139 ret <4 x i8> %x140}141 142define <8 x i8> @vrol_vv_v8i8(<8 x i8> %a, <8 x i8> %b) {143; CHECK-LABEL: vrol_vv_v8i8:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma146; CHECK-NEXT: vand.vi v10, v9, 7147; CHECK-NEXT: vrsub.vi v9, v9, 0148; CHECK-NEXT: vsll.vv v10, v8, v10149; CHECK-NEXT: vand.vi v9, v9, 7150; CHECK-NEXT: vsrl.vv v8, v8, v9151; CHECK-NEXT: vor.vv v8, v10, v8152; CHECK-NEXT: ret153;154; CHECK-ZVKB-LABEL: vrol_vv_v8i8:155; CHECK-ZVKB: # %bb.0:156; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma157; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9158; CHECK-ZVKB-NEXT: ret159 %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b)160 ret <8 x i8> %x161}162 163define <8 x i8> @vrol_vx_v8i8(<8 x i8> %a, i8 %b) {164; CHECK-LABEL: vrol_vx_v8i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma167; CHECK-NEXT: vmv.v.x v9, a0168; CHECK-NEXT: vand.vi v10, v9, 7169; CHECK-NEXT: vrsub.vi v9, v9, 0170; CHECK-NEXT: vsll.vv v10, v8, v10171; CHECK-NEXT: vand.vi v9, v9, 7172; CHECK-NEXT: vsrl.vv v8, v8, v9173; CHECK-NEXT: vor.vv v8, v10, v8174; CHECK-NEXT: ret175;176; CHECK-ZVKB-LABEL: vrol_vx_v8i8:177; CHECK-ZVKB: # %bb.0:178; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma179; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0180; CHECK-ZVKB-NEXT: ret181 %b.head = insertelement <8 x i8> poison, i8 %b, i32 0182 %b.splat = shufflevector <8 x i8> %b.head, <8 x i8> poison, <8 x i32> zeroinitializer183 %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b.splat)184 ret <8 x i8> %x185}186 187define <16 x i8> @vrol_vv_v16i8(<16 x i8> %a, <16 x i8> %b) {188; CHECK-LABEL: vrol_vv_v16i8:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma191; CHECK-NEXT: vand.vi v10, v9, 7192; CHECK-NEXT: vrsub.vi v9, v9, 0193; CHECK-NEXT: vsll.vv v10, v8, v10194; CHECK-NEXT: vand.vi v9, v9, 7195; CHECK-NEXT: vsrl.vv v8, v8, v9196; CHECK-NEXT: vor.vv v8, v10, v8197; CHECK-NEXT: ret198;199; CHECK-ZVKB-LABEL: vrol_vv_v16i8:200; CHECK-ZVKB: # %bb.0:201; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma202; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9203; CHECK-ZVKB-NEXT: ret204 %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b)205 ret <16 x i8> %x206}207 208define <16 x i8> @vrol_vx_v16i8(<16 x i8> %a, i8 %b) {209; CHECK-LABEL: vrol_vx_v16i8:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma212; CHECK-NEXT: vmv.v.x v9, a0213; CHECK-NEXT: vand.vi v10, v9, 7214; CHECK-NEXT: vrsub.vi v9, v9, 0215; CHECK-NEXT: vsll.vv v10, v8, v10216; CHECK-NEXT: vand.vi v9, v9, 7217; CHECK-NEXT: vsrl.vv v8, v8, v9218; CHECK-NEXT: vor.vv v8, v10, v8219; CHECK-NEXT: ret220;221; CHECK-ZVKB-LABEL: vrol_vx_v16i8:222; CHECK-ZVKB: # %bb.0:223; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma224; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0225; CHECK-ZVKB-NEXT: ret226 %b.head = insertelement <16 x i8> poison, i8 %b, i32 0227 %b.splat = shufflevector <16 x i8> %b.head, <16 x i8> poison, <16 x i32> zeroinitializer228 %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b.splat)229 ret <16 x i8> %x230}231 232define <32 x i8> @vrol_vv_v32i8(<32 x i8> %a, <32 x i8> %b) {233; CHECK-LABEL: vrol_vv_v32i8:234; CHECK: # %bb.0:235; CHECK-NEXT: li a0, 32236; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma237; CHECK-NEXT: vand.vi v12, v10, 7238; CHECK-NEXT: vrsub.vi v10, v10, 0239; CHECK-NEXT: vsll.vv v12, v8, v12240; CHECK-NEXT: vand.vi v10, v10, 7241; CHECK-NEXT: vsrl.vv v8, v8, v10242; CHECK-NEXT: vor.vv v8, v12, v8243; CHECK-NEXT: ret244;245; CHECK-ZVKB-LABEL: vrol_vv_v32i8:246; CHECK-ZVKB: # %bb.0:247; CHECK-ZVKB-NEXT: li a0, 32248; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma249; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10250; CHECK-ZVKB-NEXT: ret251 %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b)252 ret <32 x i8> %x253}254 255define <32 x i8> @vrol_vx_v32i8(<32 x i8> %a, i8 %b) {256; CHECK-LABEL: vrol_vx_v32i8:257; CHECK: # %bb.0:258; CHECK-NEXT: li a1, 32259; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma260; CHECK-NEXT: vmv.v.x v10, a0261; CHECK-NEXT: vand.vi v12, v10, 7262; CHECK-NEXT: vrsub.vi v10, v10, 0263; CHECK-NEXT: vsll.vv v12, v8, v12264; CHECK-NEXT: vand.vi v10, v10, 7265; CHECK-NEXT: vsrl.vv v8, v8, v10266; CHECK-NEXT: vor.vv v8, v12, v8267; CHECK-NEXT: ret268;269; CHECK-ZVKB-LABEL: vrol_vx_v32i8:270; CHECK-ZVKB: # %bb.0:271; CHECK-ZVKB-NEXT: li a1, 32272; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m2, ta, ma273; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0274; CHECK-ZVKB-NEXT: ret275 %b.head = insertelement <32 x i8> poison, i8 %b, i32 0276 %b.splat = shufflevector <32 x i8> %b.head, <32 x i8> poison, <32 x i32> zeroinitializer277 %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b.splat)278 ret <32 x i8> %x279}280 281define <64 x i8> @vrol_vv_v64i8(<64 x i8> %a, <64 x i8> %b) {282; CHECK-LABEL: vrol_vv_v64i8:283; CHECK: # %bb.0:284; CHECK-NEXT: li a0, 64285; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma286; CHECK-NEXT: vand.vi v16, v12, 7287; CHECK-NEXT: vrsub.vi v12, v12, 0288; CHECK-NEXT: vsll.vv v16, v8, v16289; CHECK-NEXT: vand.vi v12, v12, 7290; CHECK-NEXT: vsrl.vv v8, v8, v12291; CHECK-NEXT: vor.vv v8, v16, v8292; CHECK-NEXT: ret293;294; CHECK-ZVKB-LABEL: vrol_vv_v64i8:295; CHECK-ZVKB: # %bb.0:296; CHECK-ZVKB-NEXT: li a0, 64297; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma298; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12299; CHECK-ZVKB-NEXT: ret300 %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b)301 ret <64 x i8> %x302}303 304define <64 x i8> @vrol_vx_v64i8(<64 x i8> %a, i8 %b) {305; CHECK-LABEL: vrol_vx_v64i8:306; CHECK: # %bb.0:307; CHECK-NEXT: li a1, 64308; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma309; CHECK-NEXT: vmv.v.x v12, a0310; CHECK-NEXT: vand.vi v16, v12, 7311; CHECK-NEXT: vrsub.vi v12, v12, 0312; CHECK-NEXT: vsll.vv v16, v8, v16313; CHECK-NEXT: vand.vi v12, v12, 7314; CHECK-NEXT: vsrl.vv v8, v8, v12315; CHECK-NEXT: vor.vv v8, v16, v8316; CHECK-NEXT: ret317;318; CHECK-ZVKB-LABEL: vrol_vx_v64i8:319; CHECK-ZVKB: # %bb.0:320; CHECK-ZVKB-NEXT: li a1, 64321; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m4, ta, ma322; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0323; CHECK-ZVKB-NEXT: ret324 %b.head = insertelement <64 x i8> poison, i8 %b, i32 0325 %b.splat = shufflevector <64 x i8> %b.head, <64 x i8> poison, <64 x i32> zeroinitializer326 %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b.splat)327 ret <64 x i8> %x328}329 330define <1 x i16> @vrol_vv_v1i16(<1 x i16> %a, <1 x i16> %b) {331; CHECK-LABEL: vrol_vv_v1i16:332; CHECK: # %bb.0:333; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma334; CHECK-NEXT: vand.vi v10, v9, 15335; CHECK-NEXT: vrsub.vi v9, v9, 0336; CHECK-NEXT: vsll.vv v10, v8, v10337; CHECK-NEXT: vand.vi v9, v9, 15338; CHECK-NEXT: vsrl.vv v8, v8, v9339; CHECK-NEXT: vor.vv v8, v10, v8340; CHECK-NEXT: ret341;342; CHECK-ZVKB-LABEL: vrol_vv_v1i16:343; CHECK-ZVKB: # %bb.0:344; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma345; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9346; CHECK-ZVKB-NEXT: ret347 %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b)348 ret <1 x i16> %x349}350 351define <1 x i16> @vrol_vx_v1i16(<1 x i16> %a, i16 %b) {352; CHECK-LABEL: vrol_vx_v1i16:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma355; CHECK-NEXT: vmv.s.x v9, a0356; CHECK-NEXT: vand.vi v10, v9, 15357; CHECK-NEXT: vrsub.vi v9, v9, 0358; CHECK-NEXT: vsll.vv v10, v8, v10359; CHECK-NEXT: vand.vi v9, v9, 15360; CHECK-NEXT: vsrl.vv v8, v8, v9361; CHECK-NEXT: vor.vv v8, v10, v8362; CHECK-NEXT: ret363;364; CHECK-ZVKB-LABEL: vrol_vx_v1i16:365; CHECK-ZVKB: # %bb.0:366; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma367; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0368; CHECK-ZVKB-NEXT: ret369 %b.head = insertelement <1 x i16> poison, i16 %b, i32 0370 %b.splat = shufflevector <1 x i16> %b.head, <1 x i16> poison, <1 x i32> zeroinitializer371 %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b.splat)372 ret <1 x i16> %x373}374 375define <2 x i16> @vrol_vv_v2i16(<2 x i16> %a, <2 x i16> %b) {376; CHECK-LABEL: vrol_vv_v2i16:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma379; CHECK-NEXT: vand.vi v10, v9, 15380; CHECK-NEXT: vrsub.vi v9, v9, 0381; CHECK-NEXT: vsll.vv v10, v8, v10382; CHECK-NEXT: vand.vi v9, v9, 15383; CHECK-NEXT: vsrl.vv v8, v8, v9384; CHECK-NEXT: vor.vv v8, v10, v8385; CHECK-NEXT: ret386;387; CHECK-ZVKB-LABEL: vrol_vv_v2i16:388; CHECK-ZVKB: # %bb.0:389; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma390; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9391; CHECK-ZVKB-NEXT: ret392 %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b)393 ret <2 x i16> %x394}395 396define <2 x i16> @vrol_vx_v2i16(<2 x i16> %a, i16 %b) {397; CHECK-LABEL: vrol_vx_v2i16:398; CHECK: # %bb.0:399; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma400; CHECK-NEXT: vmv.v.x v9, a0401; CHECK-NEXT: vand.vi v10, v9, 15402; CHECK-NEXT: vrsub.vi v9, v9, 0403; CHECK-NEXT: vsll.vv v10, v8, v10404; CHECK-NEXT: vand.vi v9, v9, 15405; CHECK-NEXT: vsrl.vv v8, v8, v9406; CHECK-NEXT: vor.vv v8, v10, v8407; CHECK-NEXT: ret408;409; CHECK-ZVKB-LABEL: vrol_vx_v2i16:410; CHECK-ZVKB: # %bb.0:411; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma412; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0413; CHECK-ZVKB-NEXT: ret414 %b.head = insertelement <2 x i16> poison, i16 %b, i32 0415 %b.splat = shufflevector <2 x i16> %b.head, <2 x i16> poison, <2 x i32> zeroinitializer416 %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b.splat)417 ret <2 x i16> %x418}419 420define <4 x i16> @vrol_vv_v4i16(<4 x i16> %a, <4 x i16> %b) {421; CHECK-LABEL: vrol_vv_v4i16:422; CHECK: # %bb.0:423; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma424; CHECK-NEXT: vand.vi v10, v9, 15425; CHECK-NEXT: vrsub.vi v9, v9, 0426; CHECK-NEXT: vsll.vv v10, v8, v10427; CHECK-NEXT: vand.vi v9, v9, 15428; CHECK-NEXT: vsrl.vv v8, v8, v9429; CHECK-NEXT: vor.vv v8, v10, v8430; CHECK-NEXT: ret431;432; CHECK-ZVKB-LABEL: vrol_vv_v4i16:433; CHECK-ZVKB: # %bb.0:434; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma435; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9436; CHECK-ZVKB-NEXT: ret437 %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b)438 ret <4 x i16> %x439}440 441define <4 x i16> @vrol_vx_v4i16(<4 x i16> %a, i16 %b) {442; CHECK-LABEL: vrol_vx_v4i16:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma445; CHECK-NEXT: vmv.v.x v9, a0446; CHECK-NEXT: vand.vi v10, v9, 15447; CHECK-NEXT: vrsub.vi v9, v9, 0448; CHECK-NEXT: vsll.vv v10, v8, v10449; CHECK-NEXT: vand.vi v9, v9, 15450; CHECK-NEXT: vsrl.vv v8, v8, v9451; CHECK-NEXT: vor.vv v8, v10, v8452; CHECK-NEXT: ret453;454; CHECK-ZVKB-LABEL: vrol_vx_v4i16:455; CHECK-ZVKB: # %bb.0:456; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma457; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0458; CHECK-ZVKB-NEXT: ret459 %b.head = insertelement <4 x i16> poison, i16 %b, i32 0460 %b.splat = shufflevector <4 x i16> %b.head, <4 x i16> poison, <4 x i32> zeroinitializer461 %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b.splat)462 ret <4 x i16> %x463}464 465define <8 x i16> @vrol_vv_v8i16(<8 x i16> %a, <8 x i16> %b) {466; CHECK-LABEL: vrol_vv_v8i16:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma469; CHECK-NEXT: vand.vi v10, v9, 15470; CHECK-NEXT: vrsub.vi v9, v9, 0471; CHECK-NEXT: vsll.vv v10, v8, v10472; CHECK-NEXT: vand.vi v9, v9, 15473; CHECK-NEXT: vsrl.vv v8, v8, v9474; CHECK-NEXT: vor.vv v8, v10, v8475; CHECK-NEXT: ret476;477; CHECK-ZVKB-LABEL: vrol_vv_v8i16:478; CHECK-ZVKB: # %bb.0:479; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma480; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9481; CHECK-ZVKB-NEXT: ret482 %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b)483 ret <8 x i16> %x484}485 486define <8 x i16> @vrol_vx_v8i16(<8 x i16> %a, i16 %b) {487; CHECK-LABEL: vrol_vx_v8i16:488; CHECK: # %bb.0:489; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma490; CHECK-NEXT: vmv.v.x v9, a0491; CHECK-NEXT: vand.vi v10, v9, 15492; CHECK-NEXT: vrsub.vi v9, v9, 0493; CHECK-NEXT: vsll.vv v10, v8, v10494; CHECK-NEXT: vand.vi v9, v9, 15495; CHECK-NEXT: vsrl.vv v8, v8, v9496; CHECK-NEXT: vor.vv v8, v10, v8497; CHECK-NEXT: ret498;499; CHECK-ZVKB-LABEL: vrol_vx_v8i16:500; CHECK-ZVKB: # %bb.0:501; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma502; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0503; CHECK-ZVKB-NEXT: ret504 %b.head = insertelement <8 x i16> poison, i16 %b, i32 0505 %b.splat = shufflevector <8 x i16> %b.head, <8 x i16> poison, <8 x i32> zeroinitializer506 %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b.splat)507 ret <8 x i16> %x508}509 510define <16 x i16> @vrol_vv_v16i16(<16 x i16> %a, <16 x i16> %b) {511; CHECK-LABEL: vrol_vv_v16i16:512; CHECK: # %bb.0:513; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma514; CHECK-NEXT: vand.vi v12, v10, 15515; CHECK-NEXT: vrsub.vi v10, v10, 0516; CHECK-NEXT: vsll.vv v12, v8, v12517; CHECK-NEXT: vand.vi v10, v10, 15518; CHECK-NEXT: vsrl.vv v8, v8, v10519; CHECK-NEXT: vor.vv v8, v12, v8520; CHECK-NEXT: ret521;522; CHECK-ZVKB-LABEL: vrol_vv_v16i16:523; CHECK-ZVKB: # %bb.0:524; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma525; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10526; CHECK-ZVKB-NEXT: ret527 %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b)528 ret <16 x i16> %x529}530 531define <16 x i16> @vrol_vx_v16i16(<16 x i16> %a, i16 %b) {532; CHECK-LABEL: vrol_vx_v16i16:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma535; CHECK-NEXT: vmv.v.x v10, a0536; CHECK-NEXT: vand.vi v12, v10, 15537; CHECK-NEXT: vrsub.vi v10, v10, 0538; CHECK-NEXT: vsll.vv v12, v8, v12539; CHECK-NEXT: vand.vi v10, v10, 15540; CHECK-NEXT: vsrl.vv v8, v8, v10541; CHECK-NEXT: vor.vv v8, v12, v8542; CHECK-NEXT: ret543;544; CHECK-ZVKB-LABEL: vrol_vx_v16i16:545; CHECK-ZVKB: # %bb.0:546; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma547; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0548; CHECK-ZVKB-NEXT: ret549 %b.head = insertelement <16 x i16> poison, i16 %b, i32 0550 %b.splat = shufflevector <16 x i16> %b.head, <16 x i16> poison, <16 x i32> zeroinitializer551 %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b.splat)552 ret <16 x i16> %x553}554 555define <32 x i16> @vrol_vv_v32i16(<32 x i16> %a, <32 x i16> %b) {556; CHECK-LABEL: vrol_vv_v32i16:557; CHECK: # %bb.0:558; CHECK-NEXT: li a0, 32559; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma560; CHECK-NEXT: vand.vi v16, v12, 15561; CHECK-NEXT: vrsub.vi v12, v12, 0562; CHECK-NEXT: vsll.vv v16, v8, v16563; CHECK-NEXT: vand.vi v12, v12, 15564; CHECK-NEXT: vsrl.vv v8, v8, v12565; CHECK-NEXT: vor.vv v8, v16, v8566; CHECK-NEXT: ret567;568; CHECK-ZVKB-LABEL: vrol_vv_v32i16:569; CHECK-ZVKB: # %bb.0:570; CHECK-ZVKB-NEXT: li a0, 32571; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma572; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12573; CHECK-ZVKB-NEXT: ret574 %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b)575 ret <32 x i16> %x576}577 578define <32 x i16> @vrol_vx_v32i16(<32 x i16> %a, i16 %b) {579; CHECK-LABEL: vrol_vx_v32i16:580; CHECK: # %bb.0:581; CHECK-NEXT: li a1, 32582; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma583; CHECK-NEXT: vmv.v.x v12, a0584; CHECK-NEXT: vand.vi v16, v12, 15585; CHECK-NEXT: vrsub.vi v12, v12, 0586; CHECK-NEXT: vsll.vv v16, v8, v16587; CHECK-NEXT: vand.vi v12, v12, 15588; CHECK-NEXT: vsrl.vv v8, v8, v12589; CHECK-NEXT: vor.vv v8, v16, v8590; CHECK-NEXT: ret591;592; CHECK-ZVKB-LABEL: vrol_vx_v32i16:593; CHECK-ZVKB: # %bb.0:594; CHECK-ZVKB-NEXT: li a1, 32595; CHECK-ZVKB-NEXT: vsetvli zero, a1, e16, m4, ta, ma596; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0597; CHECK-ZVKB-NEXT: ret598 %b.head = insertelement <32 x i16> poison, i16 %b, i32 0599 %b.splat = shufflevector <32 x i16> %b.head, <32 x i16> poison, <32 x i32> zeroinitializer600 %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b.splat)601 ret <32 x i16> %x602}603 604define <1 x i32> @vrol_vv_v1i32(<1 x i32> %a, <1 x i32> %b) {605; CHECK-LABEL: vrol_vv_v1i32:606; CHECK: # %bb.0:607; CHECK-NEXT: li a0, 31608; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma609; CHECK-NEXT: vrsub.vi v10, v9, 0610; CHECK-NEXT: vand.vx v9, v9, a0611; CHECK-NEXT: vand.vx v10, v10, a0612; CHECK-NEXT: vsll.vv v9, v8, v9613; CHECK-NEXT: vsrl.vv v8, v8, v10614; CHECK-NEXT: vor.vv v8, v9, v8615; CHECK-NEXT: ret616;617; CHECK-ZVKB-LABEL: vrol_vv_v1i32:618; CHECK-ZVKB: # %bb.0:619; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma620; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9621; CHECK-ZVKB-NEXT: ret622 %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b)623 ret <1 x i32> %x624}625 626define <1 x i32> @vrol_vx_v1i32(<1 x i32> %a, i32 %b) {627; CHECK-LABEL: vrol_vx_v1i32:628; CHECK: # %bb.0:629; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma630; CHECK-NEXT: vmv.s.x v9, a0631; CHECK-NEXT: li a0, 31632; CHECK-NEXT: vand.vx v10, v9, a0633; CHECK-NEXT: vrsub.vi v9, v9, 0634; CHECK-NEXT: vsll.vv v10, v8, v10635; CHECK-NEXT: vand.vx v9, v9, a0636; CHECK-NEXT: vsrl.vv v8, v8, v9637; CHECK-NEXT: vor.vv v8, v10, v8638; CHECK-NEXT: ret639;640; CHECK-ZVKB-LABEL: vrol_vx_v1i32:641; CHECK-ZVKB: # %bb.0:642; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma643; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0644; CHECK-ZVKB-NEXT: ret645 %b.head = insertelement <1 x i32> poison, i32 %b, i32 0646 %b.splat = shufflevector <1 x i32> %b.head, <1 x i32> poison, <1 x i32> zeroinitializer647 %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b.splat)648 ret <1 x i32> %x649}650 651define <2 x i32> @vrol_vv_v2i32(<2 x i32> %a, <2 x i32> %b) {652; CHECK-LABEL: vrol_vv_v2i32:653; CHECK: # %bb.0:654; CHECK-NEXT: li a0, 31655; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma656; CHECK-NEXT: vrsub.vi v10, v9, 0657; CHECK-NEXT: vand.vx v9, v9, a0658; CHECK-NEXT: vand.vx v10, v10, a0659; CHECK-NEXT: vsll.vv v9, v8, v9660; CHECK-NEXT: vsrl.vv v8, v8, v10661; CHECK-NEXT: vor.vv v8, v9, v8662; CHECK-NEXT: ret663;664; CHECK-ZVKB-LABEL: vrol_vv_v2i32:665; CHECK-ZVKB: # %bb.0:666; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma667; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9668; CHECK-ZVKB-NEXT: ret669 %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b)670 ret <2 x i32> %x671}672 673define <2 x i32> @vrol_vx_v2i32(<2 x i32> %a, i32 %b) {674; CHECK-LABEL: vrol_vx_v2i32:675; CHECK: # %bb.0:676; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma677; CHECK-NEXT: vmv.v.x v9, a0678; CHECK-NEXT: li a0, 31679; CHECK-NEXT: vand.vx v10, v9, a0680; CHECK-NEXT: vrsub.vi v9, v9, 0681; CHECK-NEXT: vsll.vv v10, v8, v10682; CHECK-NEXT: vand.vx v9, v9, a0683; CHECK-NEXT: vsrl.vv v8, v8, v9684; CHECK-NEXT: vor.vv v8, v10, v8685; CHECK-NEXT: ret686;687; CHECK-ZVKB-LABEL: vrol_vx_v2i32:688; CHECK-ZVKB: # %bb.0:689; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma690; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0691; CHECK-ZVKB-NEXT: ret692 %b.head = insertelement <2 x i32> poison, i32 %b, i32 0693 %b.splat = shufflevector <2 x i32> %b.head, <2 x i32> poison, <2 x i32> zeroinitializer694 %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b.splat)695 ret <2 x i32> %x696}697 698define <4 x i32> @vrol_vv_v4i32(<4 x i32> %a, <4 x i32> %b) {699; CHECK-LABEL: vrol_vv_v4i32:700; CHECK: # %bb.0:701; CHECK-NEXT: li a0, 31702; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma703; CHECK-NEXT: vrsub.vi v10, v9, 0704; CHECK-NEXT: vand.vx v9, v9, a0705; CHECK-NEXT: vand.vx v10, v10, a0706; CHECK-NEXT: vsll.vv v9, v8, v9707; CHECK-NEXT: vsrl.vv v8, v8, v10708; CHECK-NEXT: vor.vv v8, v9, v8709; CHECK-NEXT: ret710;711; CHECK-ZVKB-LABEL: vrol_vv_v4i32:712; CHECK-ZVKB: # %bb.0:713; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma714; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9715; CHECK-ZVKB-NEXT: ret716 %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b)717 ret <4 x i32> %x718}719 720define <4 x i32> @vrol_vx_v4i32(<4 x i32> %a, i32 %b) {721; CHECK-LABEL: vrol_vx_v4i32:722; CHECK: # %bb.0:723; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma724; CHECK-NEXT: vmv.v.x v9, a0725; CHECK-NEXT: li a0, 31726; CHECK-NEXT: vand.vx v10, v9, a0727; CHECK-NEXT: vrsub.vi v9, v9, 0728; CHECK-NEXT: vsll.vv v10, v8, v10729; CHECK-NEXT: vand.vx v9, v9, a0730; CHECK-NEXT: vsrl.vv v8, v8, v9731; CHECK-NEXT: vor.vv v8, v10, v8732; CHECK-NEXT: ret733;734; CHECK-ZVKB-LABEL: vrol_vx_v4i32:735; CHECK-ZVKB: # %bb.0:736; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma737; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0738; CHECK-ZVKB-NEXT: ret739 %b.head = insertelement <4 x i32> poison, i32 %b, i32 0740 %b.splat = shufflevector <4 x i32> %b.head, <4 x i32> poison, <4 x i32> zeroinitializer741 %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b.splat)742 ret <4 x i32> %x743}744 745define <8 x i32> @vrol_vv_v8i32(<8 x i32> %a, <8 x i32> %b) {746; CHECK-LABEL: vrol_vv_v8i32:747; CHECK: # %bb.0:748; CHECK-NEXT: li a0, 31749; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma750; CHECK-NEXT: vrsub.vi v12, v10, 0751; CHECK-NEXT: vand.vx v10, v10, a0752; CHECK-NEXT: vand.vx v12, v12, a0753; CHECK-NEXT: vsll.vv v10, v8, v10754; CHECK-NEXT: vsrl.vv v8, v8, v12755; CHECK-NEXT: vor.vv v8, v10, v8756; CHECK-NEXT: ret757;758; CHECK-ZVKB-LABEL: vrol_vv_v8i32:759; CHECK-ZVKB: # %bb.0:760; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma761; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10762; CHECK-ZVKB-NEXT: ret763 %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b)764 ret <8 x i32> %x765}766 767define <8 x i32> @vrol_vx_v8i32(<8 x i32> %a, i32 %b) {768; CHECK-LABEL: vrol_vx_v8i32:769; CHECK: # %bb.0:770; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma771; CHECK-NEXT: vmv.v.x v10, a0772; CHECK-NEXT: li a0, 31773; CHECK-NEXT: vand.vx v12, v10, a0774; CHECK-NEXT: vrsub.vi v10, v10, 0775; CHECK-NEXT: vsll.vv v12, v8, v12776; CHECK-NEXT: vand.vx v10, v10, a0777; CHECK-NEXT: vsrl.vv v8, v8, v10778; CHECK-NEXT: vor.vv v8, v12, v8779; CHECK-NEXT: ret780;781; CHECK-ZVKB-LABEL: vrol_vx_v8i32:782; CHECK-ZVKB: # %bb.0:783; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma784; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0785; CHECK-ZVKB-NEXT: ret786 %b.head = insertelement <8 x i32> poison, i32 %b, i32 0787 %b.splat = shufflevector <8 x i32> %b.head, <8 x i32> poison, <8 x i32> zeroinitializer788 %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b.splat)789 ret <8 x i32> %x790}791 792define <16 x i32> @vrol_vv_v16i32(<16 x i32> %a, <16 x i32> %b) {793; CHECK-LABEL: vrol_vv_v16i32:794; CHECK: # %bb.0:795; CHECK-NEXT: li a0, 31796; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma797; CHECK-NEXT: vrsub.vi v16, v12, 0798; CHECK-NEXT: vand.vx v12, v12, a0799; CHECK-NEXT: vand.vx v16, v16, a0800; CHECK-NEXT: vsll.vv v12, v8, v12801; CHECK-NEXT: vsrl.vv v8, v8, v16802; CHECK-NEXT: vor.vv v8, v12, v8803; CHECK-NEXT: ret804;805; CHECK-ZVKB-LABEL: vrol_vv_v16i32:806; CHECK-ZVKB: # %bb.0:807; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma808; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12809; CHECK-ZVKB-NEXT: ret810 %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b)811 ret <16 x i32> %x812}813 814define <16 x i32> @vrol_vx_v16i32(<16 x i32> %a, i32 %b) {815; CHECK-LABEL: vrol_vx_v16i32:816; CHECK: # %bb.0:817; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma818; CHECK-NEXT: vmv.v.x v12, a0819; CHECK-NEXT: li a0, 31820; CHECK-NEXT: vand.vx v16, v12, a0821; CHECK-NEXT: vrsub.vi v12, v12, 0822; CHECK-NEXT: vsll.vv v16, v8, v16823; CHECK-NEXT: vand.vx v12, v12, a0824; CHECK-NEXT: vsrl.vv v8, v8, v12825; CHECK-NEXT: vor.vv v8, v16, v8826; CHECK-NEXT: ret827;828; CHECK-ZVKB-LABEL: vrol_vx_v16i32:829; CHECK-ZVKB: # %bb.0:830; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma831; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0832; CHECK-ZVKB-NEXT: ret833 %b.head = insertelement <16 x i32> poison, i32 %b, i32 0834 %b.splat = shufflevector <16 x i32> %b.head, <16 x i32> poison, <16 x i32> zeroinitializer835 %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b.splat)836 ret <16 x i32> %x837}838 839define <1 x i64> @vrol_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {840; CHECK-LABEL: vrol_vv_v1i64:841; CHECK: # %bb.0:842; CHECK-NEXT: li a0, 63843; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma844; CHECK-NEXT: vrsub.vi v10, v9, 0845; CHECK-NEXT: vand.vx v9, v9, a0846; CHECK-NEXT: vand.vx v10, v10, a0847; CHECK-NEXT: vsll.vv v9, v8, v9848; CHECK-NEXT: vsrl.vv v8, v8, v10849; CHECK-NEXT: vor.vv v8, v9, v8850; CHECK-NEXT: ret851;852; CHECK-ZVKB-LABEL: vrol_vv_v1i64:853; CHECK-ZVKB: # %bb.0:854; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma855; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9856; CHECK-ZVKB-NEXT: ret857 %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)858 ret <1 x i64> %x859}860 861define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) {862; CHECK-LABEL: vrol_vx_v1i64:863; CHECK: # %bb.0:864; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma865; CHECK-NEXT: vmv.s.x v9, a0866; CHECK-NEXT: li a0, 63867; CHECK-NEXT: vand.vx v10, v9, a0868; CHECK-NEXT: vrsub.vi v9, v9, 0869; CHECK-NEXT: vsll.vv v10, v8, v10870; CHECK-NEXT: vand.vx v9, v9, a0871; CHECK-NEXT: vsrl.vv v8, v8, v9872; CHECK-NEXT: vor.vv v8, v10, v8873; CHECK-NEXT: ret874;875; CHECK-ZVKB-LABEL: vrol_vx_v1i64:876; CHECK-ZVKB: # %bb.0:877; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma878; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0879; CHECK-ZVKB-NEXT: ret880 %b.head = insertelement <1 x i64> poison, i64 %b, i32 0881 %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer882 %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)883 ret <1 x i64> %x884}885 886define <2 x i64> @vrol_vv_v2i64(<2 x i64> %a, <2 x i64> %b) {887; CHECK-LABEL: vrol_vv_v2i64:888; CHECK: # %bb.0:889; CHECK-NEXT: li a0, 63890; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma891; CHECK-NEXT: vrsub.vi v10, v9, 0892; CHECK-NEXT: vand.vx v9, v9, a0893; CHECK-NEXT: vand.vx v10, v10, a0894; CHECK-NEXT: vsll.vv v9, v8, v9895; CHECK-NEXT: vsrl.vv v8, v8, v10896; CHECK-NEXT: vor.vv v8, v9, v8897; CHECK-NEXT: ret898;899; CHECK-ZVKB-LABEL: vrol_vv_v2i64:900; CHECK-ZVKB: # %bb.0:901; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma902; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9903; CHECK-ZVKB-NEXT: ret904 %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b)905 ret <2 x i64> %x906}907 908define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) {909; RV32-LABEL: vrol_vx_v2i64:910; RV32: # %bb.0:911; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma912; RV32-NEXT: vmv.v.x v9, a0913; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma914; RV32-NEXT: vmv.v.i v10, 0915; RV32-NEXT: vwsub.vx v11, v10, a0916; RV32-NEXT: li a0, 63917; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma918; RV32-NEXT: vand.vx v9, v9, a0919; RV32-NEXT: vand.vx v10, v11, a0920; RV32-NEXT: vsrl.vv v10, v8, v10921; RV32-NEXT: vsll.vv v8, v8, v9922; RV32-NEXT: vor.vv v8, v8, v10923; RV32-NEXT: ret924;925; RV64-LABEL: vrol_vx_v2i64:926; RV64: # %bb.0:927; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma928; RV64-NEXT: vmv.v.x v9, a0929; RV64-NEXT: li a0, 63930; RV64-NEXT: vand.vx v10, v9, a0931; RV64-NEXT: vrsub.vi v9, v9, 0932; RV64-NEXT: vsll.vv v10, v8, v10933; RV64-NEXT: vand.vx v9, v9, a0934; RV64-NEXT: vsrl.vv v8, v8, v9935; RV64-NEXT: vor.vv v8, v10, v8936; RV64-NEXT: ret937;938; CHECK-ZVKB-LABEL: vrol_vx_v2i64:939; CHECK-ZVKB: # %bb.0:940; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma941; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0942; CHECK-ZVKB-NEXT: ret943 %b.head = insertelement <2 x i64> poison, i64 %b, i32 0944 %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer945 %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)946 ret <2 x i64> %x947}948 949define <4 x i64> @vrol_vv_v4i64(<4 x i64> %a, <4 x i64> %b) {950; CHECK-LABEL: vrol_vv_v4i64:951; CHECK: # %bb.0:952; CHECK-NEXT: li a0, 63953; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma954; CHECK-NEXT: vrsub.vi v12, v10, 0955; CHECK-NEXT: vand.vx v10, v10, a0956; CHECK-NEXT: vand.vx v12, v12, a0957; CHECK-NEXT: vsll.vv v10, v8, v10958; CHECK-NEXT: vsrl.vv v8, v8, v12959; CHECK-NEXT: vor.vv v8, v10, v8960; CHECK-NEXT: ret961;962; CHECK-ZVKB-LABEL: vrol_vv_v4i64:963; CHECK-ZVKB: # %bb.0:964; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma965; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10966; CHECK-ZVKB-NEXT: ret967 %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b)968 ret <4 x i64> %x969}970 971define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) {972; RV32-LABEL: vrol_vx_v4i64:973; RV32: # %bb.0:974; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma975; RV32-NEXT: vmv.v.x v10, a0976; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma977; RV32-NEXT: vmv.v.i v14, 0978; RV32-NEXT: vwsub.vx v12, v14, a0979; RV32-NEXT: li a0, 63980; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma981; RV32-NEXT: vand.vx v10, v10, a0982; RV32-NEXT: vand.vx v12, v12, a0983; RV32-NEXT: vsrl.vv v12, v8, v12984; RV32-NEXT: vsll.vv v8, v8, v10985; RV32-NEXT: vor.vv v8, v8, v12986; RV32-NEXT: ret987;988; RV64-LABEL: vrol_vx_v4i64:989; RV64: # %bb.0:990; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma991; RV64-NEXT: vmv.v.x v10, a0992; RV64-NEXT: li a0, 63993; RV64-NEXT: vand.vx v12, v10, a0994; RV64-NEXT: vrsub.vi v10, v10, 0995; RV64-NEXT: vsll.vv v12, v8, v12996; RV64-NEXT: vand.vx v10, v10, a0997; RV64-NEXT: vsrl.vv v8, v8, v10998; RV64-NEXT: vor.vv v8, v12, v8999; RV64-NEXT: ret1000;1001; CHECK-ZVKB-LABEL: vrol_vx_v4i64:1002; CHECK-ZVKB: # %bb.0:1003; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma1004; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a01005; CHECK-ZVKB-NEXT: ret1006 %b.head = insertelement <4 x i64> poison, i64 %b, i32 01007 %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer1008 %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)1009 ret <4 x i64> %x1010}1011 1012define <8 x i64> @vrol_vv_v8i64(<8 x i64> %a, <8 x i64> %b) {1013; CHECK-LABEL: vrol_vv_v8i64:1014; CHECK: # %bb.0:1015; CHECK-NEXT: li a0, 631016; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma1017; CHECK-NEXT: vrsub.vi v16, v12, 01018; CHECK-NEXT: vand.vx v12, v12, a01019; CHECK-NEXT: vand.vx v16, v16, a01020; CHECK-NEXT: vsll.vv v12, v8, v121021; CHECK-NEXT: vsrl.vv v8, v8, v161022; CHECK-NEXT: vor.vv v8, v12, v81023; CHECK-NEXT: ret1024;1025; CHECK-ZVKB-LABEL: vrol_vv_v8i64:1026; CHECK-ZVKB: # %bb.0:1027; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma1028; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v121029; CHECK-ZVKB-NEXT: ret1030 %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b)1031 ret <8 x i64> %x1032}1033 1034define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {1035; RV32-LABEL: vrol_vx_v8i64:1036; RV32: # %bb.0:1037; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1038; RV32-NEXT: vmv.v.x v12, a01039; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1040; RV32-NEXT: vmv.v.i v20, 01041; RV32-NEXT: vwsub.vx v16, v20, a01042; RV32-NEXT: li a0, 631043; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma1044; RV32-NEXT: vand.vx v12, v12, a01045; RV32-NEXT: vand.vx v16, v16, a01046; RV32-NEXT: vsrl.vv v16, v8, v161047; RV32-NEXT: vsll.vv v8, v8, v121048; RV32-NEXT: vor.vv v8, v8, v161049; RV32-NEXT: ret1050;1051; RV64-LABEL: vrol_vx_v8i64:1052; RV64: # %bb.0:1053; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1054; RV64-NEXT: vmv.v.x v12, a01055; RV64-NEXT: li a0, 631056; RV64-NEXT: vand.vx v16, v12, a01057; RV64-NEXT: vrsub.vi v12, v12, 01058; RV64-NEXT: vsll.vv v16, v8, v161059; RV64-NEXT: vand.vx v12, v12, a01060; RV64-NEXT: vsrl.vv v8, v8, v121061; RV64-NEXT: vor.vv v8, v16, v81062; RV64-NEXT: ret1063;1064; CHECK-ZVKB-LABEL: vrol_vx_v8i64:1065; CHECK-ZVKB: # %bb.0:1066; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma1067; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a01068; CHECK-ZVKB-NEXT: ret1069 %b.head = insertelement <8 x i64> poison, i64 %b, i32 01070 %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer1071 %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)1072 ret <8 x i64> %x1073}1074