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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB6 7define <1 x i8> @vror_vv_v1i8(<1 x i8> %a, <1 x i8> %b) {8; CHECK-LABEL: vror_vv_v1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma11; CHECK-NEXT: vand.vi v10, v9, 712; CHECK-NEXT: vrsub.vi v9, v9, 013; CHECK-NEXT: vsrl.vv v10, v8, v1014; CHECK-NEXT: vand.vi v9, v9, 715; CHECK-NEXT: vsll.vv v8, v8, v916; CHECK-NEXT: vor.vv v8, v10, v817; CHECK-NEXT: ret18;19; CHECK-ZVKB-LABEL: vror_vv_v1i8:20; CHECK-ZVKB: # %bb.0:21; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma22; CHECK-ZVKB-NEXT: vror.vv v8, v8, v923; CHECK-ZVKB-NEXT: ret24 %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b)25 ret <1 x i8> %x26}27 28define <1 x i8> @vror_vx_v1i8(<1 x i8> %a, i8 %b) {29; CHECK-LABEL: vror_vx_v1i8:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma32; CHECK-NEXT: vmv.s.x v9, a033; CHECK-NEXT: vand.vi v10, v9, 734; CHECK-NEXT: vrsub.vi v9, v9, 035; CHECK-NEXT: vsrl.vv v10, v8, v1036; CHECK-NEXT: vand.vi v9, v9, 737; CHECK-NEXT: vsll.vv v8, v8, v938; CHECK-NEXT: vor.vv v8, v10, v839; CHECK-NEXT: ret40;41; CHECK-ZVKB-LABEL: vror_vx_v1i8:42; CHECK-ZVKB: # %bb.0:43; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma44; CHECK-ZVKB-NEXT: vror.vx v8, v8, a045; CHECK-ZVKB-NEXT: ret46 %b.head = insertelement <1 x i8> poison, i8 %b, i32 047 %b.splat = shufflevector <1 x i8> %b.head, <1 x i8> poison, <1 x i32> zeroinitializer48 %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b.splat)49 ret <1 x i8> %x50}51 52define <1 x i8> @vror_vi_v1i8(<1 x i8> %a) {53; CHECK-LABEL: vror_vi_v1i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma56; CHECK-NEXT: vsll.vi v9, v8, 757; CHECK-NEXT: vsrl.vi v8, v8, 158; CHECK-NEXT: vor.vv v8, v8, v959; CHECK-NEXT: ret60;61; CHECK-ZVKB-LABEL: vror_vi_v1i8:62; CHECK-ZVKB: # %bb.0:63; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma64; CHECK-ZVKB-NEXT: vror.vi v8, v8, 165; CHECK-ZVKB-NEXT: ret66 %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> splat (i8 1))67 ret <1 x i8> %x68}69 70define <1 x i8> @vror_vi_rotl_v1i8(<1 x i8> %a) {71; CHECK-LABEL: vror_vi_rotl_v1i8:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma74; CHECK-NEXT: vsrl.vi v9, v8, 775; CHECK-NEXT: vadd.vv v8, v8, v876; CHECK-NEXT: vor.vv v8, v8, v977; CHECK-NEXT: ret78;79; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i8:80; CHECK-ZVKB: # %bb.0:81; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma82; CHECK-ZVKB-NEXT: vror.vi v8, v8, 783; CHECK-ZVKB-NEXT: ret84 %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> splat (i8 1))85 ret <1 x i8> %x86}87 88define <2 x i8> @vror_vv_v2i8(<2 x i8> %a, <2 x i8> %b) {89; CHECK-LABEL: vror_vv_v2i8:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma92; CHECK-NEXT: vand.vi v10, v9, 793; CHECK-NEXT: vrsub.vi v9, v9, 094; CHECK-NEXT: vsrl.vv v10, v8, v1095; CHECK-NEXT: vand.vi v9, v9, 796; CHECK-NEXT: vsll.vv v8, v8, v997; CHECK-NEXT: vor.vv v8, v10, v898; CHECK-NEXT: ret99;100; CHECK-ZVKB-LABEL: vror_vv_v2i8:101; CHECK-ZVKB: # %bb.0:102; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma103; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9104; CHECK-ZVKB-NEXT: ret105 %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b)106 ret <2 x i8> %x107}108 109define <2 x i8> @vror_vx_v2i8(<2 x i8> %a, i8 %b) {110; CHECK-LABEL: vror_vx_v2i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma113; CHECK-NEXT: vmv.v.x v9, a0114; CHECK-NEXT: vand.vi v10, v9, 7115; CHECK-NEXT: vrsub.vi v9, v9, 0116; CHECK-NEXT: vsrl.vv v10, v8, v10117; CHECK-NEXT: vand.vi v9, v9, 7118; CHECK-NEXT: vsll.vv v8, v8, v9119; CHECK-NEXT: vor.vv v8, v10, v8120; CHECK-NEXT: ret121;122; CHECK-ZVKB-LABEL: vror_vx_v2i8:123; CHECK-ZVKB: # %bb.0:124; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma125; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0126; CHECK-ZVKB-NEXT: ret127 %b.head = insertelement <2 x i8> poison, i8 %b, i32 0128 %b.splat = shufflevector <2 x i8> %b.head, <2 x i8> poison, <2 x i32> zeroinitializer129 %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b.splat)130 ret <2 x i8> %x131}132 133define <2 x i8> @vror_vi_v2i8(<2 x i8> %a) {134; CHECK-LABEL: vror_vi_v2i8:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma137; CHECK-NEXT: vsll.vi v9, v8, 7138; CHECK-NEXT: vsrl.vi v8, v8, 1139; CHECK-NEXT: vor.vv v8, v8, v9140; CHECK-NEXT: ret141;142; CHECK-ZVKB-LABEL: vror_vi_v2i8:143; CHECK-ZVKB: # %bb.0:144; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma145; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1146; CHECK-ZVKB-NEXT: ret147 %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> splat (i8 1))148 ret <2 x i8> %x149}150 151define <2 x i8> @vror_vi_rotl_v2i8(<2 x i8> %a) {152; CHECK-LABEL: vror_vi_rotl_v2i8:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma155; CHECK-NEXT: vsrl.vi v9, v8, 7156; CHECK-NEXT: vadd.vv v8, v8, v8157; CHECK-NEXT: vor.vv v8, v8, v9158; CHECK-NEXT: ret159;160; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i8:161; CHECK-ZVKB: # %bb.0:162; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma163; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7164; CHECK-ZVKB-NEXT: ret165 %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> splat (i8 1))166 ret <2 x i8> %x167}168 169define <4 x i8> @vror_vv_v4i8(<4 x i8> %a, <4 x i8> %b) {170; CHECK-LABEL: vror_vv_v4i8:171; CHECK: # %bb.0:172; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma173; CHECK-NEXT: vand.vi v10, v9, 7174; CHECK-NEXT: vrsub.vi v9, v9, 0175; CHECK-NEXT: vsrl.vv v10, v8, v10176; CHECK-NEXT: vand.vi v9, v9, 7177; CHECK-NEXT: vsll.vv v8, v8, v9178; CHECK-NEXT: vor.vv v8, v10, v8179; CHECK-NEXT: ret180;181; CHECK-ZVKB-LABEL: vror_vv_v4i8:182; CHECK-ZVKB: # %bb.0:183; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma184; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9185; CHECK-ZVKB-NEXT: ret186 %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b)187 ret <4 x i8> %x188}189 190define <4 x i8> @vror_vx_v4i8(<4 x i8> %a, i8 %b) {191; CHECK-LABEL: vror_vx_v4i8:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma194; CHECK-NEXT: vmv.v.x v9, a0195; CHECK-NEXT: vand.vi v10, v9, 7196; CHECK-NEXT: vrsub.vi v9, v9, 0197; CHECK-NEXT: vsrl.vv v10, v8, v10198; CHECK-NEXT: vand.vi v9, v9, 7199; CHECK-NEXT: vsll.vv v8, v8, v9200; CHECK-NEXT: vor.vv v8, v10, v8201; CHECK-NEXT: ret202;203; CHECK-ZVKB-LABEL: vror_vx_v4i8:204; CHECK-ZVKB: # %bb.0:205; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma206; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0207; CHECK-ZVKB-NEXT: ret208 %b.head = insertelement <4 x i8> poison, i8 %b, i32 0209 %b.splat = shufflevector <4 x i8> %b.head, <4 x i8> poison, <4 x i32> zeroinitializer210 %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b.splat)211 ret <4 x i8> %x212}213 214define <4 x i8> @vror_vi_v4i8(<4 x i8> %a) {215; CHECK-LABEL: vror_vi_v4i8:216; CHECK: # %bb.0:217; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma218; CHECK-NEXT: vsll.vi v9, v8, 7219; CHECK-NEXT: vsrl.vi v8, v8, 1220; CHECK-NEXT: vor.vv v8, v8, v9221; CHECK-NEXT: ret222;223; CHECK-ZVKB-LABEL: vror_vi_v4i8:224; CHECK-ZVKB: # %bb.0:225; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma226; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1227; CHECK-ZVKB-NEXT: ret228 %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> splat (i8 1))229 ret <4 x i8> %x230}231 232define <4 x i8> @vror_vi_rotl_v4i8(<4 x i8> %a) {233; CHECK-LABEL: vror_vi_rotl_v4i8:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma236; CHECK-NEXT: vsrl.vi v9, v8, 7237; CHECK-NEXT: vadd.vv v8, v8, v8238; CHECK-NEXT: vor.vv v8, v8, v9239; CHECK-NEXT: ret240;241; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i8:242; CHECK-ZVKB: # %bb.0:243; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma244; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7245; CHECK-ZVKB-NEXT: ret246 %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> splat (i8 1))247 ret <4 x i8> %x248}249 250define <8 x i8> @vror_vv_v8i8(<8 x i8> %a, <8 x i8> %b) {251; CHECK-LABEL: vror_vv_v8i8:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma254; CHECK-NEXT: vand.vi v10, v9, 7255; CHECK-NEXT: vrsub.vi v9, v9, 0256; CHECK-NEXT: vsrl.vv v10, v8, v10257; CHECK-NEXT: vand.vi v9, v9, 7258; CHECK-NEXT: vsll.vv v8, v8, v9259; CHECK-NEXT: vor.vv v8, v10, v8260; CHECK-NEXT: ret261;262; CHECK-ZVKB-LABEL: vror_vv_v8i8:263; CHECK-ZVKB: # %bb.0:264; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma265; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9266; CHECK-ZVKB-NEXT: ret267 %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b)268 ret <8 x i8> %x269}270 271define <8 x i8> @vror_vx_v8i8(<8 x i8> %a, i8 %b) {272; CHECK-LABEL: vror_vx_v8i8:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma275; CHECK-NEXT: vmv.v.x v9, a0276; CHECK-NEXT: vand.vi v10, v9, 7277; CHECK-NEXT: vrsub.vi v9, v9, 0278; CHECK-NEXT: vsrl.vv v10, v8, v10279; CHECK-NEXT: vand.vi v9, v9, 7280; CHECK-NEXT: vsll.vv v8, v8, v9281; CHECK-NEXT: vor.vv v8, v10, v8282; CHECK-NEXT: ret283;284; CHECK-ZVKB-LABEL: vror_vx_v8i8:285; CHECK-ZVKB: # %bb.0:286; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma287; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0288; CHECK-ZVKB-NEXT: ret289 %b.head = insertelement <8 x i8> poison, i8 %b, i32 0290 %b.splat = shufflevector <8 x i8> %b.head, <8 x i8> poison, <8 x i32> zeroinitializer291 %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b.splat)292 ret <8 x i8> %x293}294 295define <8 x i8> @vror_vi_v8i8(<8 x i8> %a) {296; CHECK-LABEL: vror_vi_v8i8:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma299; CHECK-NEXT: vsll.vi v9, v8, 7300; CHECK-NEXT: vsrl.vi v8, v8, 1301; CHECK-NEXT: vor.vv v8, v8, v9302; CHECK-NEXT: ret303;304; CHECK-ZVKB-LABEL: vror_vi_v8i8:305; CHECK-ZVKB: # %bb.0:306; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma307; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1308; CHECK-ZVKB-NEXT: ret309 %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> splat (i8 1))310 ret <8 x i8> %x311}312 313define <8 x i8> @vror_vi_rotl_v8i8(<8 x i8> %a) {314; CHECK-LABEL: vror_vi_rotl_v8i8:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma317; CHECK-NEXT: vsrl.vi v9, v8, 7318; CHECK-NEXT: vadd.vv v8, v8, v8319; CHECK-NEXT: vor.vv v8, v8, v9320; CHECK-NEXT: ret321;322; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i8:323; CHECK-ZVKB: # %bb.0:324; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma325; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7326; CHECK-ZVKB-NEXT: ret327 %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> splat (i8 1))328 ret <8 x i8> %x329}330 331define <16 x i8> @vror_vv_v16i8(<16 x i8> %a, <16 x i8> %b) {332; CHECK-LABEL: vror_vv_v16i8:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma335; CHECK-NEXT: vand.vi v10, v9, 7336; CHECK-NEXT: vrsub.vi v9, v9, 0337; CHECK-NEXT: vsrl.vv v10, v8, v10338; CHECK-NEXT: vand.vi v9, v9, 7339; CHECK-NEXT: vsll.vv v8, v8, v9340; CHECK-NEXT: vor.vv v8, v10, v8341; CHECK-NEXT: ret342;343; CHECK-ZVKB-LABEL: vror_vv_v16i8:344; CHECK-ZVKB: # %bb.0:345; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma346; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9347; CHECK-ZVKB-NEXT: ret348 %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b)349 ret <16 x i8> %x350}351 352define <16 x i8> @vror_vx_v16i8(<16 x i8> %a, i8 %b) {353; CHECK-LABEL: vror_vx_v16i8:354; CHECK: # %bb.0:355; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma356; CHECK-NEXT: vmv.v.x v9, a0357; CHECK-NEXT: vand.vi v10, v9, 7358; CHECK-NEXT: vrsub.vi v9, v9, 0359; CHECK-NEXT: vsrl.vv v10, v8, v10360; CHECK-NEXT: vand.vi v9, v9, 7361; CHECK-NEXT: vsll.vv v8, v8, v9362; CHECK-NEXT: vor.vv v8, v10, v8363; CHECK-NEXT: ret364;365; CHECK-ZVKB-LABEL: vror_vx_v16i8:366; CHECK-ZVKB: # %bb.0:367; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma368; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0369; CHECK-ZVKB-NEXT: ret370 %b.head = insertelement <16 x i8> poison, i8 %b, i32 0371 %b.splat = shufflevector <16 x i8> %b.head, <16 x i8> poison, <16 x i32> zeroinitializer372 %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b.splat)373 ret <16 x i8> %x374}375 376define <16 x i8> @vror_vi_v16i8(<16 x i8> %a) {377; CHECK-LABEL: vror_vi_v16i8:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma380; CHECK-NEXT: vsll.vi v9, v8, 7381; CHECK-NEXT: vsrl.vi v8, v8, 1382; CHECK-NEXT: vor.vv v8, v8, v9383; CHECK-NEXT: ret384;385; CHECK-ZVKB-LABEL: vror_vi_v16i8:386; CHECK-ZVKB: # %bb.0:387; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma388; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1389; CHECK-ZVKB-NEXT: ret390 %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 1))391 ret <16 x i8> %x392}393 394define <16 x i8> @vror_vi_rotl_v16i8(<16 x i8> %a) {395; CHECK-LABEL: vror_vi_rotl_v16i8:396; CHECK: # %bb.0:397; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma398; CHECK-NEXT: vsrl.vi v9, v8, 7399; CHECK-NEXT: vadd.vv v8, v8, v8400; CHECK-NEXT: vor.vv v8, v8, v9401; CHECK-NEXT: ret402;403; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i8:404; CHECK-ZVKB: # %bb.0:405; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma406; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7407; CHECK-ZVKB-NEXT: ret408 %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 1))409 ret <16 x i8> %x410}411 412define <32 x i8> @vror_vv_v32i8(<32 x i8> %a, <32 x i8> %b) {413; CHECK-LABEL: vror_vv_v32i8:414; CHECK: # %bb.0:415; CHECK-NEXT: li a0, 32416; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma417; CHECK-NEXT: vand.vi v12, v10, 7418; CHECK-NEXT: vrsub.vi v10, v10, 0419; CHECK-NEXT: vsrl.vv v12, v8, v12420; CHECK-NEXT: vand.vi v10, v10, 7421; CHECK-NEXT: vsll.vv v8, v8, v10422; CHECK-NEXT: vor.vv v8, v12, v8423; CHECK-NEXT: ret424;425; CHECK-ZVKB-LABEL: vror_vv_v32i8:426; CHECK-ZVKB: # %bb.0:427; CHECK-ZVKB-NEXT: li a0, 32428; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma429; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10430; CHECK-ZVKB-NEXT: ret431 %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b)432 ret <32 x i8> %x433}434 435define <32 x i8> @vror_vx_v32i8(<32 x i8> %a, i8 %b) {436; CHECK-LABEL: vror_vx_v32i8:437; CHECK: # %bb.0:438; CHECK-NEXT: li a1, 32439; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma440; CHECK-NEXT: vmv.v.x v10, a0441; CHECK-NEXT: vand.vi v12, v10, 7442; CHECK-NEXT: vrsub.vi v10, v10, 0443; CHECK-NEXT: vsrl.vv v12, v8, v12444; CHECK-NEXT: vand.vi v10, v10, 7445; CHECK-NEXT: vsll.vv v8, v8, v10446; CHECK-NEXT: vor.vv v8, v12, v8447; CHECK-NEXT: ret448;449; CHECK-ZVKB-LABEL: vror_vx_v32i8:450; CHECK-ZVKB: # %bb.0:451; CHECK-ZVKB-NEXT: li a1, 32452; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m2, ta, ma453; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0454; CHECK-ZVKB-NEXT: ret455 %b.head = insertelement <32 x i8> poison, i8 %b, i32 0456 %b.splat = shufflevector <32 x i8> %b.head, <32 x i8> poison, <32 x i32> zeroinitializer457 %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b.splat)458 ret <32 x i8> %x459}460 461define <32 x i8> @vror_vi_v32i8(<32 x i8> %a) {462; CHECK-LABEL: vror_vi_v32i8:463; CHECK: # %bb.0:464; CHECK-NEXT: li a0, 32465; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma466; CHECK-NEXT: vsll.vi v10, v8, 7467; CHECK-NEXT: vsrl.vi v8, v8, 1468; CHECK-NEXT: vor.vv v8, v8, v10469; CHECK-NEXT: ret470;471; CHECK-ZVKB-LABEL: vror_vi_v32i8:472; CHECK-ZVKB: # %bb.0:473; CHECK-ZVKB-NEXT: li a0, 32474; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma475; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1476; CHECK-ZVKB-NEXT: ret477 %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> splat (i8 1))478 ret <32 x i8> %x479}480 481define <32 x i8> @vror_vi_rotl_v32i8(<32 x i8> %a) {482; CHECK-LABEL: vror_vi_rotl_v32i8:483; CHECK: # %bb.0:484; CHECK-NEXT: li a0, 32485; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma486; CHECK-NEXT: vsrl.vi v10, v8, 7487; CHECK-NEXT: vadd.vv v8, v8, v8488; CHECK-NEXT: vor.vv v8, v8, v10489; CHECK-NEXT: ret490;491; CHECK-ZVKB-LABEL: vror_vi_rotl_v32i8:492; CHECK-ZVKB: # %bb.0:493; CHECK-ZVKB-NEXT: li a0, 32494; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma495; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7496; CHECK-ZVKB-NEXT: ret497 %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> splat (i8 1))498 ret <32 x i8> %x499}500 501define <64 x i8> @vror_vv_v64i8(<64 x i8> %a, <64 x i8> %b) {502; CHECK-LABEL: vror_vv_v64i8:503; CHECK: # %bb.0:504; CHECK-NEXT: li a0, 64505; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma506; CHECK-NEXT: vand.vi v16, v12, 7507; CHECK-NEXT: vrsub.vi v12, v12, 0508; CHECK-NEXT: vsrl.vv v16, v8, v16509; CHECK-NEXT: vand.vi v12, v12, 7510; CHECK-NEXT: vsll.vv v8, v8, v12511; CHECK-NEXT: vor.vv v8, v16, v8512; CHECK-NEXT: ret513;514; CHECK-ZVKB-LABEL: vror_vv_v64i8:515; CHECK-ZVKB: # %bb.0:516; CHECK-ZVKB-NEXT: li a0, 64517; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma518; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12519; CHECK-ZVKB-NEXT: ret520 %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b)521 ret <64 x i8> %x522}523 524define <64 x i8> @vror_vx_v64i8(<64 x i8> %a, i8 %b) {525; CHECK-LABEL: vror_vx_v64i8:526; CHECK: # %bb.0:527; CHECK-NEXT: li a1, 64528; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma529; CHECK-NEXT: vmv.v.x v12, a0530; CHECK-NEXT: vand.vi v16, v12, 7531; CHECK-NEXT: vrsub.vi v12, v12, 0532; CHECK-NEXT: vsrl.vv v16, v8, v16533; CHECK-NEXT: vand.vi v12, v12, 7534; CHECK-NEXT: vsll.vv v8, v8, v12535; CHECK-NEXT: vor.vv v8, v16, v8536; CHECK-NEXT: ret537;538; CHECK-ZVKB-LABEL: vror_vx_v64i8:539; CHECK-ZVKB: # %bb.0:540; CHECK-ZVKB-NEXT: li a1, 64541; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m4, ta, ma542; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0543; CHECK-ZVKB-NEXT: ret544 %b.head = insertelement <64 x i8> poison, i8 %b, i32 0545 %b.splat = shufflevector <64 x i8> %b.head, <64 x i8> poison, <64 x i32> zeroinitializer546 %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b.splat)547 ret <64 x i8> %x548}549 550define <64 x i8> @vror_vi_v64i8(<64 x i8> %a) {551; CHECK-LABEL: vror_vi_v64i8:552; CHECK: # %bb.0:553; CHECK-NEXT: li a0, 64554; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma555; CHECK-NEXT: vsll.vi v12, v8, 7556; CHECK-NEXT: vsrl.vi v8, v8, 1557; CHECK-NEXT: vor.vv v8, v8, v12558; CHECK-NEXT: ret559;560; CHECK-ZVKB-LABEL: vror_vi_v64i8:561; CHECK-ZVKB: # %bb.0:562; CHECK-ZVKB-NEXT: li a0, 64563; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma564; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1565; CHECK-ZVKB-NEXT: ret566 %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> splat (i8 1))567 ret <64 x i8> %x568}569 570define <64 x i8> @vror_vi_rotl_v64i8(<64 x i8> %a) {571; CHECK-LABEL: vror_vi_rotl_v64i8:572; CHECK: # %bb.0:573; CHECK-NEXT: li a0, 64574; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma575; CHECK-NEXT: vsrl.vi v12, v8, 7576; CHECK-NEXT: vadd.vv v8, v8, v8577; CHECK-NEXT: vor.vv v8, v8, v12578; CHECK-NEXT: ret579;580; CHECK-ZVKB-LABEL: vror_vi_rotl_v64i8:581; CHECK-ZVKB: # %bb.0:582; CHECK-ZVKB-NEXT: li a0, 64583; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma584; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7585; CHECK-ZVKB-NEXT: ret586 %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> splat (i8 1))587 ret <64 x i8> %x588}589 590define <1 x i16> @vror_vv_v1i16(<1 x i16> %a, <1 x i16> %b) {591; CHECK-LABEL: vror_vv_v1i16:592; CHECK: # %bb.0:593; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma594; CHECK-NEXT: vand.vi v10, v9, 15595; CHECK-NEXT: vrsub.vi v9, v9, 0596; CHECK-NEXT: vsrl.vv v10, v8, v10597; CHECK-NEXT: vand.vi v9, v9, 15598; CHECK-NEXT: vsll.vv v8, v8, v9599; CHECK-NEXT: vor.vv v8, v10, v8600; CHECK-NEXT: ret601;602; CHECK-ZVKB-LABEL: vror_vv_v1i16:603; CHECK-ZVKB: # %bb.0:604; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma605; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9606; CHECK-ZVKB-NEXT: ret607 %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b)608 ret <1 x i16> %x609}610 611define <1 x i16> @vror_vx_v1i16(<1 x i16> %a, i16 %b) {612; CHECK-LABEL: vror_vx_v1i16:613; CHECK: # %bb.0:614; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma615; CHECK-NEXT: vmv.s.x v9, a0616; CHECK-NEXT: vand.vi v10, v9, 15617; CHECK-NEXT: vrsub.vi v9, v9, 0618; CHECK-NEXT: vsrl.vv v10, v8, v10619; CHECK-NEXT: vand.vi v9, v9, 15620; CHECK-NEXT: vsll.vv v8, v8, v9621; CHECK-NEXT: vor.vv v8, v10, v8622; CHECK-NEXT: ret623;624; CHECK-ZVKB-LABEL: vror_vx_v1i16:625; CHECK-ZVKB: # %bb.0:626; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma627; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0628; CHECK-ZVKB-NEXT: ret629 %b.head = insertelement <1 x i16> poison, i16 %b, i32 0630 %b.splat = shufflevector <1 x i16> %b.head, <1 x i16> poison, <1 x i32> zeroinitializer631 %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b.splat)632 ret <1 x i16> %x633}634 635define <1 x i16> @vror_vi_v1i16(<1 x i16> %a) {636; CHECK-LABEL: vror_vi_v1i16:637; CHECK: # %bb.0:638; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma639; CHECK-NEXT: vsll.vi v9, v8, 15640; CHECK-NEXT: vsrl.vi v8, v8, 1641; CHECK-NEXT: vor.vv v8, v8, v9642; CHECK-NEXT: ret643;644; CHECK-ZVKB-LABEL: vror_vi_v1i16:645; CHECK-ZVKB: # %bb.0:646; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma647; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1648; CHECK-ZVKB-NEXT: ret649 %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> splat (i16 1))650 ret <1 x i16> %x651}652 653define <1 x i16> @vror_vi_rotl_v1i16(<1 x i16> %a) {654; CHECK-LABEL: vror_vi_rotl_v1i16:655; CHECK: # %bb.0:656; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma657; CHECK-NEXT: vsrl.vi v9, v8, 15658; CHECK-NEXT: vadd.vv v8, v8, v8659; CHECK-NEXT: vor.vv v8, v8, v9660; CHECK-NEXT: ret661;662; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i16:663; CHECK-ZVKB: # %bb.0:664; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma665; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15666; CHECK-ZVKB-NEXT: ret667 %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> splat (i16 1))668 ret <1 x i16> %x669}670 671define <2 x i16> @vror_vv_v2i16(<2 x i16> %a, <2 x i16> %b) {672; CHECK-LABEL: vror_vv_v2i16:673; CHECK: # %bb.0:674; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma675; CHECK-NEXT: vand.vi v10, v9, 15676; CHECK-NEXT: vrsub.vi v9, v9, 0677; CHECK-NEXT: vsrl.vv v10, v8, v10678; CHECK-NEXT: vand.vi v9, v9, 15679; CHECK-NEXT: vsll.vv v8, v8, v9680; CHECK-NEXT: vor.vv v8, v10, v8681; CHECK-NEXT: ret682;683; CHECK-ZVKB-LABEL: vror_vv_v2i16:684; CHECK-ZVKB: # %bb.0:685; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma686; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9687; CHECK-ZVKB-NEXT: ret688 %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b)689 ret <2 x i16> %x690}691 692define <2 x i16> @vror_vx_v2i16(<2 x i16> %a, i16 %b) {693; CHECK-LABEL: vror_vx_v2i16:694; CHECK: # %bb.0:695; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma696; CHECK-NEXT: vmv.v.x v9, a0697; CHECK-NEXT: vand.vi v10, v9, 15698; CHECK-NEXT: vrsub.vi v9, v9, 0699; CHECK-NEXT: vsrl.vv v10, v8, v10700; CHECK-NEXT: vand.vi v9, v9, 15701; CHECK-NEXT: vsll.vv v8, v8, v9702; CHECK-NEXT: vor.vv v8, v10, v8703; CHECK-NEXT: ret704;705; CHECK-ZVKB-LABEL: vror_vx_v2i16:706; CHECK-ZVKB: # %bb.0:707; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma708; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0709; CHECK-ZVKB-NEXT: ret710 %b.head = insertelement <2 x i16> poison, i16 %b, i32 0711 %b.splat = shufflevector <2 x i16> %b.head, <2 x i16> poison, <2 x i32> zeroinitializer712 %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b.splat)713 ret <2 x i16> %x714}715 716define <2 x i16> @vror_vi_v2i16(<2 x i16> %a) {717; CHECK-LABEL: vror_vi_v2i16:718; CHECK: # %bb.0:719; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma720; CHECK-NEXT: vsll.vi v9, v8, 15721; CHECK-NEXT: vsrl.vi v8, v8, 1722; CHECK-NEXT: vor.vv v8, v8, v9723; CHECK-NEXT: ret724;725; CHECK-ZVKB-LABEL: vror_vi_v2i16:726; CHECK-ZVKB: # %bb.0:727; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma728; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1729; CHECK-ZVKB-NEXT: ret730 %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> splat (i16 1))731 ret <2 x i16> %x732}733 734define <2 x i16> @vror_vi_rotl_v2i16(<2 x i16> %a) {735; CHECK-LABEL: vror_vi_rotl_v2i16:736; CHECK: # %bb.0:737; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma738; CHECK-NEXT: vsrl.vi v9, v8, 15739; CHECK-NEXT: vadd.vv v8, v8, v8740; CHECK-NEXT: vor.vv v8, v8, v9741; CHECK-NEXT: ret742;743; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i16:744; CHECK-ZVKB: # %bb.0:745; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma746; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15747; CHECK-ZVKB-NEXT: ret748 %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> splat (i16 1))749 ret <2 x i16> %x750}751 752define <4 x i16> @vror_vv_v4i16(<4 x i16> %a, <4 x i16> %b) {753; CHECK-LABEL: vror_vv_v4i16:754; CHECK: # %bb.0:755; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma756; CHECK-NEXT: vand.vi v10, v9, 15757; CHECK-NEXT: vrsub.vi v9, v9, 0758; CHECK-NEXT: vsrl.vv v10, v8, v10759; CHECK-NEXT: vand.vi v9, v9, 15760; CHECK-NEXT: vsll.vv v8, v8, v9761; CHECK-NEXT: vor.vv v8, v10, v8762; CHECK-NEXT: ret763;764; CHECK-ZVKB-LABEL: vror_vv_v4i16:765; CHECK-ZVKB: # %bb.0:766; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma767; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9768; CHECK-ZVKB-NEXT: ret769 %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b)770 ret <4 x i16> %x771}772 773define <4 x i16> @vror_vx_v4i16(<4 x i16> %a, i16 %b) {774; CHECK-LABEL: vror_vx_v4i16:775; CHECK: # %bb.0:776; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma777; CHECK-NEXT: vmv.v.x v9, a0778; CHECK-NEXT: vand.vi v10, v9, 15779; CHECK-NEXT: vrsub.vi v9, v9, 0780; CHECK-NEXT: vsrl.vv v10, v8, v10781; CHECK-NEXT: vand.vi v9, v9, 15782; CHECK-NEXT: vsll.vv v8, v8, v9783; CHECK-NEXT: vor.vv v8, v10, v8784; CHECK-NEXT: ret785;786; CHECK-ZVKB-LABEL: vror_vx_v4i16:787; CHECK-ZVKB: # %bb.0:788; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma789; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0790; CHECK-ZVKB-NEXT: ret791 %b.head = insertelement <4 x i16> poison, i16 %b, i32 0792 %b.splat = shufflevector <4 x i16> %b.head, <4 x i16> poison, <4 x i32> zeroinitializer793 %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b.splat)794 ret <4 x i16> %x795}796 797define <4 x i16> @vror_vi_v4i16(<4 x i16> %a) {798; CHECK-LABEL: vror_vi_v4i16:799; CHECK: # %bb.0:800; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma801; CHECK-NEXT: vsll.vi v9, v8, 15802; CHECK-NEXT: vsrl.vi v8, v8, 1803; CHECK-NEXT: vor.vv v8, v8, v9804; CHECK-NEXT: ret805;806; CHECK-ZVKB-LABEL: vror_vi_v4i16:807; CHECK-ZVKB: # %bb.0:808; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma809; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1810; CHECK-ZVKB-NEXT: ret811 %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> splat (i16 1))812 ret <4 x i16> %x813}814 815define <4 x i16> @vror_vi_rotl_v4i16(<4 x i16> %a) {816; CHECK-LABEL: vror_vi_rotl_v4i16:817; CHECK: # %bb.0:818; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma819; CHECK-NEXT: vsrl.vi v9, v8, 15820; CHECK-NEXT: vadd.vv v8, v8, v8821; CHECK-NEXT: vor.vv v8, v8, v9822; CHECK-NEXT: ret823;824; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i16:825; CHECK-ZVKB: # %bb.0:826; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma827; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15828; CHECK-ZVKB-NEXT: ret829 %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> splat (i16 1))830 ret <4 x i16> %x831}832 833define <8 x i16> @vror_vv_v8i16(<8 x i16> %a, <8 x i16> %b) {834; CHECK-LABEL: vror_vv_v8i16:835; CHECK: # %bb.0:836; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma837; CHECK-NEXT: vand.vi v10, v9, 15838; CHECK-NEXT: vrsub.vi v9, v9, 0839; CHECK-NEXT: vsrl.vv v10, v8, v10840; CHECK-NEXT: vand.vi v9, v9, 15841; CHECK-NEXT: vsll.vv v8, v8, v9842; CHECK-NEXT: vor.vv v8, v10, v8843; CHECK-NEXT: ret844;845; CHECK-ZVKB-LABEL: vror_vv_v8i16:846; CHECK-ZVKB: # %bb.0:847; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma848; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9849; CHECK-ZVKB-NEXT: ret850 %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b)851 ret <8 x i16> %x852}853 854define <8 x i16> @vror_vx_v8i16(<8 x i16> %a, i16 %b) {855; CHECK-LABEL: vror_vx_v8i16:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma858; CHECK-NEXT: vmv.v.x v9, a0859; CHECK-NEXT: vand.vi v10, v9, 15860; CHECK-NEXT: vrsub.vi v9, v9, 0861; CHECK-NEXT: vsrl.vv v10, v8, v10862; CHECK-NEXT: vand.vi v9, v9, 15863; CHECK-NEXT: vsll.vv v8, v8, v9864; CHECK-NEXT: vor.vv v8, v10, v8865; CHECK-NEXT: ret866;867; CHECK-ZVKB-LABEL: vror_vx_v8i16:868; CHECK-ZVKB: # %bb.0:869; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma870; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0871; CHECK-ZVKB-NEXT: ret872 %b.head = insertelement <8 x i16> poison, i16 %b, i32 0873 %b.splat = shufflevector <8 x i16> %b.head, <8 x i16> poison, <8 x i32> zeroinitializer874 %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b.splat)875 ret <8 x i16> %x876}877 878define <8 x i16> @vror_vi_v8i16(<8 x i16> %a) {879; CHECK-LABEL: vror_vi_v8i16:880; CHECK: # %bb.0:881; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma882; CHECK-NEXT: vsll.vi v9, v8, 15883; CHECK-NEXT: vsrl.vi v8, v8, 1884; CHECK-NEXT: vor.vv v8, v8, v9885; CHECK-NEXT: ret886;887; CHECK-ZVKB-LABEL: vror_vi_v8i16:888; CHECK-ZVKB: # %bb.0:889; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma890; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1891; CHECK-ZVKB-NEXT: ret892 %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 1))893 ret <8 x i16> %x894}895 896define <8 x i16> @vror_vi_rotl_v8i16(<8 x i16> %a) {897; CHECK-LABEL: vror_vi_rotl_v8i16:898; CHECK: # %bb.0:899; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma900; CHECK-NEXT: vsrl.vi v9, v8, 15901; CHECK-NEXT: vadd.vv v8, v8, v8902; CHECK-NEXT: vor.vv v8, v8, v9903; CHECK-NEXT: ret904;905; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i16:906; CHECK-ZVKB: # %bb.0:907; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma908; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15909; CHECK-ZVKB-NEXT: ret910 %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 1))911 ret <8 x i16> %x912}913 914define <16 x i16> @vror_vv_v16i16(<16 x i16> %a, <16 x i16> %b) {915; CHECK-LABEL: vror_vv_v16i16:916; CHECK: # %bb.0:917; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma918; CHECK-NEXT: vand.vi v12, v10, 15919; CHECK-NEXT: vrsub.vi v10, v10, 0920; CHECK-NEXT: vsrl.vv v12, v8, v12921; CHECK-NEXT: vand.vi v10, v10, 15922; CHECK-NEXT: vsll.vv v8, v8, v10923; CHECK-NEXT: vor.vv v8, v12, v8924; CHECK-NEXT: ret925;926; CHECK-ZVKB-LABEL: vror_vv_v16i16:927; CHECK-ZVKB: # %bb.0:928; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma929; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10930; CHECK-ZVKB-NEXT: ret931 %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b)932 ret <16 x i16> %x933}934 935define <16 x i16> @vror_vx_v16i16(<16 x i16> %a, i16 %b) {936; CHECK-LABEL: vror_vx_v16i16:937; CHECK: # %bb.0:938; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma939; CHECK-NEXT: vmv.v.x v10, a0940; CHECK-NEXT: vand.vi v12, v10, 15941; CHECK-NEXT: vrsub.vi v10, v10, 0942; CHECK-NEXT: vsrl.vv v12, v8, v12943; CHECK-NEXT: vand.vi v10, v10, 15944; CHECK-NEXT: vsll.vv v8, v8, v10945; CHECK-NEXT: vor.vv v8, v12, v8946; CHECK-NEXT: ret947;948; CHECK-ZVKB-LABEL: vror_vx_v16i16:949; CHECK-ZVKB: # %bb.0:950; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma951; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0952; CHECK-ZVKB-NEXT: ret953 %b.head = insertelement <16 x i16> poison, i16 %b, i32 0954 %b.splat = shufflevector <16 x i16> %b.head, <16 x i16> poison, <16 x i32> zeroinitializer955 %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b.splat)956 ret <16 x i16> %x957}958 959define <16 x i16> @vror_vi_v16i16(<16 x i16> %a) {960; CHECK-LABEL: vror_vi_v16i16:961; CHECK: # %bb.0:962; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma963; CHECK-NEXT: vsll.vi v10, v8, 15964; CHECK-NEXT: vsrl.vi v8, v8, 1965; CHECK-NEXT: vor.vv v8, v8, v10966; CHECK-NEXT: ret967;968; CHECK-ZVKB-LABEL: vror_vi_v16i16:969; CHECK-ZVKB: # %bb.0:970; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma971; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1972; CHECK-ZVKB-NEXT: ret973 %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> splat (i16 1))974 ret <16 x i16> %x975}976 977define <16 x i16> @vror_vi_rotl_v16i16(<16 x i16> %a) {978; CHECK-LABEL: vror_vi_rotl_v16i16:979; CHECK: # %bb.0:980; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma981; CHECK-NEXT: vsrl.vi v10, v8, 15982; CHECK-NEXT: vadd.vv v8, v8, v8983; CHECK-NEXT: vor.vv v8, v8, v10984; CHECK-NEXT: ret985;986; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i16:987; CHECK-ZVKB: # %bb.0:988; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma989; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15990; CHECK-ZVKB-NEXT: ret991 %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> splat (i16 1))992 ret <16 x i16> %x993}994 995define <32 x i16> @vror_vv_v32i16(<32 x i16> %a, <32 x i16> %b) {996; CHECK-LABEL: vror_vv_v32i16:997; CHECK: # %bb.0:998; CHECK-NEXT: li a0, 32999; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1000; CHECK-NEXT: vand.vi v16, v12, 151001; CHECK-NEXT: vrsub.vi v12, v12, 01002; CHECK-NEXT: vsrl.vv v16, v8, v161003; CHECK-NEXT: vand.vi v12, v12, 151004; CHECK-NEXT: vsll.vv v8, v8, v121005; CHECK-NEXT: vor.vv v8, v16, v81006; CHECK-NEXT: ret1007;1008; CHECK-ZVKB-LABEL: vror_vv_v32i16:1009; CHECK-ZVKB: # %bb.0:1010; CHECK-ZVKB-NEXT: li a0, 321011; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma1012; CHECK-ZVKB-NEXT: vror.vv v8, v8, v121013; CHECK-ZVKB-NEXT: ret1014 %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b)1015 ret <32 x i16> %x1016}1017 1018define <32 x i16> @vror_vx_v32i16(<32 x i16> %a, i16 %b) {1019; CHECK-LABEL: vror_vx_v32i16:1020; CHECK: # %bb.0:1021; CHECK-NEXT: li a1, 321022; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1023; CHECK-NEXT: vmv.v.x v12, a01024; CHECK-NEXT: vand.vi v16, v12, 151025; CHECK-NEXT: vrsub.vi v12, v12, 01026; CHECK-NEXT: vsrl.vv v16, v8, v161027; CHECK-NEXT: vand.vi v12, v12, 151028; CHECK-NEXT: vsll.vv v8, v8, v121029; CHECK-NEXT: vor.vv v8, v16, v81030; CHECK-NEXT: ret1031;1032; CHECK-ZVKB-LABEL: vror_vx_v32i16:1033; CHECK-ZVKB: # %bb.0:1034; CHECK-ZVKB-NEXT: li a1, 321035; CHECK-ZVKB-NEXT: vsetvli zero, a1, e16, m4, ta, ma1036; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01037; CHECK-ZVKB-NEXT: ret1038 %b.head = insertelement <32 x i16> poison, i16 %b, i32 01039 %b.splat = shufflevector <32 x i16> %b.head, <32 x i16> poison, <32 x i32> zeroinitializer1040 %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b.splat)1041 ret <32 x i16> %x1042}1043 1044define <32 x i16> @vror_vi_v32i16(<32 x i16> %a) {1045; CHECK-LABEL: vror_vi_v32i16:1046; CHECK: # %bb.0:1047; CHECK-NEXT: li a0, 321048; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1049; CHECK-NEXT: vsll.vi v12, v8, 151050; CHECK-NEXT: vsrl.vi v8, v8, 11051; CHECK-NEXT: vor.vv v8, v8, v121052; CHECK-NEXT: ret1053;1054; CHECK-ZVKB-LABEL: vror_vi_v32i16:1055; CHECK-ZVKB: # %bb.0:1056; CHECK-ZVKB-NEXT: li a0, 321057; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma1058; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11059; CHECK-ZVKB-NEXT: ret1060 %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> splat (i16 1))1061 ret <32 x i16> %x1062}1063 1064define <32 x i16> @vror_vi_rotl_v32i16(<32 x i16> %a) {1065; CHECK-LABEL: vror_vi_rotl_v32i16:1066; CHECK: # %bb.0:1067; CHECK-NEXT: li a0, 321068; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1069; CHECK-NEXT: vsrl.vi v12, v8, 151070; CHECK-NEXT: vadd.vv v8, v8, v81071; CHECK-NEXT: vor.vv v8, v8, v121072; CHECK-NEXT: ret1073;1074; CHECK-ZVKB-LABEL: vror_vi_rotl_v32i16:1075; CHECK-ZVKB: # %bb.0:1076; CHECK-ZVKB-NEXT: li a0, 321077; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma1078; CHECK-ZVKB-NEXT: vror.vi v8, v8, 151079; CHECK-ZVKB-NEXT: ret1080 %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> splat (i16 1))1081 ret <32 x i16> %x1082}1083 1084define <1 x i32> @vror_vv_v1i32(<1 x i32> %a, <1 x i32> %b) {1085; CHECK-LABEL: vror_vv_v1i32:1086; CHECK: # %bb.0:1087; CHECK-NEXT: li a0, 311088; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1089; CHECK-NEXT: vrsub.vi v10, v9, 01090; CHECK-NEXT: vand.vx v9, v9, a01091; CHECK-NEXT: vand.vx v10, v10, a01092; CHECK-NEXT: vsrl.vv v9, v8, v91093; CHECK-NEXT: vsll.vv v8, v8, v101094; CHECK-NEXT: vor.vv v8, v9, v81095; CHECK-NEXT: ret1096;1097; CHECK-ZVKB-LABEL: vror_vv_v1i32:1098; CHECK-ZVKB: # %bb.0:1099; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1100; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91101; CHECK-ZVKB-NEXT: ret1102 %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b)1103 ret <1 x i32> %x1104}1105 1106define <1 x i32> @vror_vx_v1i32(<1 x i32> %a, i32 %b) {1107; CHECK-LABEL: vror_vx_v1i32:1108; CHECK: # %bb.0:1109; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1110; CHECK-NEXT: vmv.s.x v9, a01111; CHECK-NEXT: li a0, 311112; CHECK-NEXT: vand.vx v10, v9, a01113; CHECK-NEXT: vrsub.vi v9, v9, 01114; CHECK-NEXT: vsrl.vv v10, v8, v101115; CHECK-NEXT: vand.vx v9, v9, a01116; CHECK-NEXT: vsll.vv v8, v8, v91117; CHECK-NEXT: vor.vv v8, v10, v81118; CHECK-NEXT: ret1119;1120; CHECK-ZVKB-LABEL: vror_vx_v1i32:1121; CHECK-ZVKB: # %bb.0:1122; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1123; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01124; CHECK-ZVKB-NEXT: ret1125 %b.head = insertelement <1 x i32> poison, i32 %b, i32 01126 %b.splat = shufflevector <1 x i32> %b.head, <1 x i32> poison, <1 x i32> zeroinitializer1127 %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b.splat)1128 ret <1 x i32> %x1129}1130 1131define <1 x i32> @vror_vi_v1i32(<1 x i32> %a) {1132; CHECK-LABEL: vror_vi_v1i32:1133; CHECK: # %bb.0:1134; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1135; CHECK-NEXT: vsll.vi v9, v8, 311136; CHECK-NEXT: vsrl.vi v8, v8, 11137; CHECK-NEXT: vor.vv v8, v8, v91138; CHECK-NEXT: ret1139;1140; CHECK-ZVKB-LABEL: vror_vi_v1i32:1141; CHECK-ZVKB: # %bb.0:1142; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1143; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11144; CHECK-ZVKB-NEXT: ret1145 %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> splat (i32 1))1146 ret <1 x i32> %x1147}1148 1149define <1 x i32> @vror_vi_rotl_v1i32(<1 x i32> %a) {1150; CHECK-LABEL: vror_vi_rotl_v1i32:1151; CHECK: # %bb.0:1152; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1153; CHECK-NEXT: vsrl.vi v9, v8, 311154; CHECK-NEXT: vadd.vv v8, v8, v81155; CHECK-NEXT: vor.vv v8, v8, v91156; CHECK-NEXT: ret1157;1158; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i32:1159; CHECK-ZVKB: # %bb.0:1160; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1161; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311162; CHECK-ZVKB-NEXT: ret1163 %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> splat (i32 1))1164 ret <1 x i32> %x1165}1166 1167define <2 x i32> @vror_vv_v2i32(<2 x i32> %a, <2 x i32> %b) {1168; CHECK-LABEL: vror_vv_v2i32:1169; CHECK: # %bb.0:1170; CHECK-NEXT: li a0, 311171; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1172; CHECK-NEXT: vrsub.vi v10, v9, 01173; CHECK-NEXT: vand.vx v9, v9, a01174; CHECK-NEXT: vand.vx v10, v10, a01175; CHECK-NEXT: vsrl.vv v9, v8, v91176; CHECK-NEXT: vsll.vv v8, v8, v101177; CHECK-NEXT: vor.vv v8, v9, v81178; CHECK-NEXT: ret1179;1180; CHECK-ZVKB-LABEL: vror_vv_v2i32:1181; CHECK-ZVKB: # %bb.0:1182; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1183; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91184; CHECK-ZVKB-NEXT: ret1185 %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b)1186 ret <2 x i32> %x1187}1188 1189define <2 x i32> @vror_vx_v2i32(<2 x i32> %a, i32 %b) {1190; CHECK-LABEL: vror_vx_v2i32:1191; CHECK: # %bb.0:1192; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1193; CHECK-NEXT: vmv.v.x v9, a01194; CHECK-NEXT: li a0, 311195; CHECK-NEXT: vand.vx v10, v9, a01196; CHECK-NEXT: vrsub.vi v9, v9, 01197; CHECK-NEXT: vsrl.vv v10, v8, v101198; CHECK-NEXT: vand.vx v9, v9, a01199; CHECK-NEXT: vsll.vv v8, v8, v91200; CHECK-NEXT: vor.vv v8, v10, v81201; CHECK-NEXT: ret1202;1203; CHECK-ZVKB-LABEL: vror_vx_v2i32:1204; CHECK-ZVKB: # %bb.0:1205; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1206; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01207; CHECK-ZVKB-NEXT: ret1208 %b.head = insertelement <2 x i32> poison, i32 %b, i32 01209 %b.splat = shufflevector <2 x i32> %b.head, <2 x i32> poison, <2 x i32> zeroinitializer1210 %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b.splat)1211 ret <2 x i32> %x1212}1213 1214define <2 x i32> @vror_vi_v2i32(<2 x i32> %a) {1215; CHECK-LABEL: vror_vi_v2i32:1216; CHECK: # %bb.0:1217; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1218; CHECK-NEXT: vsll.vi v9, v8, 311219; CHECK-NEXT: vsrl.vi v8, v8, 11220; CHECK-NEXT: vor.vv v8, v8, v91221; CHECK-NEXT: ret1222;1223; CHECK-ZVKB-LABEL: vror_vi_v2i32:1224; CHECK-ZVKB: # %bb.0:1225; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1226; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11227; CHECK-ZVKB-NEXT: ret1228 %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> splat (i32 1))1229 ret <2 x i32> %x1230}1231 1232define <2 x i32> @vror_vi_rotl_v2i32(<2 x i32> %a) {1233; CHECK-LABEL: vror_vi_rotl_v2i32:1234; CHECK: # %bb.0:1235; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1236; CHECK-NEXT: vsrl.vi v9, v8, 311237; CHECK-NEXT: vadd.vv v8, v8, v81238; CHECK-NEXT: vor.vv v8, v8, v91239; CHECK-NEXT: ret1240;1241; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i32:1242; CHECK-ZVKB: # %bb.0:1243; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1244; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311245; CHECK-ZVKB-NEXT: ret1246 %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> splat (i32 1))1247 ret <2 x i32> %x1248}1249 1250define <4 x i32> @vror_vv_v4i32(<4 x i32> %a, <4 x i32> %b) {1251; CHECK-LABEL: vror_vv_v4i32:1252; CHECK: # %bb.0:1253; CHECK-NEXT: li a0, 311254; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1255; CHECK-NEXT: vrsub.vi v10, v9, 01256; CHECK-NEXT: vand.vx v9, v9, a01257; CHECK-NEXT: vand.vx v10, v10, a01258; CHECK-NEXT: vsrl.vv v9, v8, v91259; CHECK-NEXT: vsll.vv v8, v8, v101260; CHECK-NEXT: vor.vv v8, v9, v81261; CHECK-NEXT: ret1262;1263; CHECK-ZVKB-LABEL: vror_vv_v4i32:1264; CHECK-ZVKB: # %bb.0:1265; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1266; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91267; CHECK-ZVKB-NEXT: ret1268 %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b)1269 ret <4 x i32> %x1270}1271 1272define <4 x i32> @vror_vx_v4i32(<4 x i32> %a, i32 %b) {1273; CHECK-LABEL: vror_vx_v4i32:1274; CHECK: # %bb.0:1275; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1276; CHECK-NEXT: vmv.v.x v9, a01277; CHECK-NEXT: li a0, 311278; CHECK-NEXT: vand.vx v10, v9, a01279; CHECK-NEXT: vrsub.vi v9, v9, 01280; CHECK-NEXT: vsrl.vv v10, v8, v101281; CHECK-NEXT: vand.vx v9, v9, a01282; CHECK-NEXT: vsll.vv v8, v8, v91283; CHECK-NEXT: vor.vv v8, v10, v81284; CHECK-NEXT: ret1285;1286; CHECK-ZVKB-LABEL: vror_vx_v4i32:1287; CHECK-ZVKB: # %bb.0:1288; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1289; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01290; CHECK-ZVKB-NEXT: ret1291 %b.head = insertelement <4 x i32> poison, i32 %b, i32 01292 %b.splat = shufflevector <4 x i32> %b.head, <4 x i32> poison, <4 x i32> zeroinitializer1293 %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b.splat)1294 ret <4 x i32> %x1295}1296 1297define <4 x i32> @vror_vi_v4i32(<4 x i32> %a) {1298; CHECK-LABEL: vror_vi_v4i32:1299; CHECK: # %bb.0:1300; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1301; CHECK-NEXT: vsll.vi v9, v8, 311302; CHECK-NEXT: vsrl.vi v8, v8, 11303; CHECK-NEXT: vor.vv v8, v8, v91304; CHECK-NEXT: ret1305;1306; CHECK-ZVKB-LABEL: vror_vi_v4i32:1307; CHECK-ZVKB: # %bb.0:1308; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1309; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11310; CHECK-ZVKB-NEXT: ret1311 %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 1))1312 ret <4 x i32> %x1313}1314 1315define <4 x i32> @vror_vi_rotl_v4i32(<4 x i32> %a) {1316; CHECK-LABEL: vror_vi_rotl_v4i32:1317; CHECK: # %bb.0:1318; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1319; CHECK-NEXT: vsrl.vi v9, v8, 311320; CHECK-NEXT: vadd.vv v8, v8, v81321; CHECK-NEXT: vor.vv v8, v8, v91322; CHECK-NEXT: ret1323;1324; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i32:1325; CHECK-ZVKB: # %bb.0:1326; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1327; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311328; CHECK-ZVKB-NEXT: ret1329 %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 1))1330 ret <4 x i32> %x1331}1332 1333define <8 x i32> @vror_vv_v8i32(<8 x i32> %a, <8 x i32> %b) {1334; CHECK-LABEL: vror_vv_v8i32:1335; CHECK: # %bb.0:1336; CHECK-NEXT: li a0, 311337; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1338; CHECK-NEXT: vrsub.vi v12, v10, 01339; CHECK-NEXT: vand.vx v10, v10, a01340; CHECK-NEXT: vand.vx v12, v12, a01341; CHECK-NEXT: vsrl.vv v10, v8, v101342; CHECK-NEXT: vsll.vv v8, v8, v121343; CHECK-NEXT: vor.vv v8, v10, v81344; CHECK-NEXT: ret1345;1346; CHECK-ZVKB-LABEL: vror_vv_v8i32:1347; CHECK-ZVKB: # %bb.0:1348; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma1349; CHECK-ZVKB-NEXT: vror.vv v8, v8, v101350; CHECK-ZVKB-NEXT: ret1351 %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b)1352 ret <8 x i32> %x1353}1354 1355define <8 x i32> @vror_vx_v8i32(<8 x i32> %a, i32 %b) {1356; CHECK-LABEL: vror_vx_v8i32:1357; CHECK: # %bb.0:1358; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1359; CHECK-NEXT: vmv.v.x v10, a01360; CHECK-NEXT: li a0, 311361; CHECK-NEXT: vand.vx v12, v10, a01362; CHECK-NEXT: vrsub.vi v10, v10, 01363; CHECK-NEXT: vsrl.vv v12, v8, v121364; CHECK-NEXT: vand.vx v10, v10, a01365; CHECK-NEXT: vsll.vv v8, v8, v101366; CHECK-NEXT: vor.vv v8, v12, v81367; CHECK-NEXT: ret1368;1369; CHECK-ZVKB-LABEL: vror_vx_v8i32:1370; CHECK-ZVKB: # %bb.0:1371; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma1372; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01373; CHECK-ZVKB-NEXT: ret1374 %b.head = insertelement <8 x i32> poison, i32 %b, i32 01375 %b.splat = shufflevector <8 x i32> %b.head, <8 x i32> poison, <8 x i32> zeroinitializer1376 %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b.splat)1377 ret <8 x i32> %x1378}1379 1380define <8 x i32> @vror_vi_v8i32(<8 x i32> %a) {1381; CHECK-LABEL: vror_vi_v8i32:1382; CHECK: # %bb.0:1383; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1384; CHECK-NEXT: vsll.vi v10, v8, 311385; CHECK-NEXT: vsrl.vi v8, v8, 11386; CHECK-NEXT: vor.vv v8, v8, v101387; CHECK-NEXT: ret1388;1389; CHECK-ZVKB-LABEL: vror_vi_v8i32:1390; CHECK-ZVKB: # %bb.0:1391; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma1392; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11393; CHECK-ZVKB-NEXT: ret1394 %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> splat (i32 1))1395 ret <8 x i32> %x1396}1397 1398define <8 x i32> @vror_vi_rotl_v8i32(<8 x i32> %a) {1399; CHECK-LABEL: vror_vi_rotl_v8i32:1400; CHECK: # %bb.0:1401; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1402; CHECK-NEXT: vsrl.vi v10, v8, 311403; CHECK-NEXT: vadd.vv v8, v8, v81404; CHECK-NEXT: vor.vv v8, v8, v101405; CHECK-NEXT: ret1406;1407; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i32:1408; CHECK-ZVKB: # %bb.0:1409; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma1410; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311411; CHECK-ZVKB-NEXT: ret1412 %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> splat (i32 1))1413 ret <8 x i32> %x1414}1415 1416define <16 x i32> @vror_vv_v16i32(<16 x i32> %a, <16 x i32> %b) {1417; CHECK-LABEL: vror_vv_v16i32:1418; CHECK: # %bb.0:1419; CHECK-NEXT: li a0, 311420; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1421; CHECK-NEXT: vrsub.vi v16, v12, 01422; CHECK-NEXT: vand.vx v12, v12, a01423; CHECK-NEXT: vand.vx v16, v16, a01424; CHECK-NEXT: vsrl.vv v12, v8, v121425; CHECK-NEXT: vsll.vv v8, v8, v161426; CHECK-NEXT: vor.vv v8, v12, v81427; CHECK-NEXT: ret1428;1429; CHECK-ZVKB-LABEL: vror_vv_v16i32:1430; CHECK-ZVKB: # %bb.0:1431; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma1432; CHECK-ZVKB-NEXT: vror.vv v8, v8, v121433; CHECK-ZVKB-NEXT: ret1434 %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b)1435 ret <16 x i32> %x1436}1437 1438define <16 x i32> @vror_vx_v16i32(<16 x i32> %a, i32 %b) {1439; CHECK-LABEL: vror_vx_v16i32:1440; CHECK: # %bb.0:1441; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1442; CHECK-NEXT: vmv.v.x v12, a01443; CHECK-NEXT: li a0, 311444; CHECK-NEXT: vand.vx v16, v12, a01445; CHECK-NEXT: vrsub.vi v12, v12, 01446; CHECK-NEXT: vsrl.vv v16, v8, v161447; CHECK-NEXT: vand.vx v12, v12, a01448; CHECK-NEXT: vsll.vv v8, v8, v121449; CHECK-NEXT: vor.vv v8, v16, v81450; CHECK-NEXT: ret1451;1452; CHECK-ZVKB-LABEL: vror_vx_v16i32:1453; CHECK-ZVKB: # %bb.0:1454; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma1455; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01456; CHECK-ZVKB-NEXT: ret1457 %b.head = insertelement <16 x i32> poison, i32 %b, i32 01458 %b.splat = shufflevector <16 x i32> %b.head, <16 x i32> poison, <16 x i32> zeroinitializer1459 %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b.splat)1460 ret <16 x i32> %x1461}1462 1463define <16 x i32> @vror_vi_v16i32(<16 x i32> %a) {1464; CHECK-LABEL: vror_vi_v16i32:1465; CHECK: # %bb.0:1466; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1467; CHECK-NEXT: vsll.vi v12, v8, 311468; CHECK-NEXT: vsrl.vi v8, v8, 11469; CHECK-NEXT: vor.vv v8, v8, v121470; CHECK-NEXT: ret1471;1472; CHECK-ZVKB-LABEL: vror_vi_v16i32:1473; CHECK-ZVKB: # %bb.0:1474; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma1475; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11476; CHECK-ZVKB-NEXT: ret1477 %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> splat (i32 1))1478 ret <16 x i32> %x1479}1480 1481define <16 x i32> @vror_vi_rotl_v16i32(<16 x i32> %a) {1482; CHECK-LABEL: vror_vi_rotl_v16i32:1483; CHECK: # %bb.0:1484; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma1485; CHECK-NEXT: vsrl.vi v12, v8, 311486; CHECK-NEXT: vadd.vv v8, v8, v81487; CHECK-NEXT: vor.vv v8, v8, v121488; CHECK-NEXT: ret1489;1490; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i32:1491; CHECK-ZVKB: # %bb.0:1492; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma1493; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311494; CHECK-ZVKB-NEXT: ret1495 %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> splat (i32 1))1496 ret <16 x i32> %x1497}1498 1499define <1 x i64> @vror_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {1500; CHECK-LABEL: vror_vv_v1i64:1501; CHECK: # %bb.0:1502; CHECK-NEXT: li a0, 631503; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma1504; CHECK-NEXT: vrsub.vi v10, v9, 01505; CHECK-NEXT: vand.vx v9, v9, a01506; CHECK-NEXT: vand.vx v10, v10, a01507; CHECK-NEXT: vsrl.vv v9, v8, v91508; CHECK-NEXT: vsll.vv v8, v8, v101509; CHECK-NEXT: vor.vv v8, v9, v81510; CHECK-NEXT: ret1511;1512; CHECK-ZVKB-LABEL: vror_vv_v1i64:1513; CHECK-ZVKB: # %bb.0:1514; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma1515; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91516; CHECK-ZVKB-NEXT: ret1517 %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)1518 ret <1 x i64> %x1519}1520 1521define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) {1522; CHECK-LABEL: vror_vx_v1i64:1523; CHECK: # %bb.0:1524; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma1525; CHECK-NEXT: vmv.s.x v9, a01526; CHECK-NEXT: li a0, 631527; CHECK-NEXT: vand.vx v10, v9, a01528; CHECK-NEXT: vrsub.vi v9, v9, 01529; CHECK-NEXT: vsrl.vv v10, v8, v101530; CHECK-NEXT: vand.vx v9, v9, a01531; CHECK-NEXT: vsll.vv v8, v8, v91532; CHECK-NEXT: vor.vv v8, v10, v81533; CHECK-NEXT: ret1534;1535; CHECK-ZVKB-LABEL: vror_vx_v1i64:1536; CHECK-ZVKB: # %bb.0:1537; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma1538; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01539; CHECK-ZVKB-NEXT: ret1540 %b.head = insertelement <1 x i64> poison, i64 %b, i32 01541 %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer1542 %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)1543 ret <1 x i64> %x1544}1545 1546define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) {1547; CHECK-RV32-LABEL: vror_vi_v1i64:1548; CHECK-RV32: # %bb.0:1549; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1550; CHECK-RV32-NEXT: vmv.v.i v9, 11551; CHECK-RV32-NEXT: li a0, 631552; CHECK-RV32-NEXT: vrsub.vi v9, v9, 01553; CHECK-RV32-NEXT: vmv.s.x v10, a01554; CHECK-RV32-NEXT: vand.vx v9, v9, a01555; CHECK-RV32-NEXT: vand.vi v10, v10, 11556; CHECK-RV32-NEXT: vsll.vv v9, v8, v91557; CHECK-RV32-NEXT: vsrl.vv v8, v8, v101558; CHECK-RV32-NEXT: vor.vv v8, v8, v91559; CHECK-RV32-NEXT: ret1560;1561; CHECK-RV64-LABEL: vror_vi_v1i64:1562; CHECK-RV64: # %bb.0:1563; CHECK-RV64-NEXT: li a0, 631564; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1565; CHECK-RV64-NEXT: vsll.vx v9, v8, a01566; CHECK-RV64-NEXT: vsrl.vi v8, v8, 11567; CHECK-RV64-NEXT: vor.vv v8, v8, v91568; CHECK-RV64-NEXT: ret1569;1570; CHECK-ZVKB-LABEL: vror_vi_v1i64:1571; CHECK-ZVKB: # %bb.0:1572; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma1573; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11574; CHECK-ZVKB-NEXT: ret1575 %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> splat (i64 1))1576 ret <1 x i64> %x1577}1578 1579define <1 x i64> @vror_vi_rotl_v1i64(<1 x i64> %a) {1580; CHECK-RV32-LABEL: vror_vi_rotl_v1i64:1581; CHECK-RV32: # %bb.0:1582; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1583; CHECK-RV32-NEXT: vmv.v.i v9, 11584; CHECK-RV32-NEXT: li a0, 631585; CHECK-RV32-NEXT: vrsub.vi v9, v9, 01586; CHECK-RV32-NEXT: vmv.s.x v10, a01587; CHECK-RV32-NEXT: vand.vx v9, v9, a01588; CHECK-RV32-NEXT: vand.vi v10, v10, 11589; CHECK-RV32-NEXT: vsrl.vv v9, v8, v91590; CHECK-RV32-NEXT: vsll.vv v8, v8, v101591; CHECK-RV32-NEXT: vor.vv v8, v8, v91592; CHECK-RV32-NEXT: ret1593;1594; CHECK-RV64-LABEL: vror_vi_rotl_v1i64:1595; CHECK-RV64: # %bb.0:1596; CHECK-RV64-NEXT: li a0, 631597; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1598; CHECK-RV64-NEXT: vsrl.vx v9, v8, a01599; CHECK-RV64-NEXT: vadd.vv v8, v8, v81600; CHECK-RV64-NEXT: vor.vv v8, v8, v91601; CHECK-RV64-NEXT: ret1602;1603; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i64:1604; CHECK-ZVKB: # %bb.0:1605; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma1606; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631607; CHECK-ZVKB-NEXT: ret1608 %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> splat (i64 1))1609 ret <1 x i64> %x1610}1611 1612define <2 x i64> @vror_vv_v2i64(<2 x i64> %a, <2 x i64> %b) {1613; CHECK-LABEL: vror_vv_v2i64:1614; CHECK: # %bb.0:1615; CHECK-NEXT: li a0, 631616; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma1617; CHECK-NEXT: vrsub.vi v10, v9, 01618; CHECK-NEXT: vand.vx v9, v9, a01619; CHECK-NEXT: vand.vx v10, v10, a01620; CHECK-NEXT: vsrl.vv v9, v8, v91621; CHECK-NEXT: vsll.vv v8, v8, v101622; CHECK-NEXT: vor.vv v8, v9, v81623; CHECK-NEXT: ret1624;1625; CHECK-ZVKB-LABEL: vror_vv_v2i64:1626; CHECK-ZVKB: # %bb.0:1627; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma1628; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91629; CHECK-ZVKB-NEXT: ret1630 %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b)1631 ret <2 x i64> %x1632}1633 1634define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) {1635; CHECK-RV32-LABEL: vror_vx_v2i64:1636; CHECK-RV32: # %bb.0:1637; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1638; CHECK-RV32-NEXT: vmv.v.x v9, a01639; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1640; CHECK-RV32-NEXT: vmv.v.i v10, 01641; CHECK-RV32-NEXT: vwsub.vx v11, v10, a01642; CHECK-RV32-NEXT: li a0, 631643; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma1644; CHECK-RV32-NEXT: vand.vx v9, v9, a01645; CHECK-RV32-NEXT: vand.vx v10, v11, a01646; CHECK-RV32-NEXT: vsll.vv v10, v8, v101647; CHECK-RV32-NEXT: vsrl.vv v8, v8, v91648; CHECK-RV32-NEXT: vor.vv v8, v8, v101649; CHECK-RV32-NEXT: ret1650;1651; CHECK-RV64-LABEL: vror_vx_v2i64:1652; CHECK-RV64: # %bb.0:1653; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1654; CHECK-RV64-NEXT: vmv.v.x v9, a01655; CHECK-RV64-NEXT: li a0, 631656; CHECK-RV64-NEXT: vand.vx v10, v9, a01657; CHECK-RV64-NEXT: vrsub.vi v9, v9, 01658; CHECK-RV64-NEXT: vsrl.vv v10, v8, v101659; CHECK-RV64-NEXT: vand.vx v9, v9, a01660; CHECK-RV64-NEXT: vsll.vv v8, v8, v91661; CHECK-RV64-NEXT: vor.vv v8, v10, v81662; CHECK-RV64-NEXT: ret1663;1664; CHECK-ZVKB-LABEL: vror_vx_v2i64:1665; CHECK-ZVKB: # %bb.0:1666; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma1667; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01668; CHECK-ZVKB-NEXT: ret1669 %b.head = insertelement <2 x i64> poison, i64 %b, i32 01670 %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer1671 %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)1672 ret <2 x i64> %x1673}1674 1675define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {1676; CHECK-RV32-LABEL: vror_vi_v2i64:1677; CHECK-RV32: # %bb.0:1678; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1679; CHECK-RV32-NEXT: vmv.v.i v9, 01680; CHECK-RV32-NEXT: li a0, 11681; CHECK-RV32-NEXT: vwsubu.vx v10, v9, a01682; CHECK-RV32-NEXT: li a0, 631683; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma1684; CHECK-RV32-NEXT: vmv.v.x v9, a01685; CHECK-RV32-NEXT: vand.vx v10, v10, a01686; CHECK-RV32-NEXT: vand.vi v9, v9, 11687; CHECK-RV32-NEXT: vsll.vv v10, v8, v101688; CHECK-RV32-NEXT: vsrl.vv v8, v8, v91689; CHECK-RV32-NEXT: vor.vv v8, v8, v101690; CHECK-RV32-NEXT: ret1691;1692; CHECK-RV64-LABEL: vror_vi_v2i64:1693; CHECK-RV64: # %bb.0:1694; CHECK-RV64-NEXT: li a0, 631695; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1696; CHECK-RV64-NEXT: vsll.vx v9, v8, a01697; CHECK-RV64-NEXT: vsrl.vi v8, v8, 11698; CHECK-RV64-NEXT: vor.vv v8, v8, v91699; CHECK-RV64-NEXT: ret1700;1701; CHECK-ZVKB-LABEL: vror_vi_v2i64:1702; CHECK-ZVKB: # %bb.0:1703; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma1704; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11705; CHECK-ZVKB-NEXT: ret1706 %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1))1707 ret <2 x i64> %x1708}1709 1710define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) {1711; CHECK-RV32-LABEL: vror_vi_rotl_v2i64:1712; CHECK-RV32: # %bb.0:1713; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma1714; CHECK-RV32-NEXT: vmv.v.i v9, 01715; CHECK-RV32-NEXT: li a0, 11716; CHECK-RV32-NEXT: vwsubu.vx v10, v9, a01717; CHECK-RV32-NEXT: li a0, 631718; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma1719; CHECK-RV32-NEXT: vmv.v.x v9, a01720; CHECK-RV32-NEXT: vand.vx v10, v10, a01721; CHECK-RV32-NEXT: vand.vi v9, v9, 11722; CHECK-RV32-NEXT: vsrl.vv v10, v8, v101723; CHECK-RV32-NEXT: vsll.vv v8, v8, v91724; CHECK-RV32-NEXT: vor.vv v8, v8, v101725; CHECK-RV32-NEXT: ret1726;1727; CHECK-RV64-LABEL: vror_vi_rotl_v2i64:1728; CHECK-RV64: # %bb.0:1729; CHECK-RV64-NEXT: li a0, 631730; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma1731; CHECK-RV64-NEXT: vsrl.vx v9, v8, a01732; CHECK-RV64-NEXT: vadd.vv v8, v8, v81733; CHECK-RV64-NEXT: vor.vv v8, v8, v91734; CHECK-RV64-NEXT: ret1735;1736; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i64:1737; CHECK-ZVKB: # %bb.0:1738; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma1739; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631740; CHECK-ZVKB-NEXT: ret1741 %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1))1742 ret <2 x i64> %x1743}1744 1745define <4 x i64> @vror_vv_v4i64(<4 x i64> %a, <4 x i64> %b) {1746; CHECK-LABEL: vror_vv_v4i64:1747; CHECK: # %bb.0:1748; CHECK-NEXT: li a0, 631749; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma1750; CHECK-NEXT: vrsub.vi v12, v10, 01751; CHECK-NEXT: vand.vx v10, v10, a01752; CHECK-NEXT: vand.vx v12, v12, a01753; CHECK-NEXT: vsrl.vv v10, v8, v101754; CHECK-NEXT: vsll.vv v8, v8, v121755; CHECK-NEXT: vor.vv v8, v10, v81756; CHECK-NEXT: ret1757;1758; CHECK-ZVKB-LABEL: vror_vv_v4i64:1759; CHECK-ZVKB: # %bb.0:1760; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma1761; CHECK-ZVKB-NEXT: vror.vv v8, v8, v101762; CHECK-ZVKB-NEXT: ret1763 %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b)1764 ret <4 x i64> %x1765}1766 1767define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) {1768; CHECK-RV32-LABEL: vror_vx_v4i64:1769; CHECK-RV32: # %bb.0:1770; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1771; CHECK-RV32-NEXT: vmv.v.x v10, a01772; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma1773; CHECK-RV32-NEXT: vmv.v.i v14, 01774; CHECK-RV32-NEXT: vwsub.vx v12, v14, a01775; CHECK-RV32-NEXT: li a0, 631776; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma1777; CHECK-RV32-NEXT: vand.vx v10, v10, a01778; CHECK-RV32-NEXT: vand.vx v12, v12, a01779; CHECK-RV32-NEXT: vsll.vv v12, v8, v121780; CHECK-RV32-NEXT: vsrl.vv v8, v8, v101781; CHECK-RV32-NEXT: vor.vv v8, v8, v121782; CHECK-RV32-NEXT: ret1783;1784; CHECK-RV64-LABEL: vror_vx_v4i64:1785; CHECK-RV64: # %bb.0:1786; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1787; CHECK-RV64-NEXT: vmv.v.x v10, a01788; CHECK-RV64-NEXT: li a0, 631789; CHECK-RV64-NEXT: vand.vx v12, v10, a01790; CHECK-RV64-NEXT: vrsub.vi v10, v10, 01791; CHECK-RV64-NEXT: vsrl.vv v12, v8, v121792; CHECK-RV64-NEXT: vand.vx v10, v10, a01793; CHECK-RV64-NEXT: vsll.vv v8, v8, v101794; CHECK-RV64-NEXT: vor.vv v8, v12, v81795; CHECK-RV64-NEXT: ret1796;1797; CHECK-ZVKB-LABEL: vror_vx_v4i64:1798; CHECK-ZVKB: # %bb.0:1799; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma1800; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01801; CHECK-ZVKB-NEXT: ret1802 %b.head = insertelement <4 x i64> poison, i64 %b, i32 01803 %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer1804 %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)1805 ret <4 x i64> %x1806}1807 1808define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {1809; CHECK-RV32-LABEL: vror_vi_v4i64:1810; CHECK-RV32: # %bb.0:1811; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1812; CHECK-RV32-NEXT: vmv.v.i v12, 01813; CHECK-RV32-NEXT: li a0, 11814; CHECK-RV32-NEXT: vwsubu.vx v10, v12, a01815; CHECK-RV32-NEXT: li a0, 631816; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma1817; CHECK-RV32-NEXT: vmv.v.x v12, a01818; CHECK-RV32-NEXT: vand.vx v10, v10, a01819; CHECK-RV32-NEXT: vand.vi v12, v12, 11820; CHECK-RV32-NEXT: vsll.vv v10, v8, v101821; CHECK-RV32-NEXT: vsrl.vv v8, v8, v121822; CHECK-RV32-NEXT: vor.vv v8, v8, v101823; CHECK-RV32-NEXT: ret1824;1825; CHECK-RV64-LABEL: vror_vi_v4i64:1826; CHECK-RV64: # %bb.0:1827; CHECK-RV64-NEXT: li a0, 631828; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1829; CHECK-RV64-NEXT: vsll.vx v10, v8, a01830; CHECK-RV64-NEXT: vsrl.vi v8, v8, 11831; CHECK-RV64-NEXT: vor.vv v8, v8, v101832; CHECK-RV64-NEXT: ret1833;1834; CHECK-ZVKB-LABEL: vror_vi_v4i64:1835; CHECK-ZVKB: # %bb.0:1836; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma1837; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11838; CHECK-ZVKB-NEXT: ret1839 %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> splat (i64 1))1840 ret <4 x i64> %x1841}1842 1843define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) {1844; CHECK-RV32-LABEL: vror_vi_rotl_v4i64:1845; CHECK-RV32: # %bb.0:1846; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma1847; CHECK-RV32-NEXT: vmv.v.i v12, 01848; CHECK-RV32-NEXT: li a0, 11849; CHECK-RV32-NEXT: vwsubu.vx v10, v12, a01850; CHECK-RV32-NEXT: li a0, 631851; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma1852; CHECK-RV32-NEXT: vmv.v.x v12, a01853; CHECK-RV32-NEXT: vand.vx v10, v10, a01854; CHECK-RV32-NEXT: vand.vi v12, v12, 11855; CHECK-RV32-NEXT: vsrl.vv v10, v8, v101856; CHECK-RV32-NEXT: vsll.vv v8, v8, v121857; CHECK-RV32-NEXT: vor.vv v8, v8, v101858; CHECK-RV32-NEXT: ret1859;1860; CHECK-RV64-LABEL: vror_vi_rotl_v4i64:1861; CHECK-RV64: # %bb.0:1862; CHECK-RV64-NEXT: li a0, 631863; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma1864; CHECK-RV64-NEXT: vsrl.vx v10, v8, a01865; CHECK-RV64-NEXT: vadd.vv v8, v8, v81866; CHECK-RV64-NEXT: vor.vv v8, v8, v101867; CHECK-RV64-NEXT: ret1868;1869; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i64:1870; CHECK-ZVKB: # %bb.0:1871; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma1872; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631873; CHECK-ZVKB-NEXT: ret1874 %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> splat (i64 1))1875 ret <4 x i64> %x1876}1877 1878define <8 x i64> @vror_vv_v8i64(<8 x i64> %a, <8 x i64> %b) {1879; CHECK-LABEL: vror_vv_v8i64:1880; CHECK: # %bb.0:1881; CHECK-NEXT: li a0, 631882; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma1883; CHECK-NEXT: vrsub.vi v16, v12, 01884; CHECK-NEXT: vand.vx v12, v12, a01885; CHECK-NEXT: vand.vx v16, v16, a01886; CHECK-NEXT: vsrl.vv v12, v8, v121887; CHECK-NEXT: vsll.vv v8, v8, v161888; CHECK-NEXT: vor.vv v8, v12, v81889; CHECK-NEXT: ret1890;1891; CHECK-ZVKB-LABEL: vror_vv_v8i64:1892; CHECK-ZVKB: # %bb.0:1893; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma1894; CHECK-ZVKB-NEXT: vror.vv v8, v8, v121895; CHECK-ZVKB-NEXT: ret1896 %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b)1897 ret <8 x i64> %x1898}1899 1900define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) {1901; CHECK-RV32-LABEL: vror_vx_v8i64:1902; CHECK-RV32: # %bb.0:1903; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1904; CHECK-RV32-NEXT: vmv.v.x v12, a01905; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1906; CHECK-RV32-NEXT: vmv.v.i v20, 01907; CHECK-RV32-NEXT: vwsub.vx v16, v20, a01908; CHECK-RV32-NEXT: li a0, 631909; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma1910; CHECK-RV32-NEXT: vand.vx v12, v12, a01911; CHECK-RV32-NEXT: vand.vx v16, v16, a01912; CHECK-RV32-NEXT: vsll.vv v16, v8, v161913; CHECK-RV32-NEXT: vsrl.vv v8, v8, v121914; CHECK-RV32-NEXT: vor.vv v8, v8, v161915; CHECK-RV32-NEXT: ret1916;1917; CHECK-RV64-LABEL: vror_vx_v8i64:1918; CHECK-RV64: # %bb.0:1919; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1920; CHECK-RV64-NEXT: vmv.v.x v12, a01921; CHECK-RV64-NEXT: li a0, 631922; CHECK-RV64-NEXT: vand.vx v16, v12, a01923; CHECK-RV64-NEXT: vrsub.vi v12, v12, 01924; CHECK-RV64-NEXT: vsrl.vv v16, v8, v161925; CHECK-RV64-NEXT: vand.vx v12, v12, a01926; CHECK-RV64-NEXT: vsll.vv v8, v8, v121927; CHECK-RV64-NEXT: vor.vv v8, v16, v81928; CHECK-RV64-NEXT: ret1929;1930; CHECK-ZVKB-LABEL: vror_vx_v8i64:1931; CHECK-ZVKB: # %bb.0:1932; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma1933; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01934; CHECK-ZVKB-NEXT: ret1935 %b.head = insertelement <8 x i64> poison, i64 %b, i32 01936 %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer1937 %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)1938 ret <8 x i64> %x1939}1940 1941define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {1942; CHECK-RV32-LABEL: vror_vi_v8i64:1943; CHECK-RV32: # %bb.0:1944; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1945; CHECK-RV32-NEXT: vmv.v.i v16, 01946; CHECK-RV32-NEXT: li a0, 11947; CHECK-RV32-NEXT: vwsubu.vx v12, v16, a01948; CHECK-RV32-NEXT: li a0, 631949; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma1950; CHECK-RV32-NEXT: vmv.v.x v16, a01951; CHECK-RV32-NEXT: vand.vx v12, v12, a01952; CHECK-RV32-NEXT: vand.vi v16, v16, 11953; CHECK-RV32-NEXT: vsll.vv v12, v8, v121954; CHECK-RV32-NEXT: vsrl.vv v8, v8, v161955; CHECK-RV32-NEXT: vor.vv v8, v8, v121956; CHECK-RV32-NEXT: ret1957;1958; CHECK-RV64-LABEL: vror_vi_v8i64:1959; CHECK-RV64: # %bb.0:1960; CHECK-RV64-NEXT: li a0, 631961; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1962; CHECK-RV64-NEXT: vsll.vx v12, v8, a01963; CHECK-RV64-NEXT: vsrl.vi v8, v8, 11964; CHECK-RV64-NEXT: vor.vv v8, v8, v121965; CHECK-RV64-NEXT: ret1966;1967; CHECK-ZVKB-LABEL: vror_vi_v8i64:1968; CHECK-ZVKB: # %bb.0:1969; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma1970; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11971; CHECK-ZVKB-NEXT: ret1972 %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> splat (i64 1))1973 ret <8 x i64> %x1974}1975 1976define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) {1977; CHECK-RV32-LABEL: vror_vi_rotl_v8i64:1978; CHECK-RV32: # %bb.0:1979; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma1980; CHECK-RV32-NEXT: vmv.v.i v16, 01981; CHECK-RV32-NEXT: li a0, 11982; CHECK-RV32-NEXT: vwsubu.vx v12, v16, a01983; CHECK-RV32-NEXT: li a0, 631984; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma1985; CHECK-RV32-NEXT: vmv.v.x v16, a01986; CHECK-RV32-NEXT: vand.vx v12, v12, a01987; CHECK-RV32-NEXT: vand.vi v16, v16, 11988; CHECK-RV32-NEXT: vsrl.vv v12, v8, v121989; CHECK-RV32-NEXT: vsll.vv v8, v8, v161990; CHECK-RV32-NEXT: vor.vv v8, v8, v121991; CHECK-RV32-NEXT: ret1992;1993; CHECK-RV64-LABEL: vror_vi_rotl_v8i64:1994; CHECK-RV64: # %bb.0:1995; CHECK-RV64-NEXT: li a0, 631996; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma1997; CHECK-RV64-NEXT: vsrl.vx v12, v8, a01998; CHECK-RV64-NEXT: vadd.vv v8, v8, v81999; CHECK-RV64-NEXT: vor.vv v8, v8, v122000; CHECK-RV64-NEXT: ret2001;2002; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i64:2003; CHECK-ZVKB: # %bb.0:2004; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma2005; CHECK-ZVKB-NEXT: vror.vi v8, v8, 632006; CHECK-ZVKB-NEXT: ret2007 %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> splat (i64 1))2008 ret <8 x i64> %x2009}2010