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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i8> @vrsub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vrsub_vx_v2i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t12; CHECK-NEXT: ret13 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 014 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer15 %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl)16 ret <2 x i8> %v17}18 19define <2 x i8> @vrsub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {20; CHECK-LABEL: vrsub_vx_v2i8_unmasked:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma23; CHECK-NEXT: vrsub.vx v8, v8, a024; CHECK-NEXT: ret25 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 026 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer27 %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl)28 ret <2 x i8> %v29}30 31define <2 x i8> @vrsub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {32; CHECK-LABEL: vrsub_vi_v2i8:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma35; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t36; CHECK-NEXT: ret37 %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> splat (i8 2), <2 x i8> %va, <2 x i1> %m, i32 %evl)38 ret <2 x i8> %v39}40 41define <2 x i8> @vrsub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {42; CHECK-LABEL: vrsub_vi_v2i8_unmasked:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma45; CHECK-NEXT: vrsub.vi v8, v8, 246; CHECK-NEXT: ret47 %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> splat (i8 2), <2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl)48 ret <2 x i8> %v49}50 51define <4 x i8> @vrsub_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: vrsub_vx_v4i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma55; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t56; CHECK-NEXT: ret57 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 058 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer59 %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)60 ret <4 x i8> %v61}62 63define <4 x i8> @vrsub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {64; CHECK-LABEL: vrsub_vx_v4i8_unmasked:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma67; CHECK-NEXT: vrsub.vx v8, v8, a068; CHECK-NEXT: ret69 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 070 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer71 %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)72 ret <4 x i8> %v73}74 75define <4 x i8> @vrsub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {76; CHECK-LABEL: vrsub_vi_v4i8:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma79; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t80; CHECK-NEXT: ret81 %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> splat (i8 2), <4 x i8> %va, <4 x i1> %m, i32 %evl)82 ret <4 x i8> %v83}84 85define <4 x i8> @vrsub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {86; CHECK-LABEL: vrsub_vi_v4i8_unmasked:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma89; CHECK-NEXT: vrsub.vi v8, v8, 290; CHECK-NEXT: ret91 %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> splat (i8 2), <4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)92 ret <4 x i8> %v93}94 95define <8 x i8> @vrsub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {96; CHECK-LABEL: vrsub_vx_v8i8:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma99; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t100; CHECK-NEXT: ret101 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0102 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer103 %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl)104 ret <8 x i8> %v105}106 107define <8 x i8> @vrsub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {108; CHECK-LABEL: vrsub_vx_v8i8_unmasked:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma111; CHECK-NEXT: vrsub.vx v8, v8, a0112; CHECK-NEXT: ret113 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0114 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer115 %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl)116 ret <8 x i8> %v117}118 119define <8 x i8> @vrsub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vrsub_vi_v8i8:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma123; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t124; CHECK-NEXT: ret125 %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> splat (i8 2), <8 x i8> %va, <8 x i1> %m, i32 %evl)126 ret <8 x i8> %v127}128 129define <8 x i8> @vrsub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {130; CHECK-LABEL: vrsub_vi_v8i8_unmasked:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma133; CHECK-NEXT: vrsub.vi v8, v8, 2134; CHECK-NEXT: ret135 %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> splat (i8 2), <8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl)136 ret <8 x i8> %v137}138 139define <16 x i8> @vrsub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vrsub_vx_v16i8:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma143; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t144; CHECK-NEXT: ret145 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0146 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer147 %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl)148 ret <16 x i8> %v149}150 151define <16 x i8> @vrsub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {152; CHECK-LABEL: vrsub_vx_v16i8_unmasked:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma155; CHECK-NEXT: vrsub.vx v8, v8, a0156; CHECK-NEXT: ret157 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0158 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer159 %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl)160 ret <16 x i8> %v161}162 163define <16 x i8> @vrsub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {164; CHECK-LABEL: vrsub_vi_v16i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma167; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t168; CHECK-NEXT: ret169 %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> splat (i8 2), <16 x i8> %va, <16 x i1> %m, i32 %evl)170 ret <16 x i8> %v171}172 173define <16 x i8> @vrsub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {174; CHECK-LABEL: vrsub_vi_v16i8_unmasked:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma177; CHECK-NEXT: vrsub.vi v8, v8, 2178; CHECK-NEXT: ret179 %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> splat (i8 2), <16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl)180 ret <16 x i8> %v181}182 183define <2 x i16> @vrsub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {184; CHECK-LABEL: vrsub_vx_v2i16:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma187; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t188; CHECK-NEXT: ret189 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0190 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer191 %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl)192 ret <2 x i16> %v193}194 195define <2 x i16> @vrsub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {196; CHECK-LABEL: vrsub_vx_v2i16_unmasked:197; CHECK: # %bb.0:198; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma199; CHECK-NEXT: vrsub.vx v8, v8, a0200; CHECK-NEXT: ret201 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0202 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer203 %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl)204 ret <2 x i16> %v205}206 207define <2 x i16> @vrsub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {208; CHECK-LABEL: vrsub_vi_v2i16:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma211; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t212; CHECK-NEXT: ret213 %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> splat (i16 2), <2 x i16> %va, <2 x i1> %m, i32 %evl)214 ret <2 x i16> %v215}216 217define <2 x i16> @vrsub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {218; CHECK-LABEL: vrsub_vi_v2i16_unmasked:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma221; CHECK-NEXT: vrsub.vi v8, v8, 2222; CHECK-NEXT: ret223 %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> splat (i16 2), <2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl)224 ret <2 x i16> %v225}226 227define <4 x i16> @vrsub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vrsub_vx_v4i16:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma231; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t232; CHECK-NEXT: ret233 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0234 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer235 %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl)236 ret <4 x i16> %v237}238 239define <4 x i16> @vrsub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {240; CHECK-LABEL: vrsub_vx_v4i16_unmasked:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma243; CHECK-NEXT: vrsub.vx v8, v8, a0244; CHECK-NEXT: ret245 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0246 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer247 %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)248 ret <4 x i16> %v249}250 251define <4 x i16> @vrsub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vrsub_vi_v4i16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma255; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t256; CHECK-NEXT: ret257 %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> splat (i16 2), <4 x i16> %va, <4 x i1> %m, i32 %evl)258 ret <4 x i16> %v259}260 261define <4 x i16> @vrsub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {262; CHECK-LABEL: vrsub_vi_v4i16_unmasked:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma265; CHECK-NEXT: vrsub.vi v8, v8, 2266; CHECK-NEXT: ret267 %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> splat (i16 2), <4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)268 ret <4 x i16> %v269}270 271define <8 x i16> @vrsub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vrsub_vx_v8i16:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma275; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t276; CHECK-NEXT: ret277 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0278 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer279 %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl)280 ret <8 x i16> %v281}282 283define <8 x i16> @vrsub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {284; CHECK-LABEL: vrsub_vx_v8i16_unmasked:285; CHECK: # %bb.0:286; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma287; CHECK-NEXT: vrsub.vx v8, v8, a0288; CHECK-NEXT: ret289 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0290 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer291 %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl)292 ret <8 x i16> %v293}294 295define <8 x i16> @vrsub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {296; CHECK-LABEL: vrsub_vi_v8i16:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma299; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t300; CHECK-NEXT: ret301 %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> splat (i16 2), <8 x i16> %va, <8 x i1> %m, i32 %evl)302 ret <8 x i16> %v303}304 305define <8 x i16> @vrsub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {306; CHECK-LABEL: vrsub_vi_v8i16_unmasked:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma309; CHECK-NEXT: vrsub.vi v8, v8, 2310; CHECK-NEXT: ret311 %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> splat (i16 2), <8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl)312 ret <8 x i16> %v313}314 315define <16 x i16> @vrsub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {316; CHECK-LABEL: vrsub_vx_v16i16:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma319; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t320; CHECK-NEXT: ret321 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0322 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer323 %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl)324 ret <16 x i16> %v325}326 327define <16 x i16> @vrsub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {328; CHECK-LABEL: vrsub_vx_v16i16_unmasked:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma331; CHECK-NEXT: vrsub.vx v8, v8, a0332; CHECK-NEXT: ret333 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0334 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer335 %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl)336 ret <16 x i16> %v337}338 339define <16 x i16> @vrsub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {340; CHECK-LABEL: vrsub_vi_v16i16:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma343; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t344; CHECK-NEXT: ret345 %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> splat (i16 2), <16 x i16> %va, <16 x i1> %m, i32 %evl)346 ret <16 x i16> %v347}348 349define <16 x i16> @vrsub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {350; CHECK-LABEL: vrsub_vi_v16i16_unmasked:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma353; CHECK-NEXT: vrsub.vi v8, v8, 2354; CHECK-NEXT: ret355 %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> splat (i16 2), <16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl)356 ret <16 x i16> %v357}358 359define <2 x i32> @vrsub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: vrsub_vx_v2i32:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma363; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t364; CHECK-NEXT: ret365 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0366 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer367 %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl)368 ret <2 x i32> %v369}370 371define <2 x i32> @vrsub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {372; CHECK-LABEL: vrsub_vx_v2i32_unmasked:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma375; CHECK-NEXT: vrsub.vx v8, v8, a0376; CHECK-NEXT: ret377 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0378 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer379 %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl)380 ret <2 x i32> %v381}382 383define <2 x i32> @vrsub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {384; CHECK-LABEL: vrsub_vi_v2i32:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma387; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t388; CHECK-NEXT: ret389 %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> splat (i32 2), <2 x i32> %va, <2 x i1> %m, i32 %evl)390 ret <2 x i32> %v391}392 393define <2 x i32> @vrsub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {394; CHECK-LABEL: vrsub_vi_v2i32_unmasked:395; CHECK: # %bb.0:396; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma397; CHECK-NEXT: vrsub.vi v8, v8, 2398; CHECK-NEXT: ret399 %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> splat (i32 2), <2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl)400 ret <2 x i32> %v401}402 403define <4 x i32> @vrsub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {404; CHECK-LABEL: vrsub_vx_v4i32:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma407; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t408; CHECK-NEXT: ret409 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0410 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer411 %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl)412 ret <4 x i32> %v413}414 415define <4 x i32> @vrsub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {416; CHECK-LABEL: vrsub_vx_v4i32_unmasked:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma419; CHECK-NEXT: vrsub.vx v8, v8, a0420; CHECK-NEXT: ret421 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0422 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer423 %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)424 ret <4 x i32> %v425}426 427define <4 x i32> @vrsub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {428; CHECK-LABEL: vrsub_vi_v4i32:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma431; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t432; CHECK-NEXT: ret433 %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> splat (i32 2), <4 x i32> %va, <4 x i1> %m, i32 %evl)434 ret <4 x i32> %v435}436 437define <4 x i32> @vrsub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {438; CHECK-LABEL: vrsub_vi_v4i32_unmasked:439; CHECK: # %bb.0:440; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma441; CHECK-NEXT: vrsub.vi v8, v8, 2442; CHECK-NEXT: ret443 %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> splat (i32 2), <4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)444 ret <4 x i32> %v445}446 447define <8 x i32> @vrsub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {448; CHECK-LABEL: vrsub_vx_v8i32:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma451; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t452; CHECK-NEXT: ret453 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0454 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer455 %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl)456 ret <8 x i32> %v457}458 459define <8 x i32> @vrsub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {460; CHECK-LABEL: vrsub_vx_v8i32_unmasked:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma463; CHECK-NEXT: vrsub.vx v8, v8, a0464; CHECK-NEXT: ret465 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0466 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer467 %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl)468 ret <8 x i32> %v469}470 471define <8 x i32> @vrsub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {472; CHECK-LABEL: vrsub_vi_v8i32:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma475; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t476; CHECK-NEXT: ret477 %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> splat (i32 2), <8 x i32> %va, <8 x i1> %m, i32 %evl)478 ret <8 x i32> %v479}480 481define <8 x i32> @vrsub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {482; CHECK-LABEL: vrsub_vi_v8i32_unmasked:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma485; CHECK-NEXT: vrsub.vi v8, v8, 2486; CHECK-NEXT: ret487 %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> splat (i32 2), <8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl)488 ret <8 x i32> %v489}490 491define <16 x i32> @vrsub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {492; CHECK-LABEL: vrsub_vx_v16i32:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma495; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t496; CHECK-NEXT: ret497 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0498 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer499 %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl)500 ret <16 x i32> %v501}502 503define <16 x i32> @vrsub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {504; CHECK-LABEL: vrsub_vx_v16i32_unmasked:505; CHECK: # %bb.0:506; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma507; CHECK-NEXT: vrsub.vx v8, v8, a0508; CHECK-NEXT: ret509 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0510 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer511 %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl)512 ret <16 x i32> %v513}514 515define <16 x i32> @vrsub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {516; CHECK-LABEL: vrsub_vi_v16i32:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma519; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t520; CHECK-NEXT: ret521 %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> splat (i32 2), <16 x i32> %va, <16 x i1> %m, i32 %evl)522 ret <16 x i32> %v523}524 525define <16 x i32> @vrsub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {526; CHECK-LABEL: vrsub_vi_v16i32_unmasked:527; CHECK: # %bb.0:528; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma529; CHECK-NEXT: vrsub.vi v8, v8, 2530; CHECK-NEXT: ret531 %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> splat (i32 2), <16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl)532 ret <16 x i32> %v533}534 535define <2 x i64> @vrsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {536; RV32-LABEL: vrsub_vx_v2i64:537; RV32: # %bb.0:538; RV32-NEXT: addi sp, sp, -16539; RV32-NEXT: .cfi_def_cfa_offset 16540; RV32-NEXT: sw a0, 8(sp)541; RV32-NEXT: sw a1, 12(sp)542; RV32-NEXT: addi a0, sp, 8543; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma544; RV32-NEXT: vlse64.v v9, (a0), zero545; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma546; RV32-NEXT: vsub.vv v8, v9, v8, v0.t547; RV32-NEXT: addi sp, sp, 16548; RV32-NEXT: .cfi_def_cfa_offset 0549; RV32-NEXT: ret550;551; RV64-LABEL: vrsub_vx_v2i64:552; RV64: # %bb.0:553; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma554; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t555; RV64-NEXT: ret556 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0557 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer558 %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl)559 ret <2 x i64> %v560}561 562define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {563; RV32-LABEL: vrsub_vx_v2i64_unmasked:564; RV32: # %bb.0:565; RV32-NEXT: addi sp, sp, -16566; RV32-NEXT: .cfi_def_cfa_offset 16567; RV32-NEXT: sw a0, 8(sp)568; RV32-NEXT: sw a1, 12(sp)569; RV32-NEXT: addi a0, sp, 8570; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma571; RV32-NEXT: vlse64.v v9, (a0), zero572; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma573; RV32-NEXT: vsub.vv v8, v9, v8574; RV32-NEXT: addi sp, sp, 16575; RV32-NEXT: .cfi_def_cfa_offset 0576; RV32-NEXT: ret577;578; RV64-LABEL: vrsub_vx_v2i64_unmasked:579; RV64: # %bb.0:580; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma581; RV64-NEXT: vrsub.vx v8, v8, a0582; RV64-NEXT: ret583 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0584 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer585 %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)586 ret <2 x i64> %v587}588 589define <2 x i64> @vrsub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {590; CHECK-LABEL: vrsub_vi_v2i64:591; CHECK: # %bb.0:592; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma593; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t594; CHECK-NEXT: ret595 %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> splat (i64 2), <2 x i64> %va, <2 x i1> %m, i32 %evl)596 ret <2 x i64> %v597}598 599define <2 x i64> @vrsub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {600; CHECK-LABEL: vrsub_vi_v2i64_unmasked:601; CHECK: # %bb.0:602; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma603; CHECK-NEXT: vrsub.vi v8, v8, 2604; CHECK-NEXT: ret605 %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> splat (i64 2), <2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl)606 ret <2 x i64> %v607}608 609define <4 x i64> @vrsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {610; RV32-LABEL: vrsub_vx_v4i64:611; RV32: # %bb.0:612; RV32-NEXT: addi sp, sp, -16613; RV32-NEXT: .cfi_def_cfa_offset 16614; RV32-NEXT: sw a0, 8(sp)615; RV32-NEXT: sw a1, 12(sp)616; RV32-NEXT: addi a0, sp, 8617; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma618; RV32-NEXT: vlse64.v v10, (a0), zero619; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma620; RV32-NEXT: vsub.vv v8, v10, v8, v0.t621; RV32-NEXT: addi sp, sp, 16622; RV32-NEXT: .cfi_def_cfa_offset 0623; RV32-NEXT: ret624;625; RV64-LABEL: vrsub_vx_v4i64:626; RV64: # %bb.0:627; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma628; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t629; RV64-NEXT: ret630 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0631 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer632 %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl)633 ret <4 x i64> %v634}635 636define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {637; RV32-LABEL: vrsub_vx_v4i64_unmasked:638; RV32: # %bb.0:639; RV32-NEXT: addi sp, sp, -16640; RV32-NEXT: .cfi_def_cfa_offset 16641; RV32-NEXT: sw a0, 8(sp)642; RV32-NEXT: sw a1, 12(sp)643; RV32-NEXT: addi a0, sp, 8644; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma645; RV32-NEXT: vlse64.v v10, (a0), zero646; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma647; RV32-NEXT: vsub.vv v8, v10, v8648; RV32-NEXT: addi sp, sp, 16649; RV32-NEXT: .cfi_def_cfa_offset 0650; RV32-NEXT: ret651;652; RV64-LABEL: vrsub_vx_v4i64_unmasked:653; RV64: # %bb.0:654; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma655; RV64-NEXT: vrsub.vx v8, v8, a0656; RV64-NEXT: ret657 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0658 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer659 %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)660 ret <4 x i64> %v661}662 663define <4 x i64> @vrsub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {664; CHECK-LABEL: vrsub_vi_v4i64:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma667; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t668; CHECK-NEXT: ret669 %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> splat (i64 2), <4 x i64> %va, <4 x i1> %m, i32 %evl)670 ret <4 x i64> %v671}672 673define <4 x i64> @vrsub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {674; CHECK-LABEL: vrsub_vi_v4i64_unmasked:675; CHECK: # %bb.0:676; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma677; CHECK-NEXT: vrsub.vi v8, v8, 2678; CHECK-NEXT: ret679 %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> splat (i64 2), <4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl)680 ret <4 x i64> %v681}682 683define <8 x i64> @vrsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {684; RV32-LABEL: vrsub_vx_v8i64:685; RV32: # %bb.0:686; RV32-NEXT: addi sp, sp, -16687; RV32-NEXT: .cfi_def_cfa_offset 16688; RV32-NEXT: sw a0, 8(sp)689; RV32-NEXT: sw a1, 12(sp)690; RV32-NEXT: addi a0, sp, 8691; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma692; RV32-NEXT: vlse64.v v12, (a0), zero693; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma694; RV32-NEXT: vsub.vv v8, v12, v8, v0.t695; RV32-NEXT: addi sp, sp, 16696; RV32-NEXT: .cfi_def_cfa_offset 0697; RV32-NEXT: ret698;699; RV64-LABEL: vrsub_vx_v8i64:700; RV64: # %bb.0:701; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma702; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t703; RV64-NEXT: ret704 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0705 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer706 %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl)707 ret <8 x i64> %v708}709 710define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {711; RV32-LABEL: vrsub_vx_v8i64_unmasked:712; RV32: # %bb.0:713; RV32-NEXT: addi sp, sp, -16714; RV32-NEXT: .cfi_def_cfa_offset 16715; RV32-NEXT: sw a0, 8(sp)716; RV32-NEXT: sw a1, 12(sp)717; RV32-NEXT: addi a0, sp, 8718; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma719; RV32-NEXT: vlse64.v v12, (a0), zero720; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma721; RV32-NEXT: vsub.vv v8, v12, v8722; RV32-NEXT: addi sp, sp, 16723; RV32-NEXT: .cfi_def_cfa_offset 0724; RV32-NEXT: ret725;726; RV64-LABEL: vrsub_vx_v8i64_unmasked:727; RV64: # %bb.0:728; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma729; RV64-NEXT: vrsub.vx v8, v8, a0730; RV64-NEXT: ret731 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0732 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer733 %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)734 ret <8 x i64> %v735}736 737define <8 x i64> @vrsub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {738; CHECK-LABEL: vrsub_vi_v8i64:739; CHECK: # %bb.0:740; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma741; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t742; CHECK-NEXT: ret743 %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> splat (i64 2), <8 x i64> %va, <8 x i1> %m, i32 %evl)744 ret <8 x i64> %v745}746 747define <8 x i64> @vrsub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {748; CHECK-LABEL: vrsub_vi_v8i64_unmasked:749; CHECK: # %bb.0:750; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma751; CHECK-NEXT: vrsub.vi v8, v8, 2752; CHECK-NEXT: ret753 %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> splat (i64 2), <8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl)754 ret <8 x i64> %v755}756 757define <16 x i64> @vrsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {758; RV32-LABEL: vrsub_vx_v16i64:759; RV32: # %bb.0:760; RV32-NEXT: addi sp, sp, -16761; RV32-NEXT: .cfi_def_cfa_offset 16762; RV32-NEXT: sw a0, 8(sp)763; RV32-NEXT: sw a1, 12(sp)764; RV32-NEXT: addi a0, sp, 8765; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma766; RV32-NEXT: vlse64.v v16, (a0), zero767; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma768; RV32-NEXT: vsub.vv v8, v16, v8, v0.t769; RV32-NEXT: addi sp, sp, 16770; RV32-NEXT: .cfi_def_cfa_offset 0771; RV32-NEXT: ret772;773; RV64-LABEL: vrsub_vx_v16i64:774; RV64: # %bb.0:775; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma776; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t777; RV64-NEXT: ret778 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0779 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer780 %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl)781 ret <16 x i64> %v782}783 784define <16 x i64> @vrsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {785; RV32-LABEL: vrsub_vx_v16i64_unmasked:786; RV32: # %bb.0:787; RV32-NEXT: addi sp, sp, -16788; RV32-NEXT: .cfi_def_cfa_offset 16789; RV32-NEXT: sw a0, 8(sp)790; RV32-NEXT: sw a1, 12(sp)791; RV32-NEXT: addi a0, sp, 8792; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma793; RV32-NEXT: vlse64.v v16, (a0), zero794; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma795; RV32-NEXT: vsub.vv v8, v16, v8796; RV32-NEXT: addi sp, sp, 16797; RV32-NEXT: .cfi_def_cfa_offset 0798; RV32-NEXT: ret799;800; RV64-LABEL: vrsub_vx_v16i64_unmasked:801; RV64: # %bb.0:802; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma803; RV64-NEXT: vrsub.vx v8, v8, a0804; RV64-NEXT: ret805 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0806 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer807 %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)808 ret <16 x i64> %v809}810 811define <16 x i64> @vrsub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {812; CHECK-LABEL: vrsub_vi_v16i64:813; CHECK: # %bb.0:814; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma815; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t816; CHECK-NEXT: ret817 %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> splat (i64 2), <16 x i64> %va, <16 x i1> %m, i32 %evl)818 ret <16 x i64> %v819}820 821define <16 x i64> @vrsub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {822; CHECK-LABEL: vrsub_vi_v16i64_unmasked:823; CHECK: # %bb.0:824; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma825; CHECK-NEXT: vrsub.vi v8, v8, 2826; CHECK-NEXT: ret827 %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> splat (i64 2), <16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl)828 ret <16 x i64> %v829}830