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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vsadd_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vsadd_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma11; CHECK-NEXT: vadd.vv v9, v9, v912; CHECK-NEXT: vadd.vv v8, v8, v813; CHECK-NEXT: li a1, 6314; CHECK-NEXT: vsra.vi v9, v9, 115; CHECK-NEXT: vsra.vi v8, v8, 116; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma17; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t18; CHECK-NEXT: vmin.vx v8, v8, a1, v0.t19; CHECK-NEXT: li a0, 19220; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t21; CHECK-NEXT: ret22 %v = call <8 x i7> @llvm.vp.sadd.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)23 ret <8 x i7> %v24}25 26define <2 x i8> @vsadd_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {27; CHECK-LABEL: vsadd_vv_v2i8:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma30; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t31; CHECK-NEXT: ret32 %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)33 ret <2 x i8> %v34}35 36define <2 x i8> @vsadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {37; CHECK-LABEL: vsadd_vv_v2i8_unmasked:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma40; CHECK-NEXT: vsadd.vv v8, v8, v941; CHECK-NEXT: ret42 %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)43 ret <2 x i8> %v44}45 46define <2 x i8> @vsadd_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {47; CHECK-LABEL: vsadd_vx_v2i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma50; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t51; CHECK-NEXT: ret52 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 053 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer54 %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)55 ret <2 x i8> %v56}57 58define <2 x i8> @vsadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {59; CHECK-LABEL: vsadd_vx_v2i8_unmasked:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma62; CHECK-NEXT: vsadd.vx v8, v8, a063; CHECK-NEXT: ret64 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 065 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer66 %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)67 ret <2 x i8> %v68}69 70define <2 x i8> @vsadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {71; CHECK-LABEL: vsadd_vi_v2i8:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma74; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t75; CHECK-NEXT: ret76 %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)77 ret <2 x i8> %v78}79 80define <2 x i8> @vsadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {81; CHECK-LABEL: vsadd_vi_v2i8_unmasked:82; CHECK: # %bb.0:83; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma84; CHECK-NEXT: vsadd.vi v8, v8, -185; CHECK-NEXT: ret86 %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)87 ret <2 x i8> %v88}89 90define <4 x i8> @vsadd_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {91; CHECK-LABEL: vsadd_vv_v4i8:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma94; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t95; CHECK-NEXT: ret96 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)97 ret <4 x i8> %v98}99 100define <4 x i8> @vsadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {101; CHECK-LABEL: vsadd_vv_v4i8_unmasked:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma104; CHECK-NEXT: vsadd.vv v8, v8, v9105; CHECK-NEXT: ret106 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)107 ret <4 x i8> %v108}109 110define <4 x i8> @vsadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {111; CHECK-LABEL: vsadd_vx_v4i8:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma114; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t115; CHECK-NEXT: ret116 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0117 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer118 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)119 ret <4 x i8> %v120}121 122define <4 x i8> @vsadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {123; CHECK-LABEL: vsadd_vx_v4i8_commute:124; CHECK: # %bb.0:125; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma126; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t127; CHECK-NEXT: ret128 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0129 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer130 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)131 ret <4 x i8> %v132}133 134define <4 x i8> @vsadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {135; CHECK-LABEL: vsadd_vx_v4i8_unmasked:136; CHECK: # %bb.0:137; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma138; CHECK-NEXT: vsadd.vx v8, v8, a0139; CHECK-NEXT: ret140 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0141 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer142 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)143 ret <4 x i8> %v144}145 146define <4 x i8> @vsadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {147; CHECK-LABEL: vsadd_vi_v4i8:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma150; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t151; CHECK-NEXT: ret152 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)153 ret <4 x i8> %v154}155 156define <4 x i8> @vsadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {157; CHECK-LABEL: vsadd_vi_v4i8_unmasked:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma160; CHECK-NEXT: vsadd.vi v8, v8, -1161; CHECK-NEXT: ret162 %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)163 ret <4 x i8> %v164}165 166define <5 x i8> @vsadd_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {167; CHECK-LABEL: vsadd_vv_v5i8:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma170; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t171; CHECK-NEXT: ret172 %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)173 ret <5 x i8> %v174}175 176define <5 x i8> @vsadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {177; CHECK-LABEL: vsadd_vv_v5i8_unmasked:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma180; CHECK-NEXT: vsadd.vv v8, v8, v9181; CHECK-NEXT: ret182 %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)183 ret <5 x i8> %v184}185 186define <5 x i8> @vsadd_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {187; CHECK-LABEL: vsadd_vx_v5i8:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma190; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t191; CHECK-NEXT: ret192 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0193 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer194 %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)195 ret <5 x i8> %v196}197 198define <5 x i8> @vsadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {199; CHECK-LABEL: vsadd_vx_v5i8_unmasked:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma202; CHECK-NEXT: vsadd.vx v8, v8, a0203; CHECK-NEXT: ret204 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0205 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer206 %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)207 ret <5 x i8> %v208}209 210define <5 x i8> @vsadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {211; CHECK-LABEL: vsadd_vi_v5i8:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma214; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t215; CHECK-NEXT: ret216 %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)217 ret <5 x i8> %v218}219 220define <5 x i8> @vsadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {221; CHECK-LABEL: vsadd_vi_v5i8_unmasked:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma224; CHECK-NEXT: vsadd.vi v8, v8, -1225; CHECK-NEXT: ret226 %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)227 ret <5 x i8> %v228}229 230define <8 x i8> @vsadd_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {231; CHECK-LABEL: vsadd_vv_v8i8:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma234; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t235; CHECK-NEXT: ret236 %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)237 ret <8 x i8> %v238}239 240define <8 x i8> @vsadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {241; CHECK-LABEL: vsadd_vv_v8i8_unmasked:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma244; CHECK-NEXT: vsadd.vv v8, v8, v9245; CHECK-NEXT: ret246 %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)247 ret <8 x i8> %v248}249 250define <8 x i8> @vsadd_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {251; CHECK-LABEL: vsadd_vx_v8i8:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma254; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t255; CHECK-NEXT: ret256 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0257 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer258 %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)259 ret <8 x i8> %v260}261 262define <8 x i8> @vsadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {263; CHECK-LABEL: vsadd_vx_v8i8_unmasked:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma266; CHECK-NEXT: vsadd.vx v8, v8, a0267; CHECK-NEXT: ret268 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0269 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer270 %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)271 ret <8 x i8> %v272}273 274define <8 x i8> @vsadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {275; CHECK-LABEL: vsadd_vi_v8i8:276; CHECK: # %bb.0:277; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma278; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t279; CHECK-NEXT: ret280 %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)281 ret <8 x i8> %v282}283 284define <8 x i8> @vsadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {285; CHECK-LABEL: vsadd_vi_v8i8_unmasked:286; CHECK: # %bb.0:287; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma288; CHECK-NEXT: vsadd.vi v8, v8, -1289; CHECK-NEXT: ret290 %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)291 ret <8 x i8> %v292}293 294define <16 x i8> @vsadd_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {295; CHECK-LABEL: vsadd_vv_v16i8:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma298; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t299; CHECK-NEXT: ret300 %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)301 ret <16 x i8> %v302}303 304define <16 x i8> @vsadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {305; CHECK-LABEL: vsadd_vv_v16i8_unmasked:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma308; CHECK-NEXT: vsadd.vv v8, v8, v9309; CHECK-NEXT: ret310 %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)311 ret <16 x i8> %v312}313 314define <16 x i8> @vsadd_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {315; CHECK-LABEL: vsadd_vx_v16i8:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma318; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t319; CHECK-NEXT: ret320 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0321 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer322 %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)323 ret <16 x i8> %v324}325 326define <16 x i8> @vsadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {327; CHECK-LABEL: vsadd_vx_v16i8_unmasked:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma330; CHECK-NEXT: vsadd.vx v8, v8, a0331; CHECK-NEXT: ret332 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0333 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer334 %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)335 ret <16 x i8> %v336}337 338define <16 x i8> @vsadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {339; CHECK-LABEL: vsadd_vi_v16i8:340; CHECK: # %bb.0:341; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma342; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t343; CHECK-NEXT: ret344 %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)345 ret <16 x i8> %v346}347 348define <16 x i8> @vsadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {349; CHECK-LABEL: vsadd_vi_v16i8_unmasked:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma352; CHECK-NEXT: vsadd.vi v8, v8, -1353; CHECK-NEXT: ret354 %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)355 ret <16 x i8> %v356}357 358define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {359; CHECK-LABEL: vsadd_vi_v258i8:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma362; CHECK-NEXT: vmv1r.v v24, v0363; CHECK-NEXT: li a2, 128364; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma365; CHECK-NEXT: vlm.v v0, (a0)366; CHECK-NEXT: addi a0, a1, -128367; CHECK-NEXT: sltu a3, a1, a0368; CHECK-NEXT: addi a3, a3, -1369; CHECK-NEXT: and a0, a3, a0370; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma371; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t372; CHECK-NEXT: bltu a1, a2, .LBB32_2373; CHECK-NEXT: # %bb.1:374; CHECK-NEXT: li a1, 128375; CHECK-NEXT: .LBB32_2:376; CHECK-NEXT: vmv1r.v v0, v24377; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma378; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t379; CHECK-NEXT: ret380 %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)381 ret <256 x i8> %v382}383 384define <256 x i8> @vsadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {385; CHECK-LABEL: vsadd_vi_v258i8_unmasked:386; CHECK: # %bb.0:387; CHECK-NEXT: li a2, 128388; CHECK-NEXT: mv a1, a0389; CHECK-NEXT: bltu a0, a2, .LBB33_2390; CHECK-NEXT: # %bb.1:391; CHECK-NEXT: li a1, 128392; CHECK-NEXT: .LBB33_2:393; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma394; CHECK-NEXT: vsadd.vi v8, v8, -1395; CHECK-NEXT: addi a1, a0, -128396; CHECK-NEXT: sltu a0, a0, a1397; CHECK-NEXT: addi a0, a0, -1398; CHECK-NEXT: and a0, a0, a1399; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma400; CHECK-NEXT: vsadd.vi v16, v16, -1401; CHECK-NEXT: ret402 %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)403 ret <256 x i8> %v404}405 406; Test splitting when the %evl is a known constant.407 408define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {409; CHECK-LABEL: vsadd_vi_v258i8_evl129:410; CHECK: # %bb.0:411; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma412; CHECK-NEXT: vlm.v v24, (a0)413; CHECK-NEXT: li a0, 128414; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma415; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t416; CHECK-NEXT: vmv1r.v v0, v24417; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma418; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t419; CHECK-NEXT: ret420 %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)421 ret <256 x i8> %v422}423 424define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {425; CHECK-LABEL: vsadd_vi_v258i8_evl128:426; CHECK: # %bb.0:427; CHECK-NEXT: li a0, 128428; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma429; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t430; CHECK-NEXT: ret431 %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)432 ret <256 x i8> %v433}434 435define <2 x i16> @vsadd_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {436; CHECK-LABEL: vsadd_vv_v2i16:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma439; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t440; CHECK-NEXT: ret441 %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)442 ret <2 x i16> %v443}444 445define <2 x i16> @vsadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {446; CHECK-LABEL: vsadd_vv_v2i16_unmasked:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma449; CHECK-NEXT: vsadd.vv v8, v8, v9450; CHECK-NEXT: ret451 %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)452 ret <2 x i16> %v453}454 455define <2 x i16> @vsadd_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {456; CHECK-LABEL: vsadd_vx_v2i16:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma459; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t460; CHECK-NEXT: ret461 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0462 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer463 %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)464 ret <2 x i16> %v465}466 467define <2 x i16> @vsadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {468; CHECK-LABEL: vsadd_vx_v2i16_unmasked:469; CHECK: # %bb.0:470; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma471; CHECK-NEXT: vsadd.vx v8, v8, a0472; CHECK-NEXT: ret473 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0474 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer475 %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)476 ret <2 x i16> %v477}478 479define <2 x i16> @vsadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: vsadd_vi_v2i16:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma483; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t484; CHECK-NEXT: ret485 %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)486 ret <2 x i16> %v487}488 489define <2 x i16> @vsadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {490; CHECK-LABEL: vsadd_vi_v2i16_unmasked:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma493; CHECK-NEXT: vsadd.vi v8, v8, -1494; CHECK-NEXT: ret495 %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)496 ret <2 x i16> %v497}498 499define <4 x i16> @vsadd_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {500; CHECK-LABEL: vsadd_vv_v4i16:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma503; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t504; CHECK-NEXT: ret505 %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)506 ret <4 x i16> %v507}508 509define <4 x i16> @vsadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {510; CHECK-LABEL: vsadd_vv_v4i16_unmasked:511; CHECK: # %bb.0:512; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma513; CHECK-NEXT: vsadd.vv v8, v8, v9514; CHECK-NEXT: ret515 %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)516 ret <4 x i16> %v517}518 519define <4 x i16> @vsadd_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {520; CHECK-LABEL: vsadd_vx_v4i16:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma523; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t524; CHECK-NEXT: ret525 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0526 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer527 %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)528 ret <4 x i16> %v529}530 531define <4 x i16> @vsadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {532; CHECK-LABEL: vsadd_vx_v4i16_unmasked:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma535; CHECK-NEXT: vsadd.vx v8, v8, a0536; CHECK-NEXT: ret537 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0538 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer539 %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)540 ret <4 x i16> %v541}542 543define <4 x i16> @vsadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {544; CHECK-LABEL: vsadd_vi_v4i16:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma547; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t548; CHECK-NEXT: ret549 %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)550 ret <4 x i16> %v551}552 553define <4 x i16> @vsadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {554; CHECK-LABEL: vsadd_vi_v4i16_unmasked:555; CHECK: # %bb.0:556; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma557; CHECK-NEXT: vsadd.vi v8, v8, -1558; CHECK-NEXT: ret559 %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)560 ret <4 x i16> %v561}562 563define <8 x i16> @vsadd_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {564; CHECK-LABEL: vsadd_vv_v8i16:565; CHECK: # %bb.0:566; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma567; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t568; CHECK-NEXT: ret569 %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)570 ret <8 x i16> %v571}572 573define <8 x i16> @vsadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {574; CHECK-LABEL: vsadd_vv_v8i16_unmasked:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma577; CHECK-NEXT: vsadd.vv v8, v8, v9578; CHECK-NEXT: ret579 %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)580 ret <8 x i16> %v581}582 583define <8 x i16> @vsadd_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {584; CHECK-LABEL: vsadd_vx_v8i16:585; CHECK: # %bb.0:586; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma587; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t588; CHECK-NEXT: ret589 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0590 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer591 %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)592 ret <8 x i16> %v593}594 595define <8 x i16> @vsadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {596; CHECK-LABEL: vsadd_vx_v8i16_unmasked:597; CHECK: # %bb.0:598; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma599; CHECK-NEXT: vsadd.vx v8, v8, a0600; CHECK-NEXT: ret601 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0602 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer603 %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)604 ret <8 x i16> %v605}606 607define <8 x i16> @vsadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {608; CHECK-LABEL: vsadd_vi_v8i16:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma611; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t612; CHECK-NEXT: ret613 %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)614 ret <8 x i16> %v615}616 617define <8 x i16> @vsadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {618; CHECK-LABEL: vsadd_vi_v8i16_unmasked:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma621; CHECK-NEXT: vsadd.vi v8, v8, -1622; CHECK-NEXT: ret623 %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)624 ret <8 x i16> %v625}626 627define <16 x i16> @vsadd_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {628; CHECK-LABEL: vsadd_vv_v16i16:629; CHECK: # %bb.0:630; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma631; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t632; CHECK-NEXT: ret633 %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)634 ret <16 x i16> %v635}636 637define <16 x i16> @vsadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {638; CHECK-LABEL: vsadd_vv_v16i16_unmasked:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma641; CHECK-NEXT: vsadd.vv v8, v8, v10642; CHECK-NEXT: ret643 %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)644 ret <16 x i16> %v645}646 647define <16 x i16> @vsadd_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {648; CHECK-LABEL: vsadd_vx_v16i16:649; CHECK: # %bb.0:650; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma651; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t652; CHECK-NEXT: ret653 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0654 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer655 %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)656 ret <16 x i16> %v657}658 659define <16 x i16> @vsadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {660; CHECK-LABEL: vsadd_vx_v16i16_unmasked:661; CHECK: # %bb.0:662; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma663; CHECK-NEXT: vsadd.vx v8, v8, a0664; CHECK-NEXT: ret665 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0666 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer667 %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)668 ret <16 x i16> %v669}670 671define <16 x i16> @vsadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {672; CHECK-LABEL: vsadd_vi_v16i16:673; CHECK: # %bb.0:674; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma675; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t676; CHECK-NEXT: ret677 %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)678 ret <16 x i16> %v679}680 681define <16 x i16> @vsadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {682; CHECK-LABEL: vsadd_vi_v16i16_unmasked:683; CHECK: # %bb.0:684; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma685; CHECK-NEXT: vsadd.vi v8, v8, -1686; CHECK-NEXT: ret687 %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)688 ret <16 x i16> %v689}690 691define <2 x i32> @vsadd_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {692; CHECK-LABEL: vsadd_vv_v2i32:693; CHECK: # %bb.0:694; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma695; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t696; CHECK-NEXT: ret697 %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)698 ret <2 x i32> %v699}700 701define <2 x i32> @vsadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {702; CHECK-LABEL: vsadd_vv_v2i32_unmasked:703; CHECK: # %bb.0:704; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma705; CHECK-NEXT: vsadd.vv v8, v8, v9706; CHECK-NEXT: ret707 %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)708 ret <2 x i32> %v709}710 711define <2 x i32> @vsadd_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {712; CHECK-LABEL: vsadd_vx_v2i32:713; CHECK: # %bb.0:714; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma715; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t716; CHECK-NEXT: ret717 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0718 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer719 %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)720 ret <2 x i32> %v721}722 723define <2 x i32> @vsadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {724; CHECK-LABEL: vsadd_vx_v2i32_unmasked:725; CHECK: # %bb.0:726; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma727; CHECK-NEXT: vsadd.vx v8, v8, a0728; CHECK-NEXT: ret729 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0730 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer731 %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)732 ret <2 x i32> %v733}734 735define <2 x i32> @vsadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vsadd_vi_v2i32:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma739; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t740; CHECK-NEXT: ret741 %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)742 ret <2 x i32> %v743}744 745define <2 x i32> @vsadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {746; CHECK-LABEL: vsadd_vi_v2i32_unmasked:747; CHECK: # %bb.0:748; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma749; CHECK-NEXT: vsadd.vi v8, v8, -1750; CHECK-NEXT: ret751 %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)752 ret <2 x i32> %v753}754 755define <4 x i32> @vsadd_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {756; CHECK-LABEL: vsadd_vv_v4i32:757; CHECK: # %bb.0:758; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma759; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t760; CHECK-NEXT: ret761 %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)762 ret <4 x i32> %v763}764 765define <4 x i32> @vsadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {766; CHECK-LABEL: vsadd_vv_v4i32_unmasked:767; CHECK: # %bb.0:768; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma769; CHECK-NEXT: vsadd.vv v8, v8, v9770; CHECK-NEXT: ret771 %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)772 ret <4 x i32> %v773}774 775define <4 x i32> @vsadd_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {776; CHECK-LABEL: vsadd_vx_v4i32:777; CHECK: # %bb.0:778; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma779; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t780; CHECK-NEXT: ret781 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0782 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer783 %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)784 ret <4 x i32> %v785}786 787define <4 x i32> @vsadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {788; CHECK-LABEL: vsadd_vx_v4i32_unmasked:789; CHECK: # %bb.0:790; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma791; CHECK-NEXT: vsadd.vx v8, v8, a0792; CHECK-NEXT: ret793 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0794 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer795 %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)796 ret <4 x i32> %v797}798 799define <4 x i32> @vsadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {800; CHECK-LABEL: vsadd_vi_v4i32:801; CHECK: # %bb.0:802; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma803; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t804; CHECK-NEXT: ret805 %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)806 ret <4 x i32> %v807}808 809define <4 x i32> @vsadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {810; CHECK-LABEL: vsadd_vi_v4i32_unmasked:811; CHECK: # %bb.0:812; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma813; CHECK-NEXT: vsadd.vi v8, v8, -1814; CHECK-NEXT: ret815 %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)816 ret <4 x i32> %v817}818 819define <8 x i32> @vsadd_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {820; CHECK-LABEL: vsadd_vv_v8i32:821; CHECK: # %bb.0:822; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma823; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t824; CHECK-NEXT: ret825 %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)826 ret <8 x i32> %v827}828 829define <8 x i32> @vsadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {830; CHECK-LABEL: vsadd_vv_v8i32_unmasked:831; CHECK: # %bb.0:832; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma833; CHECK-NEXT: vsadd.vv v8, v8, v10834; CHECK-NEXT: ret835 %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)836 ret <8 x i32> %v837}838 839define <8 x i32> @vsadd_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {840; CHECK-LABEL: vsadd_vx_v8i32:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma843; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t844; CHECK-NEXT: ret845 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0846 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer847 %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)848 ret <8 x i32> %v849}850 851define <8 x i32> @vsadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {852; CHECK-LABEL: vsadd_vx_v8i32_unmasked:853; CHECK: # %bb.0:854; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma855; CHECK-NEXT: vsadd.vx v8, v8, a0856; CHECK-NEXT: ret857 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0858 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer859 %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)860 ret <8 x i32> %v861}862 863define <8 x i32> @vsadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {864; CHECK-LABEL: vsadd_vi_v8i32:865; CHECK: # %bb.0:866; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma867; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t868; CHECK-NEXT: ret869 %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)870 ret <8 x i32> %v871}872 873define <8 x i32> @vsadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {874; CHECK-LABEL: vsadd_vi_v8i32_unmasked:875; CHECK: # %bb.0:876; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma877; CHECK-NEXT: vsadd.vi v8, v8, -1878; CHECK-NEXT: ret879 %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)880 ret <8 x i32> %v881}882 883define <16 x i32> @vsadd_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {884; CHECK-LABEL: vsadd_vv_v16i32:885; CHECK: # %bb.0:886; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma887; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t888; CHECK-NEXT: ret889 %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)890 ret <16 x i32> %v891}892 893define <16 x i32> @vsadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {894; CHECK-LABEL: vsadd_vv_v16i32_unmasked:895; CHECK: # %bb.0:896; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma897; CHECK-NEXT: vsadd.vv v8, v8, v12898; CHECK-NEXT: ret899 %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)900 ret <16 x i32> %v901}902 903define <16 x i32> @vsadd_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {904; CHECK-LABEL: vsadd_vx_v16i32:905; CHECK: # %bb.0:906; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma907; CHECK-NEXT: vsadd.vx v8, v8, a0, v0.t908; CHECK-NEXT: ret909 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0910 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer911 %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)912 ret <16 x i32> %v913}914 915define <16 x i32> @vsadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {916; CHECK-LABEL: vsadd_vx_v16i32_unmasked:917; CHECK: # %bb.0:918; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma919; CHECK-NEXT: vsadd.vx v8, v8, a0920; CHECK-NEXT: ret921 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0922 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer923 %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)924 ret <16 x i32> %v925}926 927define <16 x i32> @vsadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {928; CHECK-LABEL: vsadd_vi_v16i32:929; CHECK: # %bb.0:930; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma931; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t932; CHECK-NEXT: ret933 %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)934 ret <16 x i32> %v935}936 937define <16 x i32> @vsadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {938; CHECK-LABEL: vsadd_vi_v16i32_unmasked:939; CHECK: # %bb.0:940; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma941; CHECK-NEXT: vsadd.vi v8, v8, -1942; CHECK-NEXT: ret943 %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)944 ret <16 x i32> %v945}946 947define <2 x i64> @vsadd_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {948; CHECK-LABEL: vsadd_vv_v2i64:949; CHECK: # %bb.0:950; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma951; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t952; CHECK-NEXT: ret953 %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)954 ret <2 x i64> %v955}956 957define <2 x i64> @vsadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {958; CHECK-LABEL: vsadd_vv_v2i64_unmasked:959; CHECK: # %bb.0:960; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma961; CHECK-NEXT: vsadd.vv v8, v8, v9962; CHECK-NEXT: ret963 %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)964 ret <2 x i64> %v965}966 967define <2 x i64> @vsadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {968; RV32-LABEL: vsadd_vx_v2i64:969; RV32: # %bb.0:970; RV32-NEXT: addi sp, sp, -16971; RV32-NEXT: .cfi_def_cfa_offset 16972; RV32-NEXT: sw a0, 8(sp)973; RV32-NEXT: sw a1, 12(sp)974; RV32-NEXT: addi a0, sp, 8975; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma976; RV32-NEXT: vlse64.v v9, (a0), zero977; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma978; RV32-NEXT: vsadd.vv v8, v8, v9, v0.t979; RV32-NEXT: addi sp, sp, 16980; RV32-NEXT: .cfi_def_cfa_offset 0981; RV32-NEXT: ret982;983; RV64-LABEL: vsadd_vx_v2i64:984; RV64: # %bb.0:985; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma986; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t987; RV64-NEXT: ret988 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0989 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer990 %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)991 ret <2 x i64> %v992}993 994define <2 x i64> @vsadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {995; RV32-LABEL: vsadd_vx_v2i64_unmasked:996; RV32: # %bb.0:997; RV32-NEXT: addi sp, sp, -16998; RV32-NEXT: .cfi_def_cfa_offset 16999; RV32-NEXT: sw a0, 8(sp)1000; RV32-NEXT: sw a1, 12(sp)1001; RV32-NEXT: addi a0, sp, 81002; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1003; RV32-NEXT: vlse64.v v9, (a0), zero1004; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1005; RV32-NEXT: vsadd.vv v8, v8, v91006; RV32-NEXT: addi sp, sp, 161007; RV32-NEXT: .cfi_def_cfa_offset 01008; RV32-NEXT: ret1009;1010; RV64-LABEL: vsadd_vx_v2i64_unmasked:1011; RV64: # %bb.0:1012; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1013; RV64-NEXT: vsadd.vx v8, v8, a01014; RV64-NEXT: ret1015 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01016 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1017 %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)1018 ret <2 x i64> %v1019}1020 1021define <2 x i64> @vsadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {1022; CHECK-LABEL: vsadd_vi_v2i64:1023; CHECK: # %bb.0:1024; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1025; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1026; CHECK-NEXT: ret1027 %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)1028 ret <2 x i64> %v1029}1030 1031define <2 x i64> @vsadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {1032; CHECK-LABEL: vsadd_vi_v2i64_unmasked:1033; CHECK: # %bb.0:1034; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1035; CHECK-NEXT: vsadd.vi v8, v8, -11036; CHECK-NEXT: ret1037 %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)1038 ret <2 x i64> %v1039}1040 1041define <4 x i64> @vsadd_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {1042; CHECK-LABEL: vsadd_vv_v4i64:1043; CHECK: # %bb.0:1044; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1045; CHECK-NEXT: vsadd.vv v8, v8, v10, v0.t1046; CHECK-NEXT: ret1047 %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)1048 ret <4 x i64> %v1049}1050 1051define <4 x i64> @vsadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {1052; CHECK-LABEL: vsadd_vv_v4i64_unmasked:1053; CHECK: # %bb.0:1054; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1055; CHECK-NEXT: vsadd.vv v8, v8, v101056; CHECK-NEXT: ret1057 %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)1058 ret <4 x i64> %v1059}1060 1061define <4 x i64> @vsadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {1062; RV32-LABEL: vsadd_vx_v4i64:1063; RV32: # %bb.0:1064; RV32-NEXT: addi sp, sp, -161065; RV32-NEXT: .cfi_def_cfa_offset 161066; RV32-NEXT: sw a0, 8(sp)1067; RV32-NEXT: sw a1, 12(sp)1068; RV32-NEXT: addi a0, sp, 81069; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1070; RV32-NEXT: vlse64.v v10, (a0), zero1071; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1072; RV32-NEXT: vsadd.vv v8, v8, v10, v0.t1073; RV32-NEXT: addi sp, sp, 161074; RV32-NEXT: .cfi_def_cfa_offset 01075; RV32-NEXT: ret1076;1077; RV64-LABEL: vsadd_vx_v4i64:1078; RV64: # %bb.0:1079; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1080; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t1081; RV64-NEXT: ret1082 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01083 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1084 %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)1085 ret <4 x i64> %v1086}1087 1088define <4 x i64> @vsadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {1089; RV32-LABEL: vsadd_vx_v4i64_unmasked:1090; RV32: # %bb.0:1091; RV32-NEXT: addi sp, sp, -161092; RV32-NEXT: .cfi_def_cfa_offset 161093; RV32-NEXT: sw a0, 8(sp)1094; RV32-NEXT: sw a1, 12(sp)1095; RV32-NEXT: addi a0, sp, 81096; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1097; RV32-NEXT: vlse64.v v10, (a0), zero1098; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1099; RV32-NEXT: vsadd.vv v8, v8, v101100; RV32-NEXT: addi sp, sp, 161101; RV32-NEXT: .cfi_def_cfa_offset 01102; RV32-NEXT: ret1103;1104; RV64-LABEL: vsadd_vx_v4i64_unmasked:1105; RV64: # %bb.0:1106; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1107; RV64-NEXT: vsadd.vx v8, v8, a01108; RV64-NEXT: ret1109 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01110 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1111 %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)1112 ret <4 x i64> %v1113}1114 1115define <4 x i64> @vsadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1116; CHECK-LABEL: vsadd_vi_v4i64:1117; CHECK: # %bb.0:1118; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1119; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1120; CHECK-NEXT: ret1121 %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)1122 ret <4 x i64> %v1123}1124 1125define <4 x i64> @vsadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1126; CHECK-LABEL: vsadd_vi_v4i64_unmasked:1127; CHECK: # %bb.0:1128; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1129; CHECK-NEXT: vsadd.vi v8, v8, -11130; CHECK-NEXT: ret1131 %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)1132 ret <4 x i64> %v1133}1134 1135define <8 x i64> @vsadd_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {1136; CHECK-LABEL: vsadd_vv_v8i64:1137; CHECK: # %bb.0:1138; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1139; CHECK-NEXT: vsadd.vv v8, v8, v12, v0.t1140; CHECK-NEXT: ret1141 %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)1142 ret <8 x i64> %v1143}1144 1145define <8 x i64> @vsadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {1146; CHECK-LABEL: vsadd_vv_v8i64_unmasked:1147; CHECK: # %bb.0:1148; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1149; CHECK-NEXT: vsadd.vv v8, v8, v121150; CHECK-NEXT: ret1151 %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)1152 ret <8 x i64> %v1153}1154 1155define <8 x i64> @vsadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {1156; RV32-LABEL: vsadd_vx_v8i64:1157; RV32: # %bb.0:1158; RV32-NEXT: addi sp, sp, -161159; RV32-NEXT: .cfi_def_cfa_offset 161160; RV32-NEXT: sw a0, 8(sp)1161; RV32-NEXT: sw a1, 12(sp)1162; RV32-NEXT: addi a0, sp, 81163; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1164; RV32-NEXT: vlse64.v v12, (a0), zero1165; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1166; RV32-NEXT: vsadd.vv v8, v8, v12, v0.t1167; RV32-NEXT: addi sp, sp, 161168; RV32-NEXT: .cfi_def_cfa_offset 01169; RV32-NEXT: ret1170;1171; RV64-LABEL: vsadd_vx_v8i64:1172; RV64: # %bb.0:1173; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1174; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t1175; RV64-NEXT: ret1176 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01177 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1178 %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)1179 ret <8 x i64> %v1180}1181 1182define <8 x i64> @vsadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {1183; RV32-LABEL: vsadd_vx_v8i64_unmasked:1184; RV32: # %bb.0:1185; RV32-NEXT: addi sp, sp, -161186; RV32-NEXT: .cfi_def_cfa_offset 161187; RV32-NEXT: sw a0, 8(sp)1188; RV32-NEXT: sw a1, 12(sp)1189; RV32-NEXT: addi a0, sp, 81190; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1191; RV32-NEXT: vlse64.v v12, (a0), zero1192; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1193; RV32-NEXT: vsadd.vv v8, v8, v121194; RV32-NEXT: addi sp, sp, 161195; RV32-NEXT: .cfi_def_cfa_offset 01196; RV32-NEXT: ret1197;1198; RV64-LABEL: vsadd_vx_v8i64_unmasked:1199; RV64: # %bb.0:1200; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1201; RV64-NEXT: vsadd.vx v8, v8, a01202; RV64-NEXT: ret1203 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01204 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1205 %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)1206 ret <8 x i64> %v1207}1208 1209define <8 x i64> @vsadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1210; CHECK-LABEL: vsadd_vi_v8i64:1211; CHECK: # %bb.0:1212; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1213; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1214; CHECK-NEXT: ret1215 %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)1216 ret <8 x i64> %v1217}1218 1219define <8 x i64> @vsadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1220; CHECK-LABEL: vsadd_vi_v8i64_unmasked:1221; CHECK: # %bb.0:1222; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1223; CHECK-NEXT: vsadd.vi v8, v8, -11224; CHECK-NEXT: ret1225 %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)1226 ret <8 x i64> %v1227}1228 1229define <16 x i64> @vsadd_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {1230; CHECK-LABEL: vsadd_vv_v16i64:1231; CHECK: # %bb.0:1232; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1233; CHECK-NEXT: vsadd.vv v8, v8, v16, v0.t1234; CHECK-NEXT: ret1235 %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)1236 ret <16 x i64> %v1237}1238 1239define <16 x i64> @vsadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {1240; CHECK-LABEL: vsadd_vv_v16i64_unmasked:1241; CHECK: # %bb.0:1242; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1243; CHECK-NEXT: vsadd.vv v8, v8, v161244; CHECK-NEXT: ret1245 %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)1246 ret <16 x i64> %v1247}1248 1249define <16 x i64> @vsadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {1250; RV32-LABEL: vsadd_vx_v16i64:1251; RV32: # %bb.0:1252; RV32-NEXT: addi sp, sp, -161253; RV32-NEXT: .cfi_def_cfa_offset 161254; RV32-NEXT: sw a0, 8(sp)1255; RV32-NEXT: sw a1, 12(sp)1256; RV32-NEXT: addi a0, sp, 81257; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1258; RV32-NEXT: vlse64.v v16, (a0), zero1259; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1260; RV32-NEXT: vsadd.vv v8, v8, v16, v0.t1261; RV32-NEXT: addi sp, sp, 161262; RV32-NEXT: .cfi_def_cfa_offset 01263; RV32-NEXT: ret1264;1265; RV64-LABEL: vsadd_vx_v16i64:1266; RV64: # %bb.0:1267; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1268; RV64-NEXT: vsadd.vx v8, v8, a0, v0.t1269; RV64-NEXT: ret1270 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01271 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1272 %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)1273 ret <16 x i64> %v1274}1275 1276define <16 x i64> @vsadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {1277; RV32-LABEL: vsadd_vx_v16i64_unmasked:1278; RV32: # %bb.0:1279; RV32-NEXT: addi sp, sp, -161280; RV32-NEXT: .cfi_def_cfa_offset 161281; RV32-NEXT: sw a0, 8(sp)1282; RV32-NEXT: sw a1, 12(sp)1283; RV32-NEXT: addi a0, sp, 81284; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1285; RV32-NEXT: vlse64.v v16, (a0), zero1286; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1287; RV32-NEXT: vsadd.vv v8, v8, v161288; RV32-NEXT: addi sp, sp, 161289; RV32-NEXT: .cfi_def_cfa_offset 01290; RV32-NEXT: ret1291;1292; RV64-LABEL: vsadd_vx_v16i64_unmasked:1293; RV64: # %bb.0:1294; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1295; RV64-NEXT: vsadd.vx v8, v8, a01296; RV64-NEXT: ret1297 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01298 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1299 %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)1300 ret <16 x i64> %v1301}1302 1303define <16 x i64> @vsadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1304; CHECK-LABEL: vsadd_vi_v16i64:1305; CHECK: # %bb.0:1306; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1307; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1308; CHECK-NEXT: ret1309 %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)1310 ret <16 x i64> %v1311}1312 1313define <16 x i64> @vsadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1314; CHECK-LABEL: vsadd_vi_v16i64_unmasked:1315; CHECK: # %bb.0:1316; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1317; CHECK-NEXT: vsadd.vi v8, v8, -11318; CHECK-NEXT: ret1319 %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)1320 ret <16 x i64> %v1321}1322 1323; Test that split-legalization works as expected.1324 1325define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1326; CHECK-LABEL: vsadd_vx_v32i64:1327; CHECK: # %bb.0:1328; CHECK-NEXT: li a2, 161329; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1330; CHECK-NEXT: vslidedown.vi v24, v0, 21331; CHECK-NEXT: mv a1, a01332; CHECK-NEXT: bltu a0, a2, .LBB108_21333; CHECK-NEXT: # %bb.1:1334; CHECK-NEXT: li a1, 161335; CHECK-NEXT: .LBB108_2:1336; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1337; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1338; CHECK-NEXT: addi a1, a0, -161339; CHECK-NEXT: sltu a0, a0, a11340; CHECK-NEXT: addi a0, a0, -11341; CHECK-NEXT: and a0, a0, a11342; CHECK-NEXT: vmv1r.v v0, v241343; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1344; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t1345; CHECK-NEXT: ret1346 %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)1347 ret <32 x i64> %v1348}1349 1350define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1351; CHECK-LABEL: vsadd_vi_v32i64_unmasked:1352; CHECK: # %bb.0:1353; CHECK-NEXT: li a2, 161354; CHECK-NEXT: mv a1, a01355; CHECK-NEXT: bltu a0, a2, .LBB109_21356; CHECK-NEXT: # %bb.1:1357; CHECK-NEXT: li a1, 161358; CHECK-NEXT: .LBB109_2:1359; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1360; CHECK-NEXT: vsadd.vi v8, v8, -11361; CHECK-NEXT: addi a1, a0, -161362; CHECK-NEXT: sltu a0, a0, a11363; CHECK-NEXT: addi a0, a0, -11364; CHECK-NEXT: and a0, a0, a11365; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1366; CHECK-NEXT: vsadd.vi v16, v16, -11367; CHECK-NEXT: ret1368 %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)1369 ret <32 x i64> %v1370}1371 1372define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {1373; CHECK-LABEL: vsadd_vx_v32i64_evl12:1374; CHECK: # %bb.0:1375; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma1376; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1377; CHECK-NEXT: ret1378 %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)1379 ret <32 x i64> %v1380}1381 1382define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {1383; CHECK-LABEL: vsadd_vx_v32i64_evl27:1384; CHECK: # %bb.0:1385; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1386; CHECK-NEXT: vslidedown.vi v24, v0, 21387; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1388; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t1389; CHECK-NEXT: vmv1r.v v0, v241390; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma1391; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t1392; CHECK-NEXT: ret1393 %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)1394 ret <32 x i64> %v1395}1396