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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vsaddu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vsaddu_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: li a1, 12711; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma12; CHECK-NEXT: vand.vx v9, v9, a113; CHECK-NEXT: vand.vx v8, v8, a114; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma15; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t16; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t17; CHECK-NEXT: ret18 %v = call <8 x i7> @llvm.vp.uadd.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)19 ret <8 x i7> %v20}21 22define <2 x i8> @vsaddu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {23; CHECK-LABEL: vsaddu_vv_v2i8:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma26; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t27; CHECK-NEXT: ret28 %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)29 ret <2 x i8> %v30}31 32define <2 x i8> @vsaddu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {33; CHECK-LABEL: vsaddu_vv_v2i8_unmasked:34; CHECK: # %bb.0:35; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma36; CHECK-NEXT: vsaddu.vv v8, v8, v937; CHECK-NEXT: ret38 %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)39 ret <2 x i8> %v40}41 42define <2 x i8> @vsaddu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {43; CHECK-LABEL: vsaddu_vx_v2i8:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma46; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t47; CHECK-NEXT: ret48 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 049 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer50 %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)51 ret <2 x i8> %v52}53 54define <2 x i8> @vsaddu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {55; CHECK-LABEL: vsaddu_vx_v2i8_unmasked:56; CHECK: # %bb.0:57; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma58; CHECK-NEXT: vsaddu.vx v8, v8, a059; CHECK-NEXT: ret60 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 061 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer62 %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)63 ret <2 x i8> %v64}65 66define <2 x i8> @vsaddu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {67; CHECK-LABEL: vsaddu_vi_v2i8:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma70; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t71; CHECK-NEXT: ret72 %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)73 ret <2 x i8> %v74}75 76define <2 x i8> @vsaddu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {77; CHECK-LABEL: vsaddu_vi_v2i8_unmasked:78; CHECK: # %bb.0:79; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma80; CHECK-NEXT: vsaddu.vi v8, v8, -181; CHECK-NEXT: ret82 %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)83 ret <2 x i8> %v84}85 86define <4 x i8> @vsaddu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {87; CHECK-LABEL: vsaddu_vv_v4i8:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma90; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t91; CHECK-NEXT: ret92 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)93 ret <4 x i8> %v94}95 96define <4 x i8> @vsaddu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {97; CHECK-LABEL: vsaddu_vv_v4i8_unmasked:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma100; CHECK-NEXT: vsaddu.vv v8, v8, v9101; CHECK-NEXT: ret102 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)103 ret <4 x i8> %v104}105 106define <4 x i8> @vsaddu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {107; CHECK-LABEL: vsaddu_vx_v4i8:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma110; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t111; CHECK-NEXT: ret112 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0113 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer114 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)115 ret <4 x i8> %v116}117 118define <4 x i8> @vsaddu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {119; CHECK-LABEL: vsaddu_vx_v4i8_commute:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma122; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t123; CHECK-NEXT: ret124 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0125 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer126 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)127 ret <4 x i8> %v128}129 130define <4 x i8> @vsaddu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {131; CHECK-LABEL: vsaddu_vx_v4i8_unmasked:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma134; CHECK-NEXT: vsaddu.vx v8, v8, a0135; CHECK-NEXT: ret136 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0137 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer138 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)139 ret <4 x i8> %v140}141 142define <4 x i8> @vsaddu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {143; CHECK-LABEL: vsaddu_vi_v4i8:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma146; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t147; CHECK-NEXT: ret148 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)149 ret <4 x i8> %v150}151 152define <4 x i8> @vsaddu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {153; CHECK-LABEL: vsaddu_vi_v4i8_unmasked:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma156; CHECK-NEXT: vsaddu.vi v8, v8, -1157; CHECK-NEXT: ret158 %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)159 ret <4 x i8> %v160}161 162define <5 x i8> @vsaddu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {163; CHECK-LABEL: vsaddu_vv_v5i8:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma166; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t167; CHECK-NEXT: ret168 %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)169 ret <5 x i8> %v170}171 172define <5 x i8> @vsaddu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {173; CHECK-LABEL: vsaddu_vv_v5i8_unmasked:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma176; CHECK-NEXT: vsaddu.vv v8, v8, v9177; CHECK-NEXT: ret178 %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)179 ret <5 x i8> %v180}181 182define <5 x i8> @vsaddu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {183; CHECK-LABEL: vsaddu_vx_v5i8:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma186; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t187; CHECK-NEXT: ret188 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0189 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer190 %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)191 ret <5 x i8> %v192}193 194define <5 x i8> @vsaddu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {195; CHECK-LABEL: vsaddu_vx_v5i8_unmasked:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma198; CHECK-NEXT: vsaddu.vx v8, v8, a0199; CHECK-NEXT: ret200 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0201 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer202 %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)203 ret <5 x i8> %v204}205 206define <5 x i8> @vsaddu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {207; CHECK-LABEL: vsaddu_vi_v5i8:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma210; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t211; CHECK-NEXT: ret212 %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)213 ret <5 x i8> %v214}215 216define <5 x i8> @vsaddu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {217; CHECK-LABEL: vsaddu_vi_v5i8_unmasked:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma220; CHECK-NEXT: vsaddu.vi v8, v8, -1221; CHECK-NEXT: ret222 %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)223 ret <5 x i8> %v224}225 226define <8 x i8> @vsaddu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {227; CHECK-LABEL: vsaddu_vv_v8i8:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma230; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t231; CHECK-NEXT: ret232 %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)233 ret <8 x i8> %v234}235 236define <8 x i8> @vsaddu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {237; CHECK-LABEL: vsaddu_vv_v8i8_unmasked:238; CHECK: # %bb.0:239; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma240; CHECK-NEXT: vsaddu.vv v8, v8, v9241; CHECK-NEXT: ret242 %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)243 ret <8 x i8> %v244}245 246define <8 x i8> @vsaddu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {247; CHECK-LABEL: vsaddu_vx_v8i8:248; CHECK: # %bb.0:249; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma250; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t251; CHECK-NEXT: ret252 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0253 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer254 %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)255 ret <8 x i8> %v256}257 258define <8 x i8> @vsaddu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {259; CHECK-LABEL: vsaddu_vx_v8i8_unmasked:260; CHECK: # %bb.0:261; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma262; CHECK-NEXT: vsaddu.vx v8, v8, a0263; CHECK-NEXT: ret264 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0265 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer266 %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)267 ret <8 x i8> %v268}269 270define <8 x i8> @vsaddu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {271; CHECK-LABEL: vsaddu_vi_v8i8:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma274; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t275; CHECK-NEXT: ret276 %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)277 ret <8 x i8> %v278}279 280define <8 x i8> @vsaddu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {281; CHECK-LABEL: vsaddu_vi_v8i8_unmasked:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma284; CHECK-NEXT: vsaddu.vi v8, v8, -1285; CHECK-NEXT: ret286 %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)287 ret <8 x i8> %v288}289 290define <16 x i8> @vsaddu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {291; CHECK-LABEL: vsaddu_vv_v16i8:292; CHECK: # %bb.0:293; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma294; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t295; CHECK-NEXT: ret296 %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)297 ret <16 x i8> %v298}299 300define <16 x i8> @vsaddu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {301; CHECK-LABEL: vsaddu_vv_v16i8_unmasked:302; CHECK: # %bb.0:303; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma304; CHECK-NEXT: vsaddu.vv v8, v8, v9305; CHECK-NEXT: ret306 %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)307 ret <16 x i8> %v308}309 310define <16 x i8> @vsaddu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {311; CHECK-LABEL: vsaddu_vx_v16i8:312; CHECK: # %bb.0:313; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma314; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t315; CHECK-NEXT: ret316 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0317 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer318 %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)319 ret <16 x i8> %v320}321 322define <16 x i8> @vsaddu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {323; CHECK-LABEL: vsaddu_vx_v16i8_unmasked:324; CHECK: # %bb.0:325; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma326; CHECK-NEXT: vsaddu.vx v8, v8, a0327; CHECK-NEXT: ret328 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0329 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer330 %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)331 ret <16 x i8> %v332}333 334define <16 x i8> @vsaddu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {335; CHECK-LABEL: vsaddu_vi_v16i8:336; CHECK: # %bb.0:337; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma338; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t339; CHECK-NEXT: ret340 %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)341 ret <16 x i8> %v342}343 344define <16 x i8> @vsaddu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {345; CHECK-LABEL: vsaddu_vi_v16i8_unmasked:346; CHECK: # %bb.0:347; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma348; CHECK-NEXT: vsaddu.vi v8, v8, -1349; CHECK-NEXT: ret350 %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)351 ret <16 x i8> %v352}353 354define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {355; CHECK-LABEL: vsaddu_vi_v258i8:356; CHECK: # %bb.0:357; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma358; CHECK-NEXT: vmv1r.v v24, v0359; CHECK-NEXT: li a2, 128360; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma361; CHECK-NEXT: vlm.v v0, (a0)362; CHECK-NEXT: addi a0, a1, -128363; CHECK-NEXT: sltu a3, a1, a0364; CHECK-NEXT: addi a3, a3, -1365; CHECK-NEXT: and a0, a3, a0366; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma367; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t368; CHECK-NEXT: bltu a1, a2, .LBB32_2369; CHECK-NEXT: # %bb.1:370; CHECK-NEXT: li a1, 128371; CHECK-NEXT: .LBB32_2:372; CHECK-NEXT: vmv1r.v v0, v24373; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma374; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t375; CHECK-NEXT: ret376 %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)377 ret <256 x i8> %v378}379 380define <256 x i8> @vsaddu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {381; CHECK-LABEL: vsaddu_vi_v258i8_unmasked:382; CHECK: # %bb.0:383; CHECK-NEXT: li a2, 128384; CHECK-NEXT: mv a1, a0385; CHECK-NEXT: bltu a0, a2, .LBB33_2386; CHECK-NEXT: # %bb.1:387; CHECK-NEXT: li a1, 128388; CHECK-NEXT: .LBB33_2:389; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma390; CHECK-NEXT: vsaddu.vi v8, v8, -1391; CHECK-NEXT: addi a1, a0, -128392; CHECK-NEXT: sltu a0, a0, a1393; CHECK-NEXT: addi a0, a0, -1394; CHECK-NEXT: and a0, a0, a1395; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma396; CHECK-NEXT: vsaddu.vi v16, v16, -1397; CHECK-NEXT: ret398 %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)399 ret <256 x i8> %v400}401 402; Test splitting when the %evl is a known constant.403 404define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {405; CHECK-LABEL: vsaddu_vi_v258i8_evl129:406; CHECK: # %bb.0:407; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma408; CHECK-NEXT: vlm.v v24, (a0)409; CHECK-NEXT: li a0, 128410; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma411; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t412; CHECK-NEXT: vmv1r.v v0, v24413; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma414; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t415; CHECK-NEXT: ret416 %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)417 ret <256 x i8> %v418}419 420define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {421; CHECK-LABEL: vsaddu_vi_v258i8_evl128:422; CHECK: # %bb.0:423; CHECK-NEXT: li a0, 128424; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma425; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t426; CHECK-NEXT: ret427 %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)428 ret <256 x i8> %v429}430 431define <2 x i16> @vsaddu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {432; CHECK-LABEL: vsaddu_vv_v2i16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma435; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t436; CHECK-NEXT: ret437 %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)438 ret <2 x i16> %v439}440 441define <2 x i16> @vsaddu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {442; CHECK-LABEL: vsaddu_vv_v2i16_unmasked:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma445; CHECK-NEXT: vsaddu.vv v8, v8, v9446; CHECK-NEXT: ret447 %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)448 ret <2 x i16> %v449}450 451define <2 x i16> @vsaddu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {452; CHECK-LABEL: vsaddu_vx_v2i16:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma455; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t456; CHECK-NEXT: ret457 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0458 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer459 %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)460 ret <2 x i16> %v461}462 463define <2 x i16> @vsaddu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {464; CHECK-LABEL: vsaddu_vx_v2i16_unmasked:465; CHECK: # %bb.0:466; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma467; CHECK-NEXT: vsaddu.vx v8, v8, a0468; CHECK-NEXT: ret469 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0470 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer471 %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)472 ret <2 x i16> %v473}474 475define <2 x i16> @vsaddu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {476; CHECK-LABEL: vsaddu_vi_v2i16:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma479; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t480; CHECK-NEXT: ret481 %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)482 ret <2 x i16> %v483}484 485define <2 x i16> @vsaddu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {486; CHECK-LABEL: vsaddu_vi_v2i16_unmasked:487; CHECK: # %bb.0:488; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma489; CHECK-NEXT: vsaddu.vi v8, v8, -1490; CHECK-NEXT: ret491 %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)492 ret <2 x i16> %v493}494 495define <4 x i16> @vsaddu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {496; CHECK-LABEL: vsaddu_vv_v4i16:497; CHECK: # %bb.0:498; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma499; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t500; CHECK-NEXT: ret501 %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)502 ret <4 x i16> %v503}504 505define <4 x i16> @vsaddu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {506; CHECK-LABEL: vsaddu_vv_v4i16_unmasked:507; CHECK: # %bb.0:508; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma509; CHECK-NEXT: vsaddu.vv v8, v8, v9510; CHECK-NEXT: ret511 %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)512 ret <4 x i16> %v513}514 515define <4 x i16> @vsaddu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {516; CHECK-LABEL: vsaddu_vx_v4i16:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma519; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t520; CHECK-NEXT: ret521 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0522 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer523 %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)524 ret <4 x i16> %v525}526 527define <4 x i16> @vsaddu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {528; CHECK-LABEL: vsaddu_vx_v4i16_unmasked:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma531; CHECK-NEXT: vsaddu.vx v8, v8, a0532; CHECK-NEXT: ret533 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0534 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer535 %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)536 ret <4 x i16> %v537}538 539define <4 x i16> @vsaddu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {540; CHECK-LABEL: vsaddu_vi_v4i16:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma543; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t544; CHECK-NEXT: ret545 %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)546 ret <4 x i16> %v547}548 549define <4 x i16> @vsaddu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {550; CHECK-LABEL: vsaddu_vi_v4i16_unmasked:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma553; CHECK-NEXT: vsaddu.vi v8, v8, -1554; CHECK-NEXT: ret555 %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)556 ret <4 x i16> %v557}558 559define <8 x i16> @vsaddu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {560; CHECK-LABEL: vsaddu_vv_v8i16:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma563; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t564; CHECK-NEXT: ret565 %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)566 ret <8 x i16> %v567}568 569define <8 x i16> @vsaddu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {570; CHECK-LABEL: vsaddu_vv_v8i16_unmasked:571; CHECK: # %bb.0:572; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma573; CHECK-NEXT: vsaddu.vv v8, v8, v9574; CHECK-NEXT: ret575 %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)576 ret <8 x i16> %v577}578 579define <8 x i16> @vsaddu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {580; CHECK-LABEL: vsaddu_vx_v8i16:581; CHECK: # %bb.0:582; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma583; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t584; CHECK-NEXT: ret585 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0586 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer587 %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)588 ret <8 x i16> %v589}590 591define <8 x i16> @vsaddu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {592; CHECK-LABEL: vsaddu_vx_v8i16_unmasked:593; CHECK: # %bb.0:594; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma595; CHECK-NEXT: vsaddu.vx v8, v8, a0596; CHECK-NEXT: ret597 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0598 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer599 %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)600 ret <8 x i16> %v601}602 603define <8 x i16> @vsaddu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {604; CHECK-LABEL: vsaddu_vi_v8i16:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma607; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t608; CHECK-NEXT: ret609 %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)610 ret <8 x i16> %v611}612 613define <8 x i16> @vsaddu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {614; CHECK-LABEL: vsaddu_vi_v8i16_unmasked:615; CHECK: # %bb.0:616; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma617; CHECK-NEXT: vsaddu.vi v8, v8, -1618; CHECK-NEXT: ret619 %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)620 ret <8 x i16> %v621}622 623define <16 x i16> @vsaddu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {624; CHECK-LABEL: vsaddu_vv_v16i16:625; CHECK: # %bb.0:626; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma627; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t628; CHECK-NEXT: ret629 %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)630 ret <16 x i16> %v631}632 633define <16 x i16> @vsaddu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {634; CHECK-LABEL: vsaddu_vv_v16i16_unmasked:635; CHECK: # %bb.0:636; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma637; CHECK-NEXT: vsaddu.vv v8, v8, v10638; CHECK-NEXT: ret639 %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)640 ret <16 x i16> %v641}642 643define <16 x i16> @vsaddu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {644; CHECK-LABEL: vsaddu_vx_v16i16:645; CHECK: # %bb.0:646; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma647; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t648; CHECK-NEXT: ret649 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0650 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer651 %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)652 ret <16 x i16> %v653}654 655define <16 x i16> @vsaddu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {656; CHECK-LABEL: vsaddu_vx_v16i16_unmasked:657; CHECK: # %bb.0:658; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma659; CHECK-NEXT: vsaddu.vx v8, v8, a0660; CHECK-NEXT: ret661 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0662 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer663 %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)664 ret <16 x i16> %v665}666 667define <16 x i16> @vsaddu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {668; CHECK-LABEL: vsaddu_vi_v16i16:669; CHECK: # %bb.0:670; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma671; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t672; CHECK-NEXT: ret673 %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)674 ret <16 x i16> %v675}676 677define <16 x i16> @vsaddu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {678; CHECK-LABEL: vsaddu_vi_v16i16_unmasked:679; CHECK: # %bb.0:680; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma681; CHECK-NEXT: vsaddu.vi v8, v8, -1682; CHECK-NEXT: ret683 %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)684 ret <16 x i16> %v685}686 687define <2 x i32> @vsaddu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {688; CHECK-LABEL: vsaddu_vv_v2i32:689; CHECK: # %bb.0:690; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma691; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t692; CHECK-NEXT: ret693 %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)694 ret <2 x i32> %v695}696 697define <2 x i32> @vsaddu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {698; CHECK-LABEL: vsaddu_vv_v2i32_unmasked:699; CHECK: # %bb.0:700; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma701; CHECK-NEXT: vsaddu.vv v8, v8, v9702; CHECK-NEXT: ret703 %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)704 ret <2 x i32> %v705}706 707define <2 x i32> @vsaddu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {708; CHECK-LABEL: vsaddu_vx_v2i32:709; CHECK: # %bb.0:710; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma711; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t712; CHECK-NEXT: ret713 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0714 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer715 %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)716 ret <2 x i32> %v717}718 719define <2 x i32> @vsaddu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {720; CHECK-LABEL: vsaddu_vx_v2i32_unmasked:721; CHECK: # %bb.0:722; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma723; CHECK-NEXT: vsaddu.vx v8, v8, a0724; CHECK-NEXT: ret725 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0726 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer727 %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)728 ret <2 x i32> %v729}730 731define <2 x i32> @vsaddu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {732; CHECK-LABEL: vsaddu_vi_v2i32:733; CHECK: # %bb.0:734; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma735; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t736; CHECK-NEXT: ret737 %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)738 ret <2 x i32> %v739}740 741define <2 x i32> @vsaddu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {742; CHECK-LABEL: vsaddu_vi_v2i32_unmasked:743; CHECK: # %bb.0:744; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma745; CHECK-NEXT: vsaddu.vi v8, v8, -1746; CHECK-NEXT: ret747 %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)748 ret <2 x i32> %v749}750 751define <4 x i32> @vsaddu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {752; CHECK-LABEL: vsaddu_vv_v4i32:753; CHECK: # %bb.0:754; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma755; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t756; CHECK-NEXT: ret757 %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)758 ret <4 x i32> %v759}760 761define <4 x i32> @vsaddu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {762; CHECK-LABEL: vsaddu_vv_v4i32_unmasked:763; CHECK: # %bb.0:764; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma765; CHECK-NEXT: vsaddu.vv v8, v8, v9766; CHECK-NEXT: ret767 %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)768 ret <4 x i32> %v769}770 771define <4 x i32> @vsaddu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {772; CHECK-LABEL: vsaddu_vx_v4i32:773; CHECK: # %bb.0:774; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma775; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t776; CHECK-NEXT: ret777 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0778 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer779 %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)780 ret <4 x i32> %v781}782 783define <4 x i32> @vsaddu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {784; CHECK-LABEL: vsaddu_vx_v4i32_unmasked:785; CHECK: # %bb.0:786; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma787; CHECK-NEXT: vsaddu.vx v8, v8, a0788; CHECK-NEXT: ret789 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0790 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer791 %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)792 ret <4 x i32> %v793}794 795define <4 x i32> @vsaddu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {796; CHECK-LABEL: vsaddu_vi_v4i32:797; CHECK: # %bb.0:798; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma799; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t800; CHECK-NEXT: ret801 %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)802 ret <4 x i32> %v803}804 805define <4 x i32> @vsaddu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {806; CHECK-LABEL: vsaddu_vi_v4i32_unmasked:807; CHECK: # %bb.0:808; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma809; CHECK-NEXT: vsaddu.vi v8, v8, -1810; CHECK-NEXT: ret811 %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)812 ret <4 x i32> %v813}814 815define <8 x i32> @vsaddu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {816; CHECK-LABEL: vsaddu_vv_v8i32:817; CHECK: # %bb.0:818; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma819; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t820; CHECK-NEXT: ret821 %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)822 ret <8 x i32> %v823}824 825define <8 x i32> @vsaddu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {826; CHECK-LABEL: vsaddu_vv_v8i32_unmasked:827; CHECK: # %bb.0:828; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma829; CHECK-NEXT: vsaddu.vv v8, v8, v10830; CHECK-NEXT: ret831 %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)832 ret <8 x i32> %v833}834 835define <8 x i32> @vsaddu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {836; CHECK-LABEL: vsaddu_vx_v8i32:837; CHECK: # %bb.0:838; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma839; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t840; CHECK-NEXT: ret841 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0842 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer843 %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)844 ret <8 x i32> %v845}846 847define <8 x i32> @vsaddu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {848; CHECK-LABEL: vsaddu_vx_v8i32_unmasked:849; CHECK: # %bb.0:850; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma851; CHECK-NEXT: vsaddu.vx v8, v8, a0852; CHECK-NEXT: ret853 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0854 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer855 %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)856 ret <8 x i32> %v857}858 859define <8 x i32> @vsaddu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {860; CHECK-LABEL: vsaddu_vi_v8i32:861; CHECK: # %bb.0:862; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma863; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t864; CHECK-NEXT: ret865 %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)866 ret <8 x i32> %v867}868 869define <8 x i32> @vsaddu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {870; CHECK-LABEL: vsaddu_vi_v8i32_unmasked:871; CHECK: # %bb.0:872; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma873; CHECK-NEXT: vsaddu.vi v8, v8, -1874; CHECK-NEXT: ret875 %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)876 ret <8 x i32> %v877}878 879define <16 x i32> @vsaddu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {880; CHECK-LABEL: vsaddu_vv_v16i32:881; CHECK: # %bb.0:882; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma883; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t884; CHECK-NEXT: ret885 %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)886 ret <16 x i32> %v887}888 889define <16 x i32> @vsaddu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {890; CHECK-LABEL: vsaddu_vv_v16i32_unmasked:891; CHECK: # %bb.0:892; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma893; CHECK-NEXT: vsaddu.vv v8, v8, v12894; CHECK-NEXT: ret895 %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)896 ret <16 x i32> %v897}898 899define <16 x i32> @vsaddu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {900; CHECK-LABEL: vsaddu_vx_v16i32:901; CHECK: # %bb.0:902; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma903; CHECK-NEXT: vsaddu.vx v8, v8, a0, v0.t904; CHECK-NEXT: ret905 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0906 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer907 %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)908 ret <16 x i32> %v909}910 911define <16 x i32> @vsaddu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {912; CHECK-LABEL: vsaddu_vx_v16i32_unmasked:913; CHECK: # %bb.0:914; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma915; CHECK-NEXT: vsaddu.vx v8, v8, a0916; CHECK-NEXT: ret917 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0918 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer919 %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)920 ret <16 x i32> %v921}922 923define <16 x i32> @vsaddu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {924; CHECK-LABEL: vsaddu_vi_v16i32:925; CHECK: # %bb.0:926; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma927; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t928; CHECK-NEXT: ret929 %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)930 ret <16 x i32> %v931}932 933define <16 x i32> @vsaddu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {934; CHECK-LABEL: vsaddu_vi_v16i32_unmasked:935; CHECK: # %bb.0:936; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma937; CHECK-NEXT: vsaddu.vi v8, v8, -1938; CHECK-NEXT: ret939 %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)940 ret <16 x i32> %v941}942 943define <2 x i64> @vsaddu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {944; CHECK-LABEL: vsaddu_vv_v2i64:945; CHECK: # %bb.0:946; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma947; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t948; CHECK-NEXT: ret949 %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)950 ret <2 x i64> %v951}952 953define <2 x i64> @vsaddu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {954; CHECK-LABEL: vsaddu_vv_v2i64_unmasked:955; CHECK: # %bb.0:956; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma957; CHECK-NEXT: vsaddu.vv v8, v8, v9958; CHECK-NEXT: ret959 %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)960 ret <2 x i64> %v961}962 963define <2 x i64> @vsaddu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {964; RV32-LABEL: vsaddu_vx_v2i64:965; RV32: # %bb.0:966; RV32-NEXT: addi sp, sp, -16967; RV32-NEXT: .cfi_def_cfa_offset 16968; RV32-NEXT: sw a0, 8(sp)969; RV32-NEXT: sw a1, 12(sp)970; RV32-NEXT: addi a0, sp, 8971; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma972; RV32-NEXT: vlse64.v v9, (a0), zero973; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma974; RV32-NEXT: vsaddu.vv v8, v8, v9, v0.t975; RV32-NEXT: addi sp, sp, 16976; RV32-NEXT: .cfi_def_cfa_offset 0977; RV32-NEXT: ret978;979; RV64-LABEL: vsaddu_vx_v2i64:980; RV64: # %bb.0:981; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma982; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t983; RV64-NEXT: ret984 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0985 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer986 %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)987 ret <2 x i64> %v988}989 990define <2 x i64> @vsaddu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {991; RV32-LABEL: vsaddu_vx_v2i64_unmasked:992; RV32: # %bb.0:993; RV32-NEXT: addi sp, sp, -16994; RV32-NEXT: .cfi_def_cfa_offset 16995; RV32-NEXT: sw a0, 8(sp)996; RV32-NEXT: sw a1, 12(sp)997; RV32-NEXT: addi a0, sp, 8998; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma999; RV32-NEXT: vlse64.v v9, (a0), zero1000; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1001; RV32-NEXT: vsaddu.vv v8, v8, v91002; RV32-NEXT: addi sp, sp, 161003; RV32-NEXT: .cfi_def_cfa_offset 01004; RV32-NEXT: ret1005;1006; RV64-LABEL: vsaddu_vx_v2i64_unmasked:1007; RV64: # %bb.0:1008; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1009; RV64-NEXT: vsaddu.vx v8, v8, a01010; RV64-NEXT: ret1011 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01012 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1013 %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)1014 ret <2 x i64> %v1015}1016 1017define <2 x i64> @vsaddu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {1018; CHECK-LABEL: vsaddu_vi_v2i64:1019; CHECK: # %bb.0:1020; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1021; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1022; CHECK-NEXT: ret1023 %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)1024 ret <2 x i64> %v1025}1026 1027define <2 x i64> @vsaddu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {1028; CHECK-LABEL: vsaddu_vi_v2i64_unmasked:1029; CHECK: # %bb.0:1030; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1031; CHECK-NEXT: vsaddu.vi v8, v8, -11032; CHECK-NEXT: ret1033 %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)1034 ret <2 x i64> %v1035}1036 1037define <4 x i64> @vsaddu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {1038; CHECK-LABEL: vsaddu_vv_v4i64:1039; CHECK: # %bb.0:1040; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1041; CHECK-NEXT: vsaddu.vv v8, v8, v10, v0.t1042; CHECK-NEXT: ret1043 %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)1044 ret <4 x i64> %v1045}1046 1047define <4 x i64> @vsaddu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {1048; CHECK-LABEL: vsaddu_vv_v4i64_unmasked:1049; CHECK: # %bb.0:1050; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1051; CHECK-NEXT: vsaddu.vv v8, v8, v101052; CHECK-NEXT: ret1053 %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)1054 ret <4 x i64> %v1055}1056 1057define <4 x i64> @vsaddu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {1058; RV32-LABEL: vsaddu_vx_v4i64:1059; RV32: # %bb.0:1060; RV32-NEXT: addi sp, sp, -161061; RV32-NEXT: .cfi_def_cfa_offset 161062; RV32-NEXT: sw a0, 8(sp)1063; RV32-NEXT: sw a1, 12(sp)1064; RV32-NEXT: addi a0, sp, 81065; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1066; RV32-NEXT: vlse64.v v10, (a0), zero1067; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1068; RV32-NEXT: vsaddu.vv v8, v8, v10, v0.t1069; RV32-NEXT: addi sp, sp, 161070; RV32-NEXT: .cfi_def_cfa_offset 01071; RV32-NEXT: ret1072;1073; RV64-LABEL: vsaddu_vx_v4i64:1074; RV64: # %bb.0:1075; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1076; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t1077; RV64-NEXT: ret1078 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01079 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1080 %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)1081 ret <4 x i64> %v1082}1083 1084define <4 x i64> @vsaddu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {1085; RV32-LABEL: vsaddu_vx_v4i64_unmasked:1086; RV32: # %bb.0:1087; RV32-NEXT: addi sp, sp, -161088; RV32-NEXT: .cfi_def_cfa_offset 161089; RV32-NEXT: sw a0, 8(sp)1090; RV32-NEXT: sw a1, 12(sp)1091; RV32-NEXT: addi a0, sp, 81092; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1093; RV32-NEXT: vlse64.v v10, (a0), zero1094; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1095; RV32-NEXT: vsaddu.vv v8, v8, v101096; RV32-NEXT: addi sp, sp, 161097; RV32-NEXT: .cfi_def_cfa_offset 01098; RV32-NEXT: ret1099;1100; RV64-LABEL: vsaddu_vx_v4i64_unmasked:1101; RV64: # %bb.0:1102; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1103; RV64-NEXT: vsaddu.vx v8, v8, a01104; RV64-NEXT: ret1105 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01106 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1107 %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)1108 ret <4 x i64> %v1109}1110 1111define <4 x i64> @vsaddu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1112; CHECK-LABEL: vsaddu_vi_v4i64:1113; CHECK: # %bb.0:1114; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1115; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1116; CHECK-NEXT: ret1117 %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)1118 ret <4 x i64> %v1119}1120 1121define <4 x i64> @vsaddu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1122; CHECK-LABEL: vsaddu_vi_v4i64_unmasked:1123; CHECK: # %bb.0:1124; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1125; CHECK-NEXT: vsaddu.vi v8, v8, -11126; CHECK-NEXT: ret1127 %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)1128 ret <4 x i64> %v1129}1130 1131define <8 x i64> @vsaddu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {1132; CHECK-LABEL: vsaddu_vv_v8i64:1133; CHECK: # %bb.0:1134; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1135; CHECK-NEXT: vsaddu.vv v8, v8, v12, v0.t1136; CHECK-NEXT: ret1137 %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)1138 ret <8 x i64> %v1139}1140 1141define <8 x i64> @vsaddu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {1142; CHECK-LABEL: vsaddu_vv_v8i64_unmasked:1143; CHECK: # %bb.0:1144; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1145; CHECK-NEXT: vsaddu.vv v8, v8, v121146; CHECK-NEXT: ret1147 %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)1148 ret <8 x i64> %v1149}1150 1151define <8 x i64> @vsaddu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {1152; RV32-LABEL: vsaddu_vx_v8i64:1153; RV32: # %bb.0:1154; RV32-NEXT: addi sp, sp, -161155; RV32-NEXT: .cfi_def_cfa_offset 161156; RV32-NEXT: sw a0, 8(sp)1157; RV32-NEXT: sw a1, 12(sp)1158; RV32-NEXT: addi a0, sp, 81159; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1160; RV32-NEXT: vlse64.v v12, (a0), zero1161; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1162; RV32-NEXT: vsaddu.vv v8, v8, v12, v0.t1163; RV32-NEXT: addi sp, sp, 161164; RV32-NEXT: .cfi_def_cfa_offset 01165; RV32-NEXT: ret1166;1167; RV64-LABEL: vsaddu_vx_v8i64:1168; RV64: # %bb.0:1169; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1170; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t1171; RV64-NEXT: ret1172 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01173 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1174 %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)1175 ret <8 x i64> %v1176}1177 1178define <8 x i64> @vsaddu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {1179; RV32-LABEL: vsaddu_vx_v8i64_unmasked:1180; RV32: # %bb.0:1181; RV32-NEXT: addi sp, sp, -161182; RV32-NEXT: .cfi_def_cfa_offset 161183; RV32-NEXT: sw a0, 8(sp)1184; RV32-NEXT: sw a1, 12(sp)1185; RV32-NEXT: addi a0, sp, 81186; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1187; RV32-NEXT: vlse64.v v12, (a0), zero1188; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1189; RV32-NEXT: vsaddu.vv v8, v8, v121190; RV32-NEXT: addi sp, sp, 161191; RV32-NEXT: .cfi_def_cfa_offset 01192; RV32-NEXT: ret1193;1194; RV64-LABEL: vsaddu_vx_v8i64_unmasked:1195; RV64: # %bb.0:1196; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1197; RV64-NEXT: vsaddu.vx v8, v8, a01198; RV64-NEXT: ret1199 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01200 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1201 %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)1202 ret <8 x i64> %v1203}1204 1205define <8 x i64> @vsaddu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1206; CHECK-LABEL: vsaddu_vi_v8i64:1207; CHECK: # %bb.0:1208; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1209; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1210; CHECK-NEXT: ret1211 %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)1212 ret <8 x i64> %v1213}1214 1215define <8 x i64> @vsaddu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1216; CHECK-LABEL: vsaddu_vi_v8i64_unmasked:1217; CHECK: # %bb.0:1218; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1219; CHECK-NEXT: vsaddu.vi v8, v8, -11220; CHECK-NEXT: ret1221 %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)1222 ret <8 x i64> %v1223}1224 1225define <16 x i64> @vsaddu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {1226; CHECK-LABEL: vsaddu_vv_v16i64:1227; CHECK: # %bb.0:1228; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1229; CHECK-NEXT: vsaddu.vv v8, v8, v16, v0.t1230; CHECK-NEXT: ret1231 %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)1232 ret <16 x i64> %v1233}1234 1235define <16 x i64> @vsaddu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {1236; CHECK-LABEL: vsaddu_vv_v16i64_unmasked:1237; CHECK: # %bb.0:1238; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1239; CHECK-NEXT: vsaddu.vv v8, v8, v161240; CHECK-NEXT: ret1241 %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)1242 ret <16 x i64> %v1243}1244 1245define <16 x i64> @vsaddu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {1246; RV32-LABEL: vsaddu_vx_v16i64:1247; RV32: # %bb.0:1248; RV32-NEXT: addi sp, sp, -161249; RV32-NEXT: .cfi_def_cfa_offset 161250; RV32-NEXT: sw a0, 8(sp)1251; RV32-NEXT: sw a1, 12(sp)1252; RV32-NEXT: addi a0, sp, 81253; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1254; RV32-NEXT: vlse64.v v16, (a0), zero1255; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1256; RV32-NEXT: vsaddu.vv v8, v8, v16, v0.t1257; RV32-NEXT: addi sp, sp, 161258; RV32-NEXT: .cfi_def_cfa_offset 01259; RV32-NEXT: ret1260;1261; RV64-LABEL: vsaddu_vx_v16i64:1262; RV64: # %bb.0:1263; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1264; RV64-NEXT: vsaddu.vx v8, v8, a0, v0.t1265; RV64-NEXT: ret1266 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01267 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1268 %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)1269 ret <16 x i64> %v1270}1271 1272define <16 x i64> @vsaddu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {1273; RV32-LABEL: vsaddu_vx_v16i64_unmasked:1274; RV32: # %bb.0:1275; RV32-NEXT: addi sp, sp, -161276; RV32-NEXT: .cfi_def_cfa_offset 161277; RV32-NEXT: sw a0, 8(sp)1278; RV32-NEXT: sw a1, 12(sp)1279; RV32-NEXT: addi a0, sp, 81280; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1281; RV32-NEXT: vlse64.v v16, (a0), zero1282; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1283; RV32-NEXT: vsaddu.vv v8, v8, v161284; RV32-NEXT: addi sp, sp, 161285; RV32-NEXT: .cfi_def_cfa_offset 01286; RV32-NEXT: ret1287;1288; RV64-LABEL: vsaddu_vx_v16i64_unmasked:1289; RV64: # %bb.0:1290; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1291; RV64-NEXT: vsaddu.vx v8, v8, a01292; RV64-NEXT: ret1293 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01294 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1295 %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)1296 ret <16 x i64> %v1297}1298 1299define <16 x i64> @vsaddu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1300; CHECK-LABEL: vsaddu_vi_v16i64:1301; CHECK: # %bb.0:1302; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1303; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1304; CHECK-NEXT: ret1305 %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)1306 ret <16 x i64> %v1307}1308 1309define <16 x i64> @vsaddu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1310; CHECK-LABEL: vsaddu_vi_v16i64_unmasked:1311; CHECK: # %bb.0:1312; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1313; CHECK-NEXT: vsaddu.vi v8, v8, -11314; CHECK-NEXT: ret1315 %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)1316 ret <16 x i64> %v1317}1318 1319; Test that split-legalization works as expected.1320 1321define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1322; CHECK-LABEL: vsaddu_vx_v32i64:1323; CHECK: # %bb.0:1324; CHECK-NEXT: li a2, 161325; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1326; CHECK-NEXT: vslidedown.vi v24, v0, 21327; CHECK-NEXT: mv a1, a01328; CHECK-NEXT: bltu a0, a2, .LBB108_21329; CHECK-NEXT: # %bb.1:1330; CHECK-NEXT: li a1, 161331; CHECK-NEXT: .LBB108_2:1332; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1333; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1334; CHECK-NEXT: addi a1, a0, -161335; CHECK-NEXT: sltu a0, a0, a11336; CHECK-NEXT: addi a0, a0, -11337; CHECK-NEXT: and a0, a0, a11338; CHECK-NEXT: vmv1r.v v0, v241339; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1340; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t1341; CHECK-NEXT: ret1342 %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)1343 ret <32 x i64> %v1344}1345 1346define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1347; CHECK-LABEL: vsaddu_vi_v32i64_unmasked:1348; CHECK: # %bb.0:1349; CHECK-NEXT: li a2, 161350; CHECK-NEXT: mv a1, a01351; CHECK-NEXT: bltu a0, a2, .LBB109_21352; CHECK-NEXT: # %bb.1:1353; CHECK-NEXT: li a1, 161354; CHECK-NEXT: .LBB109_2:1355; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1356; CHECK-NEXT: vsaddu.vi v8, v8, -11357; CHECK-NEXT: addi a1, a0, -161358; CHECK-NEXT: sltu a0, a0, a11359; CHECK-NEXT: addi a0, a0, -11360; CHECK-NEXT: and a0, a0, a11361; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1362; CHECK-NEXT: vsaddu.vi v16, v16, -11363; CHECK-NEXT: ret1364 %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)1365 ret <32 x i64> %v1366}1367 1368define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {1369; CHECK-LABEL: vsaddu_vx_v32i64_evl12:1370; CHECK: # %bb.0:1371; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma1372; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1373; CHECK-NEXT: ret1374 %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)1375 ret <32 x i64> %v1376}1377 1378define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {1379; CHECK-LABEL: vsaddu_vx_v32i64_evl27:1380; CHECK: # %bb.0:1381; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1382; CHECK-NEXT: vslidedown.vi v24, v0, 21383; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1384; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t1385; CHECK-NEXT: vmv1r.v v0, v241386; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma1387; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t1388; CHECK-NEXT: ret1389 %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)1390 ret <32 x i64> %v1391}1392