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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <2 x i8> @uadd_v2i8_vv(<2 x i8> %va, <2 x i8> %b) {8; CHECK-LABEL: uadd_v2i8_vv:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma11; CHECK-NEXT: vsaddu.vv v8, v8, v912; CHECK-NEXT: ret13 %v = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b)14 ret <2 x i8> %v15}16 17define <2 x i8> @uadd_v2i8_vx(<2 x i8> %va, i8 %b) {18; CHECK-LABEL: uadd_v2i8_vx:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma21; CHECK-NEXT: vsaddu.vx v8, v8, a022; CHECK-NEXT: ret23 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 024 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer25 %v = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb)26 ret <2 x i8> %v27}28 29define <2 x i8> @uadd_v2i8_vi(<2 x i8> %va) {30; CHECK-LABEL: uadd_v2i8_vi:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma33; CHECK-NEXT: vsaddu.vi v8, v8, 834; CHECK-NEXT: ret35 %v = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 8))36 ret <2 x i8> %v37}38 39define <4 x i8> @uadd_v4i8_vv(<4 x i8> %va, <4 x i8> %b) {40; CHECK-LABEL: uadd_v4i8_vv:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma43; CHECK-NEXT: vsaddu.vv v8, v8, v944; CHECK-NEXT: ret45 %v = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b)46 ret <4 x i8> %v47}48 49define <4 x i8> @uadd_v4i8_vx(<4 x i8> %va, i8 %b) {50; CHECK-LABEL: uadd_v4i8_vx:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma53; CHECK-NEXT: vsaddu.vx v8, v8, a054; CHECK-NEXT: ret55 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 056 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer57 %v = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb)58 ret <4 x i8> %v59}60 61define <4 x i8> @uadd_v4i8_vi(<4 x i8> %va) {62; CHECK-LABEL: uadd_v4i8_vi:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma65; CHECK-NEXT: vsaddu.vi v8, v8, 866; CHECK-NEXT: ret67 %v = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 8))68 ret <4 x i8> %v69}70 71define <8 x i8> @uadd_v8i8_vv(<8 x i8> %va, <8 x i8> %b) {72; CHECK-LABEL: uadd_v8i8_vv:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma75; CHECK-NEXT: vsaddu.vv v8, v8, v976; CHECK-NEXT: ret77 %v = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b)78 ret <8 x i8> %v79}80 81define <8 x i8> @uadd_v8i8_vx(<8 x i8> %va, i8 %b) {82; CHECK-LABEL: uadd_v8i8_vx:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma85; CHECK-NEXT: vsaddu.vx v8, v8, a086; CHECK-NEXT: ret87 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 088 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer89 %v = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb)90 ret <8 x i8> %v91}92 93define <8 x i8> @uadd_v8i8_vi(<8 x i8> %va) {94; CHECK-LABEL: uadd_v8i8_vi:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma97; CHECK-NEXT: vsaddu.vi v8, v8, 898; CHECK-NEXT: ret99 %v = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 8))100 ret <8 x i8> %v101}102 103define <16 x i8> @uadd_v16i8_vv(<16 x i8> %va, <16 x i8> %b) {104; CHECK-LABEL: uadd_v16i8_vv:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma107; CHECK-NEXT: vsaddu.vv v8, v8, v9108; CHECK-NEXT: ret109 %v = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b)110 ret <16 x i8> %v111}112 113define <16 x i8> @uadd_v16i8_vx(<16 x i8> %va, i8 %b) {114; CHECK-LABEL: uadd_v16i8_vx:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma117; CHECK-NEXT: vsaddu.vx v8, v8, a0118; CHECK-NEXT: ret119 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0120 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer121 %v = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb)122 ret <16 x i8> %v123}124 125define <16 x i8> @uadd_v16i8_vi(<16 x i8> %va) {126; CHECK-LABEL: uadd_v16i8_vi:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma129; CHECK-NEXT: vsaddu.vi v8, v8, 8130; CHECK-NEXT: ret131 %v = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 8))132 ret <16 x i8> %v133}134 135define <2 x i16> @uadd_v2i16_vv(<2 x i16> %va, <2 x i16> %b) {136; CHECK-LABEL: uadd_v2i16_vv:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma139; CHECK-NEXT: vsaddu.vv v8, v8, v9140; CHECK-NEXT: ret141 %v = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b)142 ret <2 x i16> %v143}144 145define <2 x i16> @uadd_v2i16_vx(<2 x i16> %va, i16 %b) {146; CHECK-LABEL: uadd_v2i16_vx:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma149; CHECK-NEXT: vsaddu.vx v8, v8, a0150; CHECK-NEXT: ret151 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0152 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer153 %v = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb)154 ret <2 x i16> %v155}156 157define <2 x i16> @uadd_v2i16_vi(<2 x i16> %va) {158; CHECK-LABEL: uadd_v2i16_vi:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma161; CHECK-NEXT: vsaddu.vi v8, v8, 8162; CHECK-NEXT: ret163 %v = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 8))164 ret <2 x i16> %v165}166 167define <4 x i16> @uadd_v4i16_vv(<4 x i16> %va, <4 x i16> %b) {168; CHECK-LABEL: uadd_v4i16_vv:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma171; CHECK-NEXT: vsaddu.vv v8, v8, v9172; CHECK-NEXT: ret173 %v = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b)174 ret <4 x i16> %v175}176 177define <4 x i16> @uadd_v4i16_vx(<4 x i16> %va, i16 %b) {178; CHECK-LABEL: uadd_v4i16_vx:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma181; CHECK-NEXT: vsaddu.vx v8, v8, a0182; CHECK-NEXT: ret183 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0184 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer185 %v = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb)186 ret <4 x i16> %v187}188 189define <4 x i16> @uadd_v4i16_vi(<4 x i16> %va) {190; CHECK-LABEL: uadd_v4i16_vi:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma193; CHECK-NEXT: vsaddu.vi v8, v8, 8194; CHECK-NEXT: ret195 %v = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 8))196 ret <4 x i16> %v197}198 199define <8 x i16> @uadd_v8i16_vv(<8 x i16> %va, <8 x i16> %b) {200; CHECK-LABEL: uadd_v8i16_vv:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma203; CHECK-NEXT: vsaddu.vv v8, v8, v9204; CHECK-NEXT: ret205 %v = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b)206 ret <8 x i16> %v207}208 209define <8 x i16> @uadd_v8i16_vx(<8 x i16> %va, i16 %b) {210; CHECK-LABEL: uadd_v8i16_vx:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma213; CHECK-NEXT: vsaddu.vx v8, v8, a0214; CHECK-NEXT: ret215 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0216 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer217 %v = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb)218 ret <8 x i16> %v219}220 221define <8 x i16> @uadd_v8i16_vi(<8 x i16> %va) {222; CHECK-LABEL: uadd_v8i16_vi:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma225; CHECK-NEXT: vsaddu.vi v8, v8, 8226; CHECK-NEXT: ret227 %v = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 8))228 ret <8 x i16> %v229}230 231define <16 x i16> @uadd_v16i16_vv(<16 x i16> %va, <16 x i16> %b) {232; CHECK-LABEL: uadd_v16i16_vv:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma235; CHECK-NEXT: vsaddu.vv v8, v8, v10236; CHECK-NEXT: ret237 %v = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b)238 ret <16 x i16> %v239}240 241define <16 x i16> @uadd_v16i16_vx(<16 x i16> %va, i16 %b) {242; CHECK-LABEL: uadd_v16i16_vx:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma245; CHECK-NEXT: vsaddu.vx v8, v8, a0246; CHECK-NEXT: ret247 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0248 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer249 %v = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb)250 ret <16 x i16> %v251}252 253define <16 x i16> @uadd_v16i16_vi(<16 x i16> %va) {254; CHECK-LABEL: uadd_v16i16_vi:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma257; CHECK-NEXT: vsaddu.vi v8, v8, 8258; CHECK-NEXT: ret259 %v = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 8))260 ret <16 x i16> %v261}262 263define <2 x i32> @uadd_v2i32_vv(<2 x i32> %va, <2 x i32> %b) {264; CHECK-LABEL: uadd_v2i32_vv:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma267; CHECK-NEXT: vsaddu.vv v8, v8, v9268; CHECK-NEXT: ret269 %v = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b)270 ret <2 x i32> %v271}272 273define <2 x i32> @uadd_v2i32_vx(<2 x i32> %va, i32 %b) {274; CHECK-LABEL: uadd_v2i32_vx:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma277; CHECK-NEXT: vsaddu.vx v8, v8, a0278; CHECK-NEXT: ret279 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0280 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer281 %v = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb)282 ret <2 x i32> %v283}284 285define <2 x i32> @uadd_v2i32_vx_commute(<2 x i32> %va, i32 %b) {286; CHECK-LABEL: uadd_v2i32_vx_commute:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma289; CHECK-NEXT: vsaddu.vx v8, v8, a0290; CHECK-NEXT: ret291 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0292 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer293 %v = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %vb, <2 x i32> %va)294 ret <2 x i32> %v295}296 297define <2 x i32> @uadd_v2i32_vi(<2 x i32> %va) {298; CHECK-LABEL: uadd_v2i32_vi:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma301; CHECK-NEXT: vsaddu.vi v8, v8, 8302; CHECK-NEXT: ret303 %v = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 8))304 ret <2 x i32> %v305}306 307define <4 x i32> @uadd_v4i32_vv(<4 x i32> %va, <4 x i32> %b) {308; CHECK-LABEL: uadd_v4i32_vv:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma311; CHECK-NEXT: vsaddu.vv v8, v8, v9312; CHECK-NEXT: ret313 %v = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b)314 ret <4 x i32> %v315}316 317define <4 x i32> @uadd_v4i32_vx(<4 x i32> %va, i32 %b) {318; CHECK-LABEL: uadd_v4i32_vx:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma321; CHECK-NEXT: vsaddu.vx v8, v8, a0322; CHECK-NEXT: ret323 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0324 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer325 %v = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb)326 ret <4 x i32> %v327}328 329define <4 x i32> @uadd_v4i32_vi(<4 x i32> %va) {330; CHECK-LABEL: uadd_v4i32_vi:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma333; CHECK-NEXT: vsaddu.vi v8, v8, 8334; CHECK-NEXT: ret335 %v = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 8))336 ret <4 x i32> %v337}338 339define <8 x i32> @uadd_v8i32_vv(<8 x i32> %va, <8 x i32> %b) {340; CHECK-LABEL: uadd_v8i32_vv:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma343; CHECK-NEXT: vsaddu.vv v8, v8, v10344; CHECK-NEXT: ret345 %v = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b)346 ret <8 x i32> %v347}348 349define <8 x i32> @uadd_v8i32_vx(<8 x i32> %va, i32 %b) {350; CHECK-LABEL: uadd_v8i32_vx:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma353; CHECK-NEXT: vsaddu.vx v8, v8, a0354; CHECK-NEXT: ret355 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0356 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer357 %v = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb)358 ret <8 x i32> %v359}360 361define <8 x i32> @uadd_v8i32_vi(<8 x i32> %va) {362; CHECK-LABEL: uadd_v8i32_vi:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma365; CHECK-NEXT: vsaddu.vi v8, v8, 8366; CHECK-NEXT: ret367 %v = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 8))368 ret <8 x i32> %v369}370 371define <16 x i32> @uadd_v16i32_vv(<16 x i32> %va, <16 x i32> %b) {372; CHECK-LABEL: uadd_v16i32_vv:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma375; CHECK-NEXT: vsaddu.vv v8, v8, v12376; CHECK-NEXT: ret377 %v = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b)378 ret <16 x i32> %v379}380 381define <16 x i32> @uadd_v16i32_vx(<16 x i32> %va, i32 %b) {382; CHECK-LABEL: uadd_v16i32_vx:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma385; CHECK-NEXT: vsaddu.vx v8, v8, a0386; CHECK-NEXT: ret387 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0388 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer389 %v = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb)390 ret <16 x i32> %v391}392 393define <16 x i32> @uadd_v16i32_vi(<16 x i32> %va) {394; CHECK-LABEL: uadd_v16i32_vi:395; CHECK: # %bb.0:396; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma397; CHECK-NEXT: vsaddu.vi v8, v8, 8398; CHECK-NEXT: ret399 %v = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 8))400 ret <16 x i32> %v401}402 403define <2 x i64> @uadd_v2i64_vv(<2 x i64> %va, <2 x i64> %b) {404; CHECK-LABEL: uadd_v2i64_vv:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma407; CHECK-NEXT: vsaddu.vv v8, v8, v9408; CHECK-NEXT: ret409 %v = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b)410 ret <2 x i64> %v411}412 413define <2 x i64> @uadd_v2i64_vx(<2 x i64> %va, i64 %b) {414; RV32-LABEL: uadd_v2i64_vx:415; RV32: # %bb.0:416; RV32-NEXT: addi sp, sp, -16417; RV32-NEXT: .cfi_def_cfa_offset 16418; RV32-NEXT: sw a0, 8(sp)419; RV32-NEXT: sw a1, 12(sp)420; RV32-NEXT: addi a0, sp, 8421; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma422; RV32-NEXT: vlse64.v v9, (a0), zero423; RV32-NEXT: vsaddu.vv v8, v8, v9424; RV32-NEXT: addi sp, sp, 16425; RV32-NEXT: .cfi_def_cfa_offset 0426; RV32-NEXT: ret427;428; RV64-LABEL: uadd_v2i64_vx:429; RV64: # %bb.0:430; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma431; RV64-NEXT: vsaddu.vx v8, v8, a0432; RV64-NEXT: ret433 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0434 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer435 %v = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb)436 ret <2 x i64> %v437}438 439define <2 x i64> @uadd_v2i64_vi(<2 x i64> %va) {440; CHECK-LABEL: uadd_v2i64_vi:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma443; CHECK-NEXT: vsaddu.vi v8, v8, 8444; CHECK-NEXT: ret445 %v = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 8))446 ret <2 x i64> %v447}448 449define <4 x i64> @uadd_v4i64_vv(<4 x i64> %va, <4 x i64> %b) {450; CHECK-LABEL: uadd_v4i64_vv:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma453; CHECK-NEXT: vsaddu.vv v8, v8, v10454; CHECK-NEXT: ret455 %v = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b)456 ret <4 x i64> %v457}458 459define <4 x i64> @uadd_v4i64_vx(<4 x i64> %va, i64 %b) {460; RV32-LABEL: uadd_v4i64_vx:461; RV32: # %bb.0:462; RV32-NEXT: addi sp, sp, -16463; RV32-NEXT: .cfi_def_cfa_offset 16464; RV32-NEXT: sw a0, 8(sp)465; RV32-NEXT: sw a1, 12(sp)466; RV32-NEXT: addi a0, sp, 8467; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma468; RV32-NEXT: vlse64.v v10, (a0), zero469; RV32-NEXT: vsaddu.vv v8, v8, v10470; RV32-NEXT: addi sp, sp, 16471; RV32-NEXT: .cfi_def_cfa_offset 0472; RV32-NEXT: ret473;474; RV64-LABEL: uadd_v4i64_vx:475; RV64: # %bb.0:476; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma477; RV64-NEXT: vsaddu.vx v8, v8, a0478; RV64-NEXT: ret479 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0480 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer481 %v = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb)482 ret <4 x i64> %v483}484 485define <4 x i64> @uadd_v4i64_vi(<4 x i64> %va) {486; CHECK-LABEL: uadd_v4i64_vi:487; CHECK: # %bb.0:488; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma489; CHECK-NEXT: vsaddu.vi v8, v8, 8490; CHECK-NEXT: ret491 %v = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 8))492 ret <4 x i64> %v493}494 495define <8 x i64> @uadd_v8i64_vv(<8 x i64> %va, <8 x i64> %b) {496; CHECK-LABEL: uadd_v8i64_vv:497; CHECK: # %bb.0:498; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma499; CHECK-NEXT: vsaddu.vv v8, v8, v12500; CHECK-NEXT: ret501 %v = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b)502 ret <8 x i64> %v503}504 505define <8 x i64> @uadd_v8i64_vx(<8 x i64> %va, i64 %b) {506; RV32-LABEL: uadd_v8i64_vx:507; RV32: # %bb.0:508; RV32-NEXT: addi sp, sp, -16509; RV32-NEXT: .cfi_def_cfa_offset 16510; RV32-NEXT: sw a0, 8(sp)511; RV32-NEXT: sw a1, 12(sp)512; RV32-NEXT: addi a0, sp, 8513; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma514; RV32-NEXT: vlse64.v v12, (a0), zero515; RV32-NEXT: vsaddu.vv v8, v8, v12516; RV32-NEXT: addi sp, sp, 16517; RV32-NEXT: .cfi_def_cfa_offset 0518; RV32-NEXT: ret519;520; RV64-LABEL: uadd_v8i64_vx:521; RV64: # %bb.0:522; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma523; RV64-NEXT: vsaddu.vx v8, v8, a0524; RV64-NEXT: ret525 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0526 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer527 %v = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb)528 ret <8 x i64> %v529}530 531define <8 x i64> @uadd_v8i64_vi(<8 x i64> %va) {532; CHECK-LABEL: uadd_v8i64_vi:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma535; CHECK-NEXT: vsaddu.vi v8, v8, 8536; CHECK-NEXT: ret537 %v = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 8))538 ret <8 x i64> %v539}540 541define <16 x i64> @uadd_v16i64_vv(<16 x i64> %va, <16 x i64> %b) {542; CHECK-LABEL: uadd_v16i64_vv:543; CHECK: # %bb.0:544; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma545; CHECK-NEXT: vsaddu.vv v8, v8, v16546; CHECK-NEXT: ret547 %v = call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b)548 ret <16 x i64> %v549}550 551define <16 x i64> @uadd_v16i64_vx(<16 x i64> %va, i64 %b) {552; RV32-LABEL: uadd_v16i64_vx:553; RV32: # %bb.0:554; RV32-NEXT: addi sp, sp, -16555; RV32-NEXT: .cfi_def_cfa_offset 16556; RV32-NEXT: sw a0, 8(sp)557; RV32-NEXT: sw a1, 12(sp)558; RV32-NEXT: addi a0, sp, 8559; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma560; RV32-NEXT: vlse64.v v16, (a0), zero561; RV32-NEXT: vsaddu.vv v8, v8, v16562; RV32-NEXT: addi sp, sp, 16563; RV32-NEXT: .cfi_def_cfa_offset 0564; RV32-NEXT: ret565;566; RV64-LABEL: uadd_v16i64_vx:567; RV64: # %bb.0:568; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma569; RV64-NEXT: vsaddu.vx v8, v8, a0570; RV64-NEXT: ret571 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0572 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer573 %v = call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb)574 ret <16 x i64> %v575}576 577define <16 x i64> @uadd_v16i64_vi(<16 x i64> %va) {578; CHECK-LABEL: uadd_v16i64_vi:579; CHECK: # %bb.0:580; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma581; CHECK-NEXT: vsaddu.vi v8, v8, 8582; CHECK-NEXT: ret583 %v = call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 8))584 ret <16 x i64> %v585}586