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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s4 5define <512 x i8> @vadd_v512i8_zvl128(<512 x i8> %a, <512 x i8> %b) #0 {6; CHECK-LABEL: vadd_v512i8_zvl128:7; CHECK: # %bb.0:8; CHECK-NEXT: addi sp, sp, -169; CHECK-NEXT: .cfi_def_cfa_offset 1610; CHECK-NEXT: csrr a2, vlenb11; CHECK-NEXT: li a4, 4812; CHECK-NEXT: mul a2, a2, a413; CHECK-NEXT: sub sp, sp, a214; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb15; CHECK-NEXT: csrr a2, vlenb16; CHECK-NEXT: slli a2, a2, 517; CHECK-NEXT: add a2, sp, a218; CHECK-NEXT: addi a2, a2, 1619; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill20; CHECK-NEXT: csrr a2, vlenb21; CHECK-NEXT: li a4, 4022; CHECK-NEXT: mul a2, a2, a423; CHECK-NEXT: add a2, sp, a224; CHECK-NEXT: addi a2, a2, 1625; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill26; CHECK-NEXT: li a2, 12827; CHECK-NEXT: addi a4, a3, 12828; CHECK-NEXT: addi a5, a3, 38429; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma30; CHECK-NEXT: vle8.v v8, (a5)31; CHECK-NEXT: csrr a2, vlenb32; CHECK-NEXT: li a5, 2433; CHECK-NEXT: mul a2, a2, a534; CHECK-NEXT: add a2, sp, a235; CHECK-NEXT: addi a2, a2, 1636; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill37; CHECK-NEXT: addi a2, a1, 12838; CHECK-NEXT: vle8.v v8, (a1)39; CHECK-NEXT: csrr a1, vlenb40; CHECK-NEXT: slli a1, a1, 441; CHECK-NEXT: add a1, sp, a142; CHECK-NEXT: addi a1, a1, 1643; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill44; CHECK-NEXT: addi a1, a3, 25645; CHECK-NEXT: vle8.v v8, (a1)46; CHECK-NEXT: csrr a1, vlenb47; CHECK-NEXT: slli a1, a1, 348; CHECK-NEXT: add a1, sp, a149; CHECK-NEXT: addi a1, a1, 1650; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill51; CHECK-NEXT: vle8.v v8, (a2)52; CHECK-NEXT: addi a1, sp, 1653; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill54; CHECK-NEXT: vle8.v v24, (a4)55; CHECK-NEXT: vle8.v v0, (a3)56; CHECK-NEXT: csrr a1, vlenb57; CHECK-NEXT: slli a1, a1, 458; CHECK-NEXT: add a1, sp, a159; CHECK-NEXT: addi a1, a1, 1660; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload61; CHECK-NEXT: csrr a1, vlenb62; CHECK-NEXT: slli a1, a1, 363; CHECK-NEXT: add a1, sp, a164; CHECK-NEXT: addi a1, a1, 1665; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload66; CHECK-NEXT: vadd.vv v8, v8, v1667; CHECK-NEXT: csrr a1, vlenb68; CHECK-NEXT: slli a1, a1, 469; CHECK-NEXT: add a1, sp, a170; CHECK-NEXT: addi a1, a1, 1671; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill72; CHECK-NEXT: csrr a1, vlenb73; CHECK-NEXT: li a2, 2474; CHECK-NEXT: mul a1, a1, a275; CHECK-NEXT: add a1, sp, a176; CHECK-NEXT: addi a1, a1, 1677; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload78; CHECK-NEXT: addi a1, sp, 1679; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload80; CHECK-NEXT: vadd.vv v16, v16, v881; CHECK-NEXT: csrr a1, vlenb82; CHECK-NEXT: slli a1, a1, 583; CHECK-NEXT: add a1, sp, a184; CHECK-NEXT: addi a1, a1, 1685; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload86; CHECK-NEXT: vadd.vv v24, v8, v2487; CHECK-NEXT: csrr a1, vlenb88; CHECK-NEXT: li a2, 4089; CHECK-NEXT: mul a1, a1, a290; CHECK-NEXT: add a1, sp, a191; CHECK-NEXT: addi a1, a1, 1692; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload93; CHECK-NEXT: vadd.vv v0, v8, v094; CHECK-NEXT: vse8.v v0, (a0)95; CHECK-NEXT: addi a1, a0, 38496; CHECK-NEXT: vse8.v v16, (a1)97; CHECK-NEXT: addi a1, a0, 25698; CHECK-NEXT: csrr a2, vlenb99; CHECK-NEXT: slli a2, a2, 4100; CHECK-NEXT: add a2, sp, a2101; CHECK-NEXT: addi a2, a2, 16102; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload103; CHECK-NEXT: vse8.v v8, (a1)104; CHECK-NEXT: addi a0, a0, 128105; CHECK-NEXT: vse8.v v24, (a0)106; CHECK-NEXT: csrr a0, vlenb107; CHECK-NEXT: li a1, 48108; CHECK-NEXT: mul a0, a0, a1109; CHECK-NEXT: add sp, sp, a0110; CHECK-NEXT: .cfi_def_cfa sp, 16111; CHECK-NEXT: addi sp, sp, 16112; CHECK-NEXT: .cfi_def_cfa_offset 0113; CHECK-NEXT: ret114 %c = add <512 x i8> %a, %b115 ret <512 x i8> %c116}117 118define <512 x i8> @vadd_v512i8_zvl256(<512 x i8> %a, <512 x i8> %b) #1 {119; CHECK-LABEL: vadd_v512i8_zvl256:120; CHECK: # %bb.0:121; CHECK-NEXT: addi a1, a0, 256122; CHECK-NEXT: li a2, 256123; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma124; CHECK-NEXT: vle8.v v24, (a0)125; CHECK-NEXT: vle8.v v0, (a1)126; CHECK-NEXT: vadd.vv v8, v8, v24127; CHECK-NEXT: vadd.vv v16, v16, v0128; CHECK-NEXT: ret129 %c = add <512 x i8> %a, %b130 ret <512 x i8> %c131}132 133define <512 x i8> @vadd_v512i8_zvl512(<512 x i8> %a, <512 x i8> %b) #2 {134; CHECK-LABEL: vadd_v512i8_zvl512:135; CHECK: # %bb.0:136; CHECK-NEXT: li a0, 512137; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma138; CHECK-NEXT: vadd.vv v8, v8, v16139; CHECK-NEXT: ret140 %c = add <512 x i8> %a, %b141 ret <512 x i8> %c142}143 144define <512 x i8> @vadd_v512i8_zvl1024(<512 x i8> %a, <512 x i8> %b) #3 {145; CHECK-LABEL: vadd_v512i8_zvl1024:146; CHECK: # %bb.0:147; CHECK-NEXT: li a0, 512148; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma149; CHECK-NEXT: vadd.vv v8, v8, v12150; CHECK-NEXT: ret151 %c = add <512 x i8> %a, %b152 ret <512 x i8> %c153}154 155define <512 x i8> @vadd_v512i8_zvl2048(<512 x i8> %a, <512 x i8> %b) #4 {156; CHECK-LABEL: vadd_v512i8_zvl2048:157; CHECK: # %bb.0:158; CHECK-NEXT: li a0, 512159; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma160; CHECK-NEXT: vadd.vv v8, v8, v10161; CHECK-NEXT: ret162 %c = add <512 x i8> %a, %b163 ret <512 x i8> %c164}165 166define <512 x i8> @vadd_v512i8_zvl4096(<512 x i8> %a, <512 x i8> %b) #5 {167; CHECK-LABEL: vadd_v512i8_zvl4096:168; CHECK: # %bb.0:169; CHECK-NEXT: li a0, 512170; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma171; CHECK-NEXT: vadd.vv v8, v8, v9172; CHECK-NEXT: ret173 %c = add <512 x i8> %a, %b174 ret <512 x i8> %c175}176 177attributes #0 = { vscale_range(2,1024) }178attributes #1 = { vscale_range(4,1024) }179attributes #2 = { vscale_range(8,1024) }180attributes #3 = { vscale_range(16,1024) }181attributes #4 = { vscale_range(32,1024) }182attributes #5 = { vscale_range(64,1024) }183