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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+m,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+m,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <2 x bfloat> @select_v2bf16(<2 x i1> %a, <2 x bfloat> %b, <2 x bfloat> %c, i32 zeroext %evl) {8; CHECK-LABEL: select_v2bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vmerge.vvm v8, v9, v8, v012; CHECK-NEXT: ret13 %v = call <2 x bfloat> @llvm.vp.select.v2bf16(<2 x i1> %a, <2 x bfloat> %b, <2 x bfloat> %c, i32 %evl)14 ret <2 x bfloat> %v15}16 17define <4 x bfloat> @select_v4bf16(<4 x i1> %a, <4 x bfloat> %b, <4 x bfloat> %c, i32 zeroext %evl) {18; CHECK-LABEL: select_v4bf16:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma21; CHECK-NEXT: vmerge.vvm v8, v9, v8, v022; CHECK-NEXT: ret23 %v = call <4 x bfloat> @llvm.vp.select.v4bf16(<4 x i1> %a, <4 x bfloat> %b, <4 x bfloat> %c, i32 %evl)24 ret <4 x bfloat> %v25}26 27define <8 x bfloat> @select_v8bf16(<8 x i1> %a, <8 x bfloat> %b, <8 x bfloat> %c, i32 zeroext %evl) {28; CHECK-LABEL: select_v8bf16:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma31; CHECK-NEXT: vmerge.vvm v8, v9, v8, v032; CHECK-NEXT: ret33 %v = call <8 x bfloat> @llvm.vp.select.v8bf16(<8 x i1> %a, <8 x bfloat> %b, <8 x bfloat> %c, i32 %evl)34 ret <8 x bfloat> %v35}36 37define <16 x bfloat> @select_v16bf16(<16 x i1> %a, <16 x bfloat> %b, <16 x bfloat> %c, i32 zeroext %evl) {38; CHECK-LABEL: select_v16bf16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma41; CHECK-NEXT: vmerge.vvm v8, v10, v8, v042; CHECK-NEXT: ret43 %v = call <16 x bfloat> @llvm.vp.select.v16bf16(<16 x i1> %a, <16 x bfloat> %b, <16 x bfloat> %c, i32 %evl)44 ret <16 x bfloat> %v45}46