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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define <1 x i1> @select_v1i1(<1 x i1> %a, <1 x i1> %b, <1 x i1> %c, i32 zeroext %evl) {12; CHECK-LABEL: select_v1i1:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vmandn.mm v9, v9, v016; CHECK-NEXT: vmand.mm v8, v8, v017; CHECK-NEXT: vmor.mm v0, v8, v918; CHECK-NEXT: ret19 %v = call <1 x i1> @llvm.vp.select.v1i1(<1 x i1> %a, <1 x i1> %b, <1 x i1> %c, i32 %evl)20 ret <1 x i1> %v21}22 23define <2 x i1> @select_v2i1(<2 x i1> %a, <2 x i1> %b, <2 x i1> %c, i32 zeroext %evl) {24; CHECK-LABEL: select_v2i1:25; CHECK: # %bb.0:26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma27; CHECK-NEXT: vmandn.mm v9, v9, v028; CHECK-NEXT: vmand.mm v8, v8, v029; CHECK-NEXT: vmor.mm v0, v8, v930; CHECK-NEXT: ret31 %v = call <2 x i1> @llvm.vp.select.v2i1(<2 x i1> %a, <2 x i1> %b, <2 x i1> %c, i32 %evl)32 ret <2 x i1> %v33}34 35define <4 x i1> @select_v4i1(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c, i32 zeroext %evl) {36; CHECK-LABEL: select_v4i1:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma39; CHECK-NEXT: vmandn.mm v9, v9, v040; CHECK-NEXT: vmand.mm v8, v8, v041; CHECK-NEXT: vmor.mm v0, v8, v942; CHECK-NEXT: ret43 %v = call <4 x i1> @llvm.vp.select.v4i1(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c, i32 %evl)44 ret <4 x i1> %v45}46 47define <8 x i1> @select_v8i1(<8 x i1> %a, <8 x i1> %b, <8 x i1> %c, i32 zeroext %evl) {48; CHECK-LABEL: select_v8i1:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma51; CHECK-NEXT: vmandn.mm v9, v9, v052; CHECK-NEXT: vmand.mm v8, v8, v053; CHECK-NEXT: vmor.mm v0, v8, v954; CHECK-NEXT: ret55 %v = call <8 x i1> @llvm.vp.select.v8i1(<8 x i1> %a, <8 x i1> %b, <8 x i1> %c, i32 %evl)56 ret <8 x i1> %v57}58 59define <16 x i1> @select_v16i1(<16 x i1> %a, <16 x i1> %b, <16 x i1> %c, i32 zeroext %evl) {60; CHECK-LABEL: select_v16i1:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma63; CHECK-NEXT: vmandn.mm v9, v9, v064; CHECK-NEXT: vmand.mm v8, v8, v065; CHECK-NEXT: vmor.mm v0, v8, v966; CHECK-NEXT: ret67 %v = call <16 x i1> @llvm.vp.select.v16i1(<16 x i1> %a, <16 x i1> %b, <16 x i1> %c, i32 %evl)68 ret <16 x i1> %v69}70 71define <8 x i7> @select_v8i7(<8 x i1> %a, <8 x i7> %b, <8 x i7> %c, i32 zeroext %evl) {72; CHECK-LABEL: select_v8i7:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma75; CHECK-NEXT: vmerge.vvm v8, v9, v8, v076; CHECK-NEXT: ret77 %v = call <8 x i7> @llvm.vp.select.v8i7(<8 x i1> %a, <8 x i7> %b, <8 x i7> %c, i32 %evl)78 ret <8 x i7> %v79}80 81define <2 x i8> @select_v2i8(<2 x i1> %a, <2 x i8> %b, <2 x i8> %c, i32 zeroext %evl) {82; CHECK-LABEL: select_v2i8:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma85; CHECK-NEXT: vmerge.vvm v8, v9, v8, v086; CHECK-NEXT: ret87 %v = call <2 x i8> @llvm.vp.select.v2i8(<2 x i1> %a, <2 x i8> %b, <2 x i8> %c, i32 %evl)88 ret <2 x i8> %v89}90 91define <4 x i8> @select_v4i8(<4 x i1> %a, <4 x i8> %b, <4 x i8> %c, i32 zeroext %evl) {92; CHECK-LABEL: select_v4i8:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma95; CHECK-NEXT: vmerge.vvm v8, v9, v8, v096; CHECK-NEXT: ret97 %v = call <4 x i8> @llvm.vp.select.v4i8(<4 x i1> %a, <4 x i8> %b, <4 x i8> %c, i32 %evl)98 ret <4 x i8> %v99}100 101define <5 x i8> @select_v5i8(<5 x i1> %a, <5 x i8> %b, <5 x i8> %c, i32 zeroext %evl) {102; CHECK-LABEL: select_v5i8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma105; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0106; CHECK-NEXT: ret107 %v = call <5 x i8> @llvm.vp.select.v5i8(<5 x i1> %a, <5 x i8> %b, <5 x i8> %c, i32 %evl)108 ret <5 x i8> %v109}110 111define <8 x i8> @select_v8i8(<8 x i1> %a, <8 x i8> %b, <8 x i8> %c, i32 zeroext %evl) {112; CHECK-LABEL: select_v8i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma115; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0116; CHECK-NEXT: ret117 %v = call <8 x i8> @llvm.vp.select.v8i8(<8 x i1> %a, <8 x i8> %b, <8 x i8> %c, i32 %evl)118 ret <8 x i8> %v119}120 121define <16 x i8> @select_v16i8(<16 x i1> %a, <16 x i8> %b, <16 x i8> %c, i32 zeroext %evl) {122; CHECK-LABEL: select_v16i8:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma125; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0126; CHECK-NEXT: ret127 %v = call <16 x i8> @llvm.vp.select.v16i8(<16 x i1> %a, <16 x i8> %b, <16 x i8> %c, i32 %evl)128 ret <16 x i8> %v129}130 131define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i32 zeroext %evl) {132; CHECK-LABEL: select_v256i8:133; CHECK: # %bb.0:134; CHECK-NEXT: addi sp, sp, -16135; CHECK-NEXT: .cfi_def_cfa_offset 16136; CHECK-NEXT: csrr a2, vlenb137; CHECK-NEXT: slli a2, a2, 3138; CHECK-NEXT: sub sp, sp, a2139; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb140; CHECK-NEXT: addi a2, sp, 16141; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill142; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma143; CHECK-NEXT: vmv1r.v v6, v8144; CHECK-NEXT: vmv1r.v v7, v0145; CHECK-NEXT: li a2, 128146; CHECK-NEXT: addi a4, a1, 128147; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma148; CHECK-NEXT: vle8.v v24, (a0)149; CHECK-NEXT: addi a0, a3, -128150; CHECK-NEXT: vle8.v v8, (a4)151; CHECK-NEXT: sltu a4, a3, a0152; CHECK-NEXT: vle8.v v16, (a1)153; CHECK-NEXT: addi a4, a4, -1154; CHECK-NEXT: and a0, a4, a0155; CHECK-NEXT: vmv1r.v v0, v6156; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma157; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0158; CHECK-NEXT: bltu a3, a2, .LBB11_2159; CHECK-NEXT: # %bb.1:160; CHECK-NEXT: li a3, 128161; CHECK-NEXT: .LBB11_2:162; CHECK-NEXT: vmv1r.v v0, v7163; CHECK-NEXT: addi a0, sp, 16164; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload165; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma166; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0167; CHECK-NEXT: vmv8r.v v16, v24168; CHECK-NEXT: csrr a0, vlenb169; CHECK-NEXT: slli a0, a0, 3170; CHECK-NEXT: add sp, sp, a0171; CHECK-NEXT: .cfi_def_cfa sp, 16172; CHECK-NEXT: addi sp, sp, 16173; CHECK-NEXT: .cfi_def_cfa_offset 0174; CHECK-NEXT: ret175 %v = call <256 x i8> @llvm.vp.select.v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i32 %evl)176 ret <256 x i8> %v177}178 179define <256 x i8> @select_evl_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c) {180; CHECK-LABEL: select_evl_v256i8:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma183; CHECK-NEXT: vmv1r.v v7, v8184; CHECK-NEXT: vmv1r.v v6, v0185; CHECK-NEXT: li a2, 128186; CHECK-NEXT: addi a3, a1, 128187; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma188; CHECK-NEXT: vle8.v v24, (a3)189; CHECK-NEXT: vle8.v v8, (a1)190; CHECK-NEXT: vmv1r.v v0, v7191; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu192; CHECK-NEXT: vle8.v v24, (a0), v0.t193; CHECK-NEXT: vmv1r.v v0, v6194; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma195; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0196; CHECK-NEXT: vmv8r.v v16, v24197; CHECK-NEXT: ret198 %v = call <256 x i8> @llvm.vp.select.v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i32 129)199 ret <256 x i8> %v200}201 202define <2 x i16> @select_v2i16(<2 x i1> %a, <2 x i16> %b, <2 x i16> %c, i32 zeroext %evl) {203; CHECK-LABEL: select_v2i16:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma206; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0207; CHECK-NEXT: ret208 %v = call <2 x i16> @llvm.vp.select.v2i16(<2 x i1> %a, <2 x i16> %b, <2 x i16> %c, i32 %evl)209 ret <2 x i16> %v210}211 212define <4 x i16> @select_v4i16(<4 x i1> %a, <4 x i16> %b, <4 x i16> %c, i32 zeroext %evl) {213; CHECK-LABEL: select_v4i16:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma216; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0217; CHECK-NEXT: ret218 %v = call <4 x i16> @llvm.vp.select.v4i16(<4 x i1> %a, <4 x i16> %b, <4 x i16> %c, i32 %evl)219 ret <4 x i16> %v220}221 222define <8 x i16> @select_v8i16(<8 x i1> %a, <8 x i16> %b, <8 x i16> %c, i32 zeroext %evl) {223; CHECK-LABEL: select_v8i16:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma226; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0227; CHECK-NEXT: ret228 %v = call <8 x i16> @llvm.vp.select.v8i16(<8 x i1> %a, <8 x i16> %b, <8 x i16> %c, i32 %evl)229 ret <8 x i16> %v230}231 232define <16 x i16> @select_v16i16(<16 x i1> %a, <16 x i16> %b, <16 x i16> %c, i32 zeroext %evl) {233; CHECK-LABEL: select_v16i16:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma236; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0237; CHECK-NEXT: ret238 %v = call <16 x i16> @llvm.vp.select.v16i16(<16 x i1> %a, <16 x i16> %b, <16 x i16> %c, i32 %evl)239 ret <16 x i16> %v240}241 242define <2 x i32> @select_v2i32(<2 x i1> %a, <2 x i32> %b, <2 x i32> %c, i32 zeroext %evl) {243; CHECK-LABEL: select_v2i32:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma246; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0247; CHECK-NEXT: ret248 %v = call <2 x i32> @llvm.vp.select.v2i32(<2 x i1> %a, <2 x i32> %b, <2 x i32> %c, i32 %evl)249 ret <2 x i32> %v250}251 252define <4 x i32> @select_v4i32(<4 x i1> %a, <4 x i32> %b, <4 x i32> %c, i32 zeroext %evl) {253; CHECK-LABEL: select_v4i32:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma256; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0257; CHECK-NEXT: ret258 %v = call <4 x i32> @llvm.vp.select.v4i32(<4 x i1> %a, <4 x i32> %b, <4 x i32> %c, i32 %evl)259 ret <4 x i32> %v260}261 262define <8 x i32> @select_v8i32(<8 x i1> %a, <8 x i32> %b, <8 x i32> %c, i32 zeroext %evl) {263; CHECK-LABEL: select_v8i32:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma266; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0267; CHECK-NEXT: ret268 %v = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %a, <8 x i32> %b, <8 x i32> %c, i32 %evl)269 ret <8 x i32> %v270}271 272define <16 x i32> @select_v16i32(<16 x i1> %a, <16 x i32> %b, <16 x i32> %c, i32 zeroext %evl) {273; CHECK-LABEL: select_v16i32:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma276; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0277; CHECK-NEXT: ret278 %v = call <16 x i32> @llvm.vp.select.v16i32(<16 x i1> %a, <16 x i32> %b, <16 x i32> %c, i32 %evl)279 ret <16 x i32> %v280}281 282define <2 x i64> @select_v2i64(<2 x i1> %a, <2 x i64> %b, <2 x i64> %c, i32 zeroext %evl) {283; CHECK-LABEL: select_v2i64:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma286; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0287; CHECK-NEXT: ret288 %v = call <2 x i64> @llvm.vp.select.v2i64(<2 x i1> %a, <2 x i64> %b, <2 x i64> %c, i32 %evl)289 ret <2 x i64> %v290}291 292define <4 x i64> @select_v4i64(<4 x i1> %a, <4 x i64> %b, <4 x i64> %c, i32 zeroext %evl) {293; CHECK-LABEL: select_v4i64:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma296; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0297; CHECK-NEXT: ret298 %v = call <4 x i64> @llvm.vp.select.v4i64(<4 x i1> %a, <4 x i64> %b, <4 x i64> %c, i32 %evl)299 ret <4 x i64> %v300}301 302define <8 x i64> @select_v8i64(<8 x i1> %a, <8 x i64> %b, <8 x i64> %c, i32 zeroext %evl) {303; CHECK-LABEL: select_v8i64:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma306; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0307; CHECK-NEXT: ret308 %v = call <8 x i64> @llvm.vp.select.v8i64(<8 x i1> %a, <8 x i64> %b, <8 x i64> %c, i32 %evl)309 ret <8 x i64> %v310}311 312define <16 x i64> @select_v16i64(<16 x i1> %a, <16 x i64> %b, <16 x i64> %c, i32 zeroext %evl) {313; CHECK-LABEL: select_v16i64:314; CHECK: # %bb.0:315; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma316; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0317; CHECK-NEXT: ret318 %v = call <16 x i64> @llvm.vp.select.v16i64(<16 x i1> %a, <16 x i64> %b, <16 x i64> %c, i32 %evl)319 ret <16 x i64> %v320}321 322define <32 x i64> @select_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 zeroext %evl) {323; CHECK-LABEL: select_v32i64:324; CHECK: # %bb.0:325; CHECK-NEXT: addi sp, sp, -16326; CHECK-NEXT: .cfi_def_cfa_offset 16327; CHECK-NEXT: csrr a1, vlenb328; CHECK-NEXT: slli a1, a1, 3329; CHECK-NEXT: sub sp, sp, a1330; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb331; CHECK-NEXT: addi a1, sp, 16332; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill333; CHECK-NEXT: addi a1, a0, 128334; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma335; CHECK-NEXT: vle64.v v16, (a1)336; CHECK-NEXT: vle64.v v24, (a0)337; CHECK-NEXT: li a1, 16338; CHECK-NEXT: mv a0, a2339; CHECK-NEXT: bltu a2, a1, .LBB25_2340; CHECK-NEXT: # %bb.1:341; CHECK-NEXT: li a0, 16342; CHECK-NEXT: .LBB25_2:343; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma344; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0345; CHECK-NEXT: addi a0, a2, -16346; CHECK-NEXT: sltu a1, a2, a0347; CHECK-NEXT: addi a1, a1, -1348; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma349; CHECK-NEXT: vslidedown.vi v0, v0, 2350; CHECK-NEXT: and a0, a1, a0351; CHECK-NEXT: addi a1, sp, 16352; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload353; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma354; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0355; CHECK-NEXT: csrr a0, vlenb356; CHECK-NEXT: slli a0, a0, 3357; CHECK-NEXT: add sp, sp, a0358; CHECK-NEXT: .cfi_def_cfa sp, 16359; CHECK-NEXT: addi sp, sp, 16360; CHECK-NEXT: .cfi_def_cfa_offset 0361; CHECK-NEXT: ret362 %v = call <32 x i64> @llvm.vp.select.v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 %evl)363 ret <32 x i64> %v364}365 366define <32 x i64> @select_evl_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c) {367; CHECK-LABEL: select_evl_v32i64:368; CHECK: # %bb.0:369; CHECK-NEXT: addi sp, sp, -16370; CHECK-NEXT: .cfi_def_cfa_offset 16371; CHECK-NEXT: csrr a1, vlenb372; CHECK-NEXT: slli a1, a1, 4373; CHECK-NEXT: sub sp, sp, a1374; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb375; CHECK-NEXT: addi a1, sp, 16376; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill377; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma378; CHECK-NEXT: vle64.v v8, (a0)379; CHECK-NEXT: addi a0, a0, 128380; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma381; CHECK-NEXT: vle64.v v24, (a0)382; CHECK-NEXT: csrr a0, vlenb383; CHECK-NEXT: slli a0, a0, 3384; CHECK-NEXT: add a0, sp, a0385; CHECK-NEXT: addi a0, a0, 16386; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill387; CHECK-NEXT: addi a0, sp, 16388; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload389; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma390; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0391; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma392; CHECK-NEXT: vslidedown.vi v0, v0, 2393; CHECK-NEXT: csrr a0, vlenb394; CHECK-NEXT: slli a0, a0, 3395; CHECK-NEXT: add a0, sp, a0396; CHECK-NEXT: addi a0, a0, 16397; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload398; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma399; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0400; CHECK-NEXT: csrr a0, vlenb401; CHECK-NEXT: slli a0, a0, 4402; CHECK-NEXT: add sp, sp, a0403; CHECK-NEXT: .cfi_def_cfa sp, 16404; CHECK-NEXT: addi sp, sp, 16405; CHECK-NEXT: .cfi_def_cfa_offset 0406; CHECK-NEXT: ret407 %v = call <32 x i64> @llvm.vp.select.v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 17)408 ret <32 x i64> %v409}410 411define <2 x half> @select_v2f16(<2 x i1> %a, <2 x half> %b, <2 x half> %c, i32 zeroext %evl) {412; CHECK-LABEL: select_v2f16:413; CHECK: # %bb.0:414; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma415; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0416; CHECK-NEXT: ret417 %v = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %a, <2 x half> %b, <2 x half> %c, i32 %evl)418 ret <2 x half> %v419}420 421define <4 x half> @select_v4f16(<4 x i1> %a, <4 x half> %b, <4 x half> %c, i32 zeroext %evl) {422; CHECK-LABEL: select_v4f16:423; CHECK: # %bb.0:424; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma425; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0426; CHECK-NEXT: ret427 %v = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %a, <4 x half> %b, <4 x half> %c, i32 %evl)428 ret <4 x half> %v429}430 431define <8 x half> @select_v8f16(<8 x i1> %a, <8 x half> %b, <8 x half> %c, i32 zeroext %evl) {432; CHECK-LABEL: select_v8f16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma435; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0436; CHECK-NEXT: ret437 %v = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %a, <8 x half> %b, <8 x half> %c, i32 %evl)438 ret <8 x half> %v439}440 441define <16 x half> @select_v16f16(<16 x i1> %a, <16 x half> %b, <16 x half> %c, i32 zeroext %evl) {442; CHECK-LABEL: select_v16f16:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma445; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0446; CHECK-NEXT: ret447 %v = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %a, <16 x half> %b, <16 x half> %c, i32 %evl)448 ret <16 x half> %v449}450 451define <2 x float> @select_v2f32(<2 x i1> %a, <2 x float> %b, <2 x float> %c, i32 zeroext %evl) {452; CHECK-LABEL: select_v2f32:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma455; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0456; CHECK-NEXT: ret457 %v = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %a, <2 x float> %b, <2 x float> %c, i32 %evl)458 ret <2 x float> %v459}460 461define <4 x float> @select_v4f32(<4 x i1> %a, <4 x float> %b, <4 x float> %c, i32 zeroext %evl) {462; CHECK-LABEL: select_v4f32:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma465; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0466; CHECK-NEXT: ret467 %v = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %a, <4 x float> %b, <4 x float> %c, i32 %evl)468 ret <4 x float> %v469}470 471define <8 x float> @select_v8f32(<8 x i1> %a, <8 x float> %b, <8 x float> %c, i32 zeroext %evl) {472; CHECK-LABEL: select_v8f32:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma475; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0476; CHECK-NEXT: ret477 %v = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %a, <8 x float> %b, <8 x float> %c, i32 %evl)478 ret <8 x float> %v479}480 481define <16 x float> @select_v16f32(<16 x i1> %a, <16 x float> %b, <16 x float> %c, i32 zeroext %evl) {482; CHECK-LABEL: select_v16f32:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma485; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0486; CHECK-NEXT: ret487 %v = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %a, <16 x float> %b, <16 x float> %c, i32 %evl)488 ret <16 x float> %v489}490 491define <64 x float> @select_v64f32(<64 x i1> %a, <64 x float> %b, <64 x float> %c, i32 zeroext %evl) {492; CHECK-LABEL: select_v64f32:493; CHECK: # %bb.0:494; CHECK-NEXT: addi sp, sp, -16495; CHECK-NEXT: .cfi_def_cfa_offset 16496; CHECK-NEXT: csrr a1, vlenb497; CHECK-NEXT: slli a1, a1, 3498; CHECK-NEXT: sub sp, sp, a1499; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb500; CHECK-NEXT: addi a1, sp, 16501; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill502; CHECK-NEXT: addi a1, a0, 128503; CHECK-NEXT: li a3, 32504; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma505; CHECK-NEXT: vle32.v v16, (a1)506; CHECK-NEXT: vle32.v v24, (a0)507; CHECK-NEXT: mv a0, a2508; CHECK-NEXT: bltu a2, a3, .LBB35_2509; CHECK-NEXT: # %bb.1:510; CHECK-NEXT: li a0, 32511; CHECK-NEXT: .LBB35_2:512; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma513; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0514; CHECK-NEXT: addi a0, a2, -32515; CHECK-NEXT: sltu a1, a2, a0516; CHECK-NEXT: addi a1, a1, -1517; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma518; CHECK-NEXT: vslidedown.vi v0, v0, 4519; CHECK-NEXT: and a0, a1, a0520; CHECK-NEXT: addi a1, sp, 16521; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload522; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma523; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0524; CHECK-NEXT: csrr a0, vlenb525; CHECK-NEXT: slli a0, a0, 3526; CHECK-NEXT: add sp, sp, a0527; CHECK-NEXT: .cfi_def_cfa sp, 16528; CHECK-NEXT: addi sp, sp, 16529; CHECK-NEXT: .cfi_def_cfa_offset 0530; CHECK-NEXT: ret531 %v = call <64 x float> @llvm.vp.select.v64f32(<64 x i1> %a, <64 x float> %b, <64 x float> %c, i32 %evl)532 ret <64 x float> %v533}534 535define <2 x double> @select_v2f64(<2 x i1> %a, <2 x double> %b, <2 x double> %c, i32 zeroext %evl) {536; CHECK-LABEL: select_v2f64:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma539; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0540; CHECK-NEXT: ret541 %v = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %a, <2 x double> %b, <2 x double> %c, i32 %evl)542 ret <2 x double> %v543}544 545define <4 x double> @select_v4f64(<4 x i1> %a, <4 x double> %b, <4 x double> %c, i32 zeroext %evl) {546; CHECK-LABEL: select_v4f64:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma549; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0550; CHECK-NEXT: ret551 %v = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %a, <4 x double> %b, <4 x double> %c, i32 %evl)552 ret <4 x double> %v553}554 555define <8 x double> @select_v8f64(<8 x i1> %a, <8 x double> %b, <8 x double> %c, i32 zeroext %evl) {556; CHECK-LABEL: select_v8f64:557; CHECK: # %bb.0:558; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma559; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0560; CHECK-NEXT: ret561 %v = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %a, <8 x double> %b, <8 x double> %c, i32 %evl)562 ret <8 x double> %v563}564 565define <16 x double> @select_v16f64(<16 x i1> %a, <16 x double> %b, <16 x double> %c, i32 zeroext %evl) {566; CHECK-LABEL: select_v16f64:567; CHECK: # %bb.0:568; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma569; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0570; CHECK-NEXT: ret571 %v = call <16 x double> @llvm.vp.select.v16f64(<16 x i1> %a, <16 x double> %b, <16 x double> %c, i32 %evl)572 ret <16 x double> %v573}574