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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV644 5define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {6; RV32-LABEL: vselect_vv_v6i32:7; RV32: # %bb.0:8; RV32-NEXT: lbu a2, 0(a2)9; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma10; RV32-NEXT: vle32.v v8, (a1)11; RV32-NEXT: slli a1, a2, 3012; RV32-NEXT: andi a4, a2, 113; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma14; RV32-NEXT: vmv.v.x v10, a415; RV32-NEXT: slli a4, a2, 2916; RV32-NEXT: srli a1, a1, 3117; RV32-NEXT: vslide1down.vx v10, v10, a118; RV32-NEXT: slli a1, a2, 2819; RV32-NEXT: srli a4, a4, 3120; RV32-NEXT: vslide1down.vx v10, v10, a421; RV32-NEXT: slli a4, a2, 2722; RV32-NEXT: srli a2, a2, 523; RV32-NEXT: srli a1, a1, 3124; RV32-NEXT: srli a4, a4, 3125; RV32-NEXT: vslide1down.vx v10, v10, a126; RV32-NEXT: vslide1down.vx v10, v10, a427; RV32-NEXT: vslide1down.vx v10, v10, a228; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma29; RV32-NEXT: vslidedown.vi v10, v10, 230; RV32-NEXT: vand.vi v10, v10, 131; RV32-NEXT: vmsne.vi v0, v10, 032; RV32-NEXT: vsetvli zero, zero, e32, m2, tu, mu33; RV32-NEXT: vle32.v v8, (a0), v0.t34; RV32-NEXT: vse32.v v8, (a3)35; RV32-NEXT: ret36;37; RV64-LABEL: vselect_vv_v6i32:38; RV64: # %bb.0:39; RV64-NEXT: lbu a2, 0(a2)40; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma41; RV64-NEXT: vle32.v v8, (a1)42; RV64-NEXT: slli a1, a2, 6243; RV64-NEXT: andi a4, a2, 144; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma45; RV64-NEXT: vmv.v.x v10, a446; RV64-NEXT: slli a4, a2, 6147; RV64-NEXT: srli a1, a1, 6348; RV64-NEXT: vslide1down.vx v10, v10, a149; RV64-NEXT: slli a1, a2, 6050; RV64-NEXT: srli a4, a4, 6351; RV64-NEXT: vslide1down.vx v10, v10, a452; RV64-NEXT: slli a4, a2, 5953; RV64-NEXT: srli a2, a2, 554; RV64-NEXT: srli a1, a1, 6355; RV64-NEXT: srli a4, a4, 6356; RV64-NEXT: vslide1down.vx v10, v10, a157; RV64-NEXT: vslide1down.vx v10, v10, a458; RV64-NEXT: vslide1down.vx v10, v10, a259; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma60; RV64-NEXT: vslidedown.vi v10, v10, 261; RV64-NEXT: vand.vi v10, v10, 162; RV64-NEXT: vmsne.vi v0, v10, 063; RV64-NEXT: vsetvli zero, zero, e32, m2, tu, mu64; RV64-NEXT: vle32.v v8, (a0), v0.t65; RV64-NEXT: vse32.v v8, (a3)66; RV64-NEXT: ret67 %va = load <6 x i32>, ptr %a68 %vb = load <6 x i32>, ptr %b69 %vcc = load <6 x i1>, ptr %cc70 %vsel = select <6 x i1> %vcc, <6 x i32> %va, <6 x i32> %vb71 store <6 x i32> %vsel, ptr %z72 ret void73}74 75define void @vselect_vx_v6i32(i32 %a, ptr %b, ptr %cc, ptr %z) {76; RV32-LABEL: vselect_vx_v6i32:77; RV32: # %bb.0:78; RV32-NEXT: lbu a2, 0(a2)79; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma80; RV32-NEXT: vle32.v v8, (a1)81; RV32-NEXT: slli a1, a2, 3082; RV32-NEXT: andi a4, a2, 183; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma84; RV32-NEXT: vmv.v.x v10, a485; RV32-NEXT: slli a4, a2, 2986; RV32-NEXT: srli a1, a1, 3187; RV32-NEXT: vslide1down.vx v10, v10, a188; RV32-NEXT: slli a1, a2, 2889; RV32-NEXT: srli a4, a4, 3190; RV32-NEXT: vslide1down.vx v10, v10, a491; RV32-NEXT: slli a4, a2, 2792; RV32-NEXT: srli a2, a2, 593; RV32-NEXT: srli a1, a1, 3194; RV32-NEXT: srli a4, a4, 3195; RV32-NEXT: vslide1down.vx v10, v10, a196; RV32-NEXT: vslide1down.vx v10, v10, a497; RV32-NEXT: vslide1down.vx v10, v10, a298; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma99; RV32-NEXT: vslidedown.vi v10, v10, 2100; RV32-NEXT: vand.vi v10, v10, 1101; RV32-NEXT: vmsne.vi v0, v10, 0102; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma103; RV32-NEXT: vmerge.vxm v8, v8, a0, v0104; RV32-NEXT: vse32.v v8, (a3)105; RV32-NEXT: ret106;107; RV64-LABEL: vselect_vx_v6i32:108; RV64: # %bb.0:109; RV64-NEXT: lbu a2, 0(a2)110; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma111; RV64-NEXT: vle32.v v8, (a1)112; RV64-NEXT: slli a1, a2, 62113; RV64-NEXT: andi a4, a2, 1114; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma115; RV64-NEXT: vmv.v.x v10, a4116; RV64-NEXT: slli a4, a2, 61117; RV64-NEXT: srli a1, a1, 63118; RV64-NEXT: vslide1down.vx v10, v10, a1119; RV64-NEXT: slli a1, a2, 60120; RV64-NEXT: srli a4, a4, 63121; RV64-NEXT: vslide1down.vx v10, v10, a4122; RV64-NEXT: slli a4, a2, 59123; RV64-NEXT: srli a2, a2, 5124; RV64-NEXT: srli a1, a1, 63125; RV64-NEXT: srli a4, a4, 63126; RV64-NEXT: vslide1down.vx v10, v10, a1127; RV64-NEXT: vslide1down.vx v10, v10, a4128; RV64-NEXT: vslide1down.vx v10, v10, a2129; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma130; RV64-NEXT: vslidedown.vi v10, v10, 2131; RV64-NEXT: vand.vi v10, v10, 1132; RV64-NEXT: vmsne.vi v0, v10, 0133; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma134; RV64-NEXT: vmerge.vxm v8, v8, a0, v0135; RV64-NEXT: vse32.v v8, (a3)136; RV64-NEXT: ret137 %vb = load <6 x i32>, ptr %b138 %ahead = insertelement <6 x i32> poison, i32 %a, i32 0139 %va = shufflevector <6 x i32> %ahead, <6 x i32> poison, <6 x i32> zeroinitializer140 %vcc = load <6 x i1>, ptr %cc141 %vsel = select <6 x i1> %vcc, <6 x i32> %va, <6 x i32> %vb142 store <6 x i32> %vsel, ptr %z143 ret void144}145 146define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) {147; RV32-LABEL: vselect_vi_v6i32:148; RV32: # %bb.0:149; RV32-NEXT: lbu a1, 0(a1)150; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma151; RV32-NEXT: vle32.v v8, (a0)152; RV32-NEXT: slli a0, a1, 30153; RV32-NEXT: andi a3, a1, 1154; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma155; RV32-NEXT: vmv.v.x v10, a3156; RV32-NEXT: slli a3, a1, 29157; RV32-NEXT: srli a0, a0, 31158; RV32-NEXT: vslide1down.vx v10, v10, a0159; RV32-NEXT: slli a0, a1, 28160; RV32-NEXT: srli a3, a3, 31161; RV32-NEXT: vslide1down.vx v10, v10, a3162; RV32-NEXT: slli a3, a1, 27163; RV32-NEXT: srli a1, a1, 5164; RV32-NEXT: srli a0, a0, 31165; RV32-NEXT: srli a3, a3, 31166; RV32-NEXT: vslide1down.vx v10, v10, a0167; RV32-NEXT: vslide1down.vx v10, v10, a3168; RV32-NEXT: vslide1down.vx v10, v10, a1169; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma170; RV32-NEXT: vslidedown.vi v10, v10, 2171; RV32-NEXT: vand.vi v10, v10, 1172; RV32-NEXT: vmsne.vi v0, v10, 0173; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma174; RV32-NEXT: vmerge.vim v8, v8, -1, v0175; RV32-NEXT: vse32.v v8, (a2)176; RV32-NEXT: ret177;178; RV64-LABEL: vselect_vi_v6i32:179; RV64: # %bb.0:180; RV64-NEXT: lbu a1, 0(a1)181; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma182; RV64-NEXT: vle32.v v8, (a0)183; RV64-NEXT: slli a0, a1, 62184; RV64-NEXT: andi a3, a1, 1185; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma186; RV64-NEXT: vmv.v.x v10, a3187; RV64-NEXT: slli a3, a1, 61188; RV64-NEXT: srli a0, a0, 63189; RV64-NEXT: vslide1down.vx v10, v10, a0190; RV64-NEXT: slli a0, a1, 60191; RV64-NEXT: srli a3, a3, 63192; RV64-NEXT: vslide1down.vx v10, v10, a3193; RV64-NEXT: slli a3, a1, 59194; RV64-NEXT: srli a1, a1, 5195; RV64-NEXT: srli a0, a0, 63196; RV64-NEXT: srli a3, a3, 63197; RV64-NEXT: vslide1down.vx v10, v10, a0198; RV64-NEXT: vslide1down.vx v10, v10, a3199; RV64-NEXT: vslide1down.vx v10, v10, a1200; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma201; RV64-NEXT: vslidedown.vi v10, v10, 2202; RV64-NEXT: vand.vi v10, v10, 1203; RV64-NEXT: vmsne.vi v0, v10, 0204; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma205; RV64-NEXT: vmerge.vim v8, v8, -1, v0206; RV64-NEXT: vse32.v v8, (a2)207; RV64-NEXT: ret208 %vb = load <6 x i32>, ptr %b209 %vcc = load <6 x i1>, ptr %cc210 %vsel = select <6 x i1> %vcc, <6 x i32> splat (i32 -1), <6 x i32> %vb211 store <6 x i32> %vsel, ptr %z212 ret void213}214 215 216define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {217; RV32-LABEL: vselect_vv_v6f32:218; RV32: # %bb.0:219; RV32-NEXT: lbu a2, 0(a2)220; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma221; RV32-NEXT: vle32.v v8, (a1)222; RV32-NEXT: slli a1, a2, 30223; RV32-NEXT: andi a4, a2, 1224; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma225; RV32-NEXT: vmv.v.x v10, a4226; RV32-NEXT: slli a4, a2, 29227; RV32-NEXT: srli a1, a1, 31228; RV32-NEXT: vslide1down.vx v10, v10, a1229; RV32-NEXT: slli a1, a2, 28230; RV32-NEXT: srli a4, a4, 31231; RV32-NEXT: vslide1down.vx v10, v10, a4232; RV32-NEXT: slli a4, a2, 27233; RV32-NEXT: srli a2, a2, 5234; RV32-NEXT: srli a1, a1, 31235; RV32-NEXT: srli a4, a4, 31236; RV32-NEXT: vslide1down.vx v10, v10, a1237; RV32-NEXT: vslide1down.vx v10, v10, a4238; RV32-NEXT: vslide1down.vx v10, v10, a2239; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma240; RV32-NEXT: vslidedown.vi v10, v10, 2241; RV32-NEXT: vand.vi v10, v10, 1242; RV32-NEXT: vmsne.vi v0, v10, 0243; RV32-NEXT: vsetvli zero, zero, e32, m2, tu, mu244; RV32-NEXT: vle32.v v8, (a0), v0.t245; RV32-NEXT: vse32.v v8, (a3)246; RV32-NEXT: ret247;248; RV64-LABEL: vselect_vv_v6f32:249; RV64: # %bb.0:250; RV64-NEXT: lbu a2, 0(a2)251; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma252; RV64-NEXT: vle32.v v8, (a1)253; RV64-NEXT: slli a1, a2, 62254; RV64-NEXT: andi a4, a2, 1255; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma256; RV64-NEXT: vmv.v.x v10, a4257; RV64-NEXT: slli a4, a2, 61258; RV64-NEXT: srli a1, a1, 63259; RV64-NEXT: vslide1down.vx v10, v10, a1260; RV64-NEXT: slli a1, a2, 60261; RV64-NEXT: srli a4, a4, 63262; RV64-NEXT: vslide1down.vx v10, v10, a4263; RV64-NEXT: slli a4, a2, 59264; RV64-NEXT: srli a2, a2, 5265; RV64-NEXT: srli a1, a1, 63266; RV64-NEXT: srli a4, a4, 63267; RV64-NEXT: vslide1down.vx v10, v10, a1268; RV64-NEXT: vslide1down.vx v10, v10, a4269; RV64-NEXT: vslide1down.vx v10, v10, a2270; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma271; RV64-NEXT: vslidedown.vi v10, v10, 2272; RV64-NEXT: vand.vi v10, v10, 1273; RV64-NEXT: vmsne.vi v0, v10, 0274; RV64-NEXT: vsetvli zero, zero, e32, m2, tu, mu275; RV64-NEXT: vle32.v v8, (a0), v0.t276; RV64-NEXT: vse32.v v8, (a3)277; RV64-NEXT: ret278 %va = load <6 x float>, ptr %a279 %vb = load <6 x float>, ptr %b280 %vcc = load <6 x i1>, ptr %cc281 %vsel = select <6 x i1> %vcc, <6 x float> %va, <6 x float> %vb282 store <6 x float> %vsel, ptr %z283 ret void284}285 286define void @vselect_vx_v6f32(float %a, ptr %b, ptr %cc, ptr %z) {287; RV32-LABEL: vselect_vx_v6f32:288; RV32: # %bb.0:289; RV32-NEXT: lbu a1, 0(a1)290; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma291; RV32-NEXT: vle32.v v8, (a0)292; RV32-NEXT: slli a0, a1, 30293; RV32-NEXT: andi a3, a1, 1294; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma295; RV32-NEXT: vmv.v.x v10, a3296; RV32-NEXT: slli a3, a1, 29297; RV32-NEXT: srli a0, a0, 31298; RV32-NEXT: vslide1down.vx v10, v10, a0299; RV32-NEXT: slli a0, a1, 28300; RV32-NEXT: srli a3, a3, 31301; RV32-NEXT: vslide1down.vx v10, v10, a3302; RV32-NEXT: slli a3, a1, 27303; RV32-NEXT: srli a1, a1, 5304; RV32-NEXT: srli a0, a0, 31305; RV32-NEXT: srli a3, a3, 31306; RV32-NEXT: vslide1down.vx v10, v10, a0307; RV32-NEXT: vslide1down.vx v10, v10, a3308; RV32-NEXT: vslide1down.vx v10, v10, a1309; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma310; RV32-NEXT: vslidedown.vi v10, v10, 2311; RV32-NEXT: vand.vi v10, v10, 1312; RV32-NEXT: vmsne.vi v0, v10, 0313; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma314; RV32-NEXT: vfmerge.vfm v8, v8, fa0, v0315; RV32-NEXT: vse32.v v8, (a2)316; RV32-NEXT: ret317;318; RV64-LABEL: vselect_vx_v6f32:319; RV64: # %bb.0:320; RV64-NEXT: lbu a1, 0(a1)321; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma322; RV64-NEXT: vle32.v v8, (a0)323; RV64-NEXT: slli a0, a1, 62324; RV64-NEXT: andi a3, a1, 1325; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma326; RV64-NEXT: vmv.v.x v10, a3327; RV64-NEXT: slli a3, a1, 61328; RV64-NEXT: srli a0, a0, 63329; RV64-NEXT: vslide1down.vx v10, v10, a0330; RV64-NEXT: slli a0, a1, 60331; RV64-NEXT: srli a3, a3, 63332; RV64-NEXT: vslide1down.vx v10, v10, a3333; RV64-NEXT: slli a3, a1, 59334; RV64-NEXT: srli a1, a1, 5335; RV64-NEXT: srli a0, a0, 63336; RV64-NEXT: srli a3, a3, 63337; RV64-NEXT: vslide1down.vx v10, v10, a0338; RV64-NEXT: vslide1down.vx v10, v10, a3339; RV64-NEXT: vslide1down.vx v10, v10, a1340; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma341; RV64-NEXT: vslidedown.vi v10, v10, 2342; RV64-NEXT: vand.vi v10, v10, 1343; RV64-NEXT: vmsne.vi v0, v10, 0344; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma345; RV64-NEXT: vfmerge.vfm v8, v8, fa0, v0346; RV64-NEXT: vse32.v v8, (a2)347; RV64-NEXT: ret348 %vb = load <6 x float>, ptr %b349 %ahead = insertelement <6 x float> poison, float %a, i32 0350 %va = shufflevector <6 x float> %ahead, <6 x float> poison, <6 x i32> zeroinitializer351 %vcc = load <6 x i1>, ptr %cc352 %vsel = select <6 x i1> %vcc, <6 x float> %va, <6 x float> %vb353 store <6 x float> %vsel, ptr %z354 ret void355}356 357define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) {358; RV32-LABEL: vselect_vfpzero_v6f32:359; RV32: # %bb.0:360; RV32-NEXT: lbu a1, 0(a1)361; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma362; RV32-NEXT: vle32.v v8, (a0)363; RV32-NEXT: slli a0, a1, 30364; RV32-NEXT: andi a3, a1, 1365; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma366; RV32-NEXT: vmv.v.x v10, a3367; RV32-NEXT: slli a3, a1, 29368; RV32-NEXT: srli a0, a0, 31369; RV32-NEXT: vslide1down.vx v10, v10, a0370; RV32-NEXT: slli a0, a1, 28371; RV32-NEXT: srli a3, a3, 31372; RV32-NEXT: vslide1down.vx v10, v10, a3373; RV32-NEXT: slli a3, a1, 27374; RV32-NEXT: srli a1, a1, 5375; RV32-NEXT: srli a0, a0, 31376; RV32-NEXT: srli a3, a3, 31377; RV32-NEXT: vslide1down.vx v10, v10, a0378; RV32-NEXT: vslide1down.vx v10, v10, a3379; RV32-NEXT: vslide1down.vx v10, v10, a1380; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma381; RV32-NEXT: vslidedown.vi v10, v10, 2382; RV32-NEXT: vand.vi v10, v10, 1383; RV32-NEXT: vmsne.vi v0, v10, 0384; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma385; RV32-NEXT: vmerge.vim v8, v8, 0, v0386; RV32-NEXT: vse32.v v8, (a2)387; RV32-NEXT: ret388;389; RV64-LABEL: vselect_vfpzero_v6f32:390; RV64: # %bb.0:391; RV64-NEXT: lbu a1, 0(a1)392; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma393; RV64-NEXT: vle32.v v8, (a0)394; RV64-NEXT: slli a0, a1, 62395; RV64-NEXT: andi a3, a1, 1396; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma397; RV64-NEXT: vmv.v.x v10, a3398; RV64-NEXT: slli a3, a1, 61399; RV64-NEXT: srli a0, a0, 63400; RV64-NEXT: vslide1down.vx v10, v10, a0401; RV64-NEXT: slli a0, a1, 60402; RV64-NEXT: srli a3, a3, 63403; RV64-NEXT: vslide1down.vx v10, v10, a3404; RV64-NEXT: slli a3, a1, 59405; RV64-NEXT: srli a1, a1, 5406; RV64-NEXT: srli a0, a0, 63407; RV64-NEXT: srli a3, a3, 63408; RV64-NEXT: vslide1down.vx v10, v10, a0409; RV64-NEXT: vslide1down.vx v10, v10, a3410; RV64-NEXT: vslide1down.vx v10, v10, a1411; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma412; RV64-NEXT: vslidedown.vi v10, v10, 2413; RV64-NEXT: vand.vi v10, v10, 1414; RV64-NEXT: vmsne.vi v0, v10, 0415; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma416; RV64-NEXT: vmerge.vim v8, v8, 0, v0417; RV64-NEXT: vse32.v v8, (a2)418; RV64-NEXT: ret419 %vb = load <6 x float>, ptr %b420 %vcc = load <6 x i1>, ptr %cc421 %vsel = select <6 x i1> %vcc, <6 x float> splat (float 0.0), <6 x float> %vb422 store <6 x float> %vsel, ptr %z423 ret void424}425 426define void @vselect_vv_v8i32(ptr %a, ptr %b, ptr %cc, ptr %z) {427; CHECK-LABEL: vselect_vv_v8i32:428; CHECK: # %bb.0:429; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu430; CHECK-NEXT: vlm.v v0, (a2)431; CHECK-NEXT: vle32.v v8, (a1)432; CHECK-NEXT: vle32.v v8, (a0), v0.t433; CHECK-NEXT: vse32.v v8, (a3)434; CHECK-NEXT: ret435 %va = load <8 x i32>, ptr %a436 %vb = load <8 x i32>, ptr %b437 %vcc = load <8 x i1>, ptr %cc438 %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb439 store <8 x i32> %vsel, ptr %z440 ret void441}442 443define void @vselect_vx_v8i32(i32 %a, ptr %b, ptr %cc, ptr %z) {444; CHECK-LABEL: vselect_vx_v8i32:445; CHECK: # %bb.0:446; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma447; CHECK-NEXT: vlm.v v0, (a2)448; CHECK-NEXT: vle32.v v8, (a1)449; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0450; CHECK-NEXT: vse32.v v8, (a3)451; CHECK-NEXT: ret452 %vb = load <8 x i32>, ptr %b453 %ahead = insertelement <8 x i32> poison, i32 %a, i32 0454 %va = shufflevector <8 x i32> %ahead, <8 x i32> poison, <8 x i32> zeroinitializer455 %vcc = load <8 x i1>, ptr %cc456 %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb457 store <8 x i32> %vsel, ptr %z458 ret void459}460 461define void @vselect_vi_v8i32(ptr %b, ptr %cc, ptr %z) {462; CHECK-LABEL: vselect_vi_v8i32:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma465; CHECK-NEXT: vlm.v v0, (a1)466; CHECK-NEXT: vle32.v v8, (a0)467; CHECK-NEXT: vmerge.vim v8, v8, -1, v0468; CHECK-NEXT: vse32.v v8, (a2)469; CHECK-NEXT: ret470 %vb = load <8 x i32>, ptr %b471 %vcc = load <8 x i1>, ptr %cc472 %vsel = select <8 x i1> %vcc, <8 x i32> splat (i32 -1), <8 x i32> %vb473 store <8 x i32> %vsel, ptr %z474 ret void475}476 477define void @vselect_vv_v8f32(ptr %a, ptr %b, ptr %cc, ptr %z) {478; CHECK-LABEL: vselect_vv_v8f32:479; CHECK: # %bb.0:480; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu481; CHECK-NEXT: vlm.v v0, (a2)482; CHECK-NEXT: vle32.v v8, (a1)483; CHECK-NEXT: vle32.v v8, (a0), v0.t484; CHECK-NEXT: vse32.v v8, (a3)485; CHECK-NEXT: ret486 %va = load <8 x float>, ptr %a487 %vb = load <8 x float>, ptr %b488 %vcc = load <8 x i1>, ptr %cc489 %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb490 store <8 x float> %vsel, ptr %z491 ret void492}493 494define void @vselect_vx_v8f32(float %a, ptr %b, ptr %cc, ptr %z) {495; CHECK-LABEL: vselect_vx_v8f32:496; CHECK: # %bb.0:497; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma498; CHECK-NEXT: vlm.v v0, (a1)499; CHECK-NEXT: vle32.v v8, (a0)500; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0501; CHECK-NEXT: vse32.v v8, (a2)502; CHECK-NEXT: ret503 %vb = load <8 x float>, ptr %b504 %ahead = insertelement <8 x float> poison, float %a, i32 0505 %va = shufflevector <8 x float> %ahead, <8 x float> poison, <8 x i32> zeroinitializer506 %vcc = load <8 x i1>, ptr %cc507 %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb508 store <8 x float> %vsel, ptr %z509 ret void510}511 512define void @vselect_vfpzero_v8f32(ptr %b, ptr %cc, ptr %z) {513; CHECK-LABEL: vselect_vfpzero_v8f32:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma516; CHECK-NEXT: vlm.v v0, (a1)517; CHECK-NEXT: vle32.v v8, (a0)518; CHECK-NEXT: vmerge.vim v8, v8, 0, v0519; CHECK-NEXT: vse32.v v8, (a2)520; CHECK-NEXT: ret521 %vb = load <8 x float>, ptr %b522 %vcc = load <8 x i1>, ptr %cc523 %vsel = select <8 x i1> %vcc, <8 x float> splat (float 0.0), <8 x float> %vb524 store <8 x float> %vsel, ptr %z525 ret void526}527 528define void @vselect_vv_v16i16(ptr %a, ptr %b, ptr %cc, ptr %z) {529; CHECK-LABEL: vselect_vv_v16i16:530; CHECK: # %bb.0:531; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu532; CHECK-NEXT: vlm.v v0, (a2)533; CHECK-NEXT: vle16.v v8, (a1)534; CHECK-NEXT: vle16.v v8, (a0), v0.t535; CHECK-NEXT: vse16.v v8, (a3)536; CHECK-NEXT: ret537 %va = load <16 x i16>, ptr %a538 %vb = load <16 x i16>, ptr %b539 %vcc = load <16 x i1>, ptr %cc540 %vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb541 store <16 x i16> %vsel, ptr %z542 ret void543}544 545define void @vselect_vx_v16i16(i16 signext %a, ptr %b, ptr %cc, ptr %z) {546; CHECK-LABEL: vselect_vx_v16i16:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma549; CHECK-NEXT: vlm.v v0, (a2)550; CHECK-NEXT: vle16.v v8, (a1)551; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0552; CHECK-NEXT: vse16.v v8, (a3)553; CHECK-NEXT: ret554 %vb = load <16 x i16>, ptr %b555 %ahead = insertelement <16 x i16> poison, i16 %a, i32 0556 %va = shufflevector <16 x i16> %ahead, <16 x i16> poison, <16 x i32> zeroinitializer557 %vcc = load <16 x i1>, ptr %cc558 %vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb559 store <16 x i16> %vsel, ptr %z560 ret void561}562 563define void @vselect_vi_v16i16(ptr %b, ptr %cc, ptr %z) {564; CHECK-LABEL: vselect_vi_v16i16:565; CHECK: # %bb.0:566; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma567; CHECK-NEXT: vlm.v v0, (a1)568; CHECK-NEXT: vle16.v v8, (a0)569; CHECK-NEXT: vmerge.vim v8, v8, 4, v0570; CHECK-NEXT: vse16.v v8, (a2)571; CHECK-NEXT: ret572 %vb = load <16 x i16>, ptr %b573 %vcc = load <16 x i1>, ptr %cc574 %vsel = select <16 x i1> %vcc, <16 x i16> splat (i16 4), <16 x i16> %vb575 store <16 x i16> %vsel, ptr %z576 ret void577}578 579define void @vselect_vv_v32f16(ptr %a, ptr %b, ptr %cc, ptr %z) {580; CHECK-LABEL: vselect_vv_v32f16:581; CHECK: # %bb.0:582; CHECK-NEXT: li a4, 32583; CHECK-NEXT: vsetvli zero, a4, e16, m4, ta, mu584; CHECK-NEXT: vlm.v v0, (a2)585; CHECK-NEXT: vle16.v v8, (a1)586; CHECK-NEXT: vle16.v v8, (a0), v0.t587; CHECK-NEXT: vse16.v v8, (a3)588; CHECK-NEXT: ret589 %va = load <32 x half>, ptr %a590 %vb = load <32 x half>, ptr %b591 %vcc = load <32 x i1>, ptr %cc592 %vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb593 store <32 x half> %vsel, ptr %z594 ret void595}596 597define void @vselect_vx_v32f16(half %a, ptr %b, ptr %cc, ptr %z) {598; CHECK-LABEL: vselect_vx_v32f16:599; CHECK: # %bb.0:600; CHECK-NEXT: li a3, 32601; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma602; CHECK-NEXT: vlm.v v0, (a1)603; CHECK-NEXT: vle16.v v8, (a0)604; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0605; CHECK-NEXT: vse16.v v8, (a2)606; CHECK-NEXT: ret607 %vb = load <32 x half>, ptr %b608 %ahead = insertelement <32 x half> poison, half %a, i32 0609 %va = shufflevector <32 x half> %ahead, <32 x half> poison, <32 x i32> zeroinitializer610 %vcc = load <32 x i1>, ptr %cc611 %vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb612 store <32 x half> %vsel, ptr %z613 ret void614}615 616define void @vselect_vfpzero_v32f16(ptr %b, ptr %cc, ptr %z) {617; CHECK-LABEL: vselect_vfpzero_v32f16:618; CHECK: # %bb.0:619; CHECK-NEXT: li a3, 32620; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma621; CHECK-NEXT: vlm.v v0, (a1)622; CHECK-NEXT: vle16.v v8, (a0)623; CHECK-NEXT: vmerge.vim v8, v8, 0, v0624; CHECK-NEXT: vse16.v v8, (a2)625; CHECK-NEXT: ret626 %vb = load <32 x half>, ptr %b627 %vcc = load <32 x i1>, ptr %cc628 %vsel = select <32 x i1> %vcc, <32 x half> splat (half 0.0), <32 x half> %vb629 store <32 x half> %vsel, ptr %z630 ret void631}632 633define <2 x i1> @vselect_v2i1(<2 x i1> %a, <2 x i1> %b, <2 x i1> %cc) {634; CHECK-LABEL: vselect_v2i1:635; CHECK: # %bb.0:636; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma637; CHECK-NEXT: vmandn.mm v8, v8, v9638; CHECK-NEXT: vmand.mm v9, v0, v9639; CHECK-NEXT: vmor.mm v0, v9, v8640; CHECK-NEXT: ret641 %v = select <2 x i1> %cc, <2 x i1> %a, <2 x i1> %b642 ret <2 x i1> %v643}644 645define <4 x i1> @vselect_v4i1(<4 x i1> %a, <4 x i1> %b, <4 x i1> %cc) {646; CHECK-LABEL: vselect_v4i1:647; CHECK: # %bb.0:648; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma649; CHECK-NEXT: vmandn.mm v8, v8, v9650; CHECK-NEXT: vmand.mm v9, v0, v9651; CHECK-NEXT: vmor.mm v0, v9, v8652; CHECK-NEXT: ret653 %v = select <4 x i1> %cc, <4 x i1> %a, <4 x i1> %b654 ret <4 x i1> %v655}656 657define <8 x i1> @vselect_v8i1(<8 x i1> %a, <8 x i1> %b, <8 x i1> %cc) {658; CHECK-LABEL: vselect_v8i1:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma661; CHECK-NEXT: vmandn.mm v8, v8, v9662; CHECK-NEXT: vmand.mm v9, v0, v9663; CHECK-NEXT: vmor.mm v0, v9, v8664; CHECK-NEXT: ret665 %v = select <8 x i1> %cc, <8 x i1> %a, <8 x i1> %b666 ret <8 x i1> %v667}668 669define <16 x i1> @vselect_v16i1(<16 x i1> %a, <16 x i1> %b, <16 x i1> %cc) {670; CHECK-LABEL: vselect_v16i1:671; CHECK: # %bb.0:672; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma673; CHECK-NEXT: vmandn.mm v8, v8, v9674; CHECK-NEXT: vmand.mm v9, v0, v9675; CHECK-NEXT: vmor.mm v0, v9, v8676; CHECK-NEXT: ret677 %v = select <16 x i1> %cc, <16 x i1> %a, <16 x i1> %b678 ret <16 x i1> %v679}680 681define <32 x i1> @vselect_v32i1(<32 x i1> %a, <32 x i1> %b, <32 x i1> %cc) {682; CHECK-LABEL: vselect_v32i1:683; CHECK: # %bb.0:684; CHECK-NEXT: li a0, 32685; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma686; CHECK-NEXT: vmandn.mm v8, v8, v9687; CHECK-NEXT: vmand.mm v9, v0, v9688; CHECK-NEXT: vmor.mm v0, v9, v8689; CHECK-NEXT: ret690 %v = select <32 x i1> %cc, <32 x i1> %a, <32 x i1> %b691 ret <32 x i1> %v692}693 694define <64 x i1> @vselect_v64i1(<64 x i1> %a, <64 x i1> %b, <64 x i1> %cc) {695; CHECK-LABEL: vselect_v64i1:696; CHECK: # %bb.0:697; CHECK-NEXT: li a0, 64698; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma699; CHECK-NEXT: vmandn.mm v8, v8, v9700; CHECK-NEXT: vmand.mm v9, v0, v9701; CHECK-NEXT: vmor.mm v0, v9, v8702; CHECK-NEXT: ret703 %v = select <64 x i1> %cc, <64 x i1> %a, <64 x i1> %b704 ret <64 x i1> %v705}706