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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vsra_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: li a1, 12711; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma12; CHECK-NEXT: vand.vx v9, v9, a1, v0.t13; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t14; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t15; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t16; CHECK-NEXT: ret17 %v = call <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)18 ret <8 x i7> %v19}20 21define <2 x i8> @vsra_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: vsra_vv_v2i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma25; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t26; CHECK-NEXT: ret27 %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)28 ret <2 x i8> %v29}30 31define <2 x i8> @vsra_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {32; CHECK-LABEL: vsra_vv_v2i8_unmasked:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma35; CHECK-NEXT: vsra.vv v8, v8, v936; CHECK-NEXT: ret37 %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)38 ret <2 x i8> %v39}40 41define <2 x i8> @vsra_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {42; CHECK-LABEL: vsra_vx_v2i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma45; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t46; CHECK-NEXT: ret47 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 048 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer49 %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)50 ret <2 x i8> %v51}52 53define <2 x i8> @vsra_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {54; CHECK-LABEL: vsra_vx_v2i8_unmasked:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma57; CHECK-NEXT: vsra.vx v8, v8, a058; CHECK-NEXT: ret59 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 060 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer61 %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)62 ret <2 x i8> %v63}64 65define <2 x i8> @vsra_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {66; CHECK-LABEL: vsra_vi_v2i8:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma69; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t70; CHECK-NEXT: ret71 %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> %m, i32 %evl)72 ret <2 x i8> %v73}74 75define <2 x i8> @vsra_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {76; CHECK-LABEL: vsra_vi_v2i8_unmasked:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma79; CHECK-NEXT: vsra.vi v8, v8, 580; CHECK-NEXT: ret81 %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> splat (i1 true), i32 %evl)82 ret <2 x i8> %v83}84 85define <4 x i8> @vsra_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: vsra_vv_v4i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma89; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t90; CHECK-NEXT: ret91 %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)92 ret <4 x i8> %v93}94 95define <4 x i8> @vsra_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {96; CHECK-LABEL: vsra_vv_v4i8_unmasked:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma99; CHECK-NEXT: vsra.vv v8, v8, v9100; CHECK-NEXT: ret101 %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)102 ret <4 x i8> %v103}104 105define <4 x i8> @vsra_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {106; CHECK-LABEL: vsra_vx_v4i8:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma109; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t110; CHECK-NEXT: ret111 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0112 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer113 %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)114 ret <4 x i8> %v115}116 117define <4 x i8> @vsra_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {118; CHECK-LABEL: vsra_vx_v4i8_unmasked:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma121; CHECK-NEXT: vsra.vx v8, v8, a0122; CHECK-NEXT: ret123 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0124 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer125 %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)126 ret <4 x i8> %v127}128 129define <4 x i8> @vsra_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {130; CHECK-LABEL: vsra_vi_v4i8:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma133; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t134; CHECK-NEXT: ret135 %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> %m, i32 %evl)136 ret <4 x i8> %v137}138 139define <4 x i8> @vsra_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {140; CHECK-LABEL: vsra_vi_v4i8_unmasked:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma143; CHECK-NEXT: vsra.vi v8, v8, 5144; CHECK-NEXT: ret145 %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> splat (i1 true), i32 %evl)146 ret <4 x i8> %v147}148 149define <7 x i8> @vsra_vv_v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 zeroext %evl) {150; CHECK-LABEL: vsra_vv_v7i8:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma153; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t154; CHECK-NEXT: ret155 %v = call <7 x i8> @llvm.vp.ashr.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 %evl)156 ret <7 x i8> %v157}158 159define <8 x i8> @vsra_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {160; CHECK-LABEL: vsra_vv_v8i8:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma163; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t164; CHECK-NEXT: ret165 %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)166 ret <8 x i8> %v167}168 169define <8 x i8> @vsra_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {170; CHECK-LABEL: vsra_vv_v8i8_unmasked:171; CHECK: # %bb.0:172; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma173; CHECK-NEXT: vsra.vv v8, v8, v9174; CHECK-NEXT: ret175 %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)176 ret <8 x i8> %v177}178 179define <8 x i8> @vsra_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {180; CHECK-LABEL: vsra_vx_v8i8:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma183; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t184; CHECK-NEXT: ret185 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0186 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer187 %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)188 ret <8 x i8> %v189}190 191define <8 x i8> @vsra_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {192; CHECK-LABEL: vsra_vx_v8i8_unmasked:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma195; CHECK-NEXT: vsra.vx v8, v8, a0196; CHECK-NEXT: ret197 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0198 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer199 %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)200 ret <8 x i8> %v201}202 203define <8 x i8> @vsra_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {204; CHECK-LABEL: vsra_vi_v8i8:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma207; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t208; CHECK-NEXT: ret209 %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> %m, i32 %evl)210 ret <8 x i8> %v211}212 213define <8 x i8> @vsra_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {214; CHECK-LABEL: vsra_vi_v8i8_unmasked:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma217; CHECK-NEXT: vsra.vi v8, v8, 5218; CHECK-NEXT: ret219 %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> splat (i1 true), i32 %evl)220 ret <8 x i8> %v221}222 223define <16 x i8> @vsra_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {224; CHECK-LABEL: vsra_vv_v16i8:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma227; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t228; CHECK-NEXT: ret229 %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)230 ret <16 x i8> %v231}232 233define <16 x i8> @vsra_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {234; CHECK-LABEL: vsra_vv_v16i8_unmasked:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma237; CHECK-NEXT: vsra.vv v8, v8, v9238; CHECK-NEXT: ret239 %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)240 ret <16 x i8> %v241}242 243define <16 x i8> @vsra_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {244; CHECK-LABEL: vsra_vx_v16i8:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma247; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t248; CHECK-NEXT: ret249 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0250 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer251 %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)252 ret <16 x i8> %v253}254 255define <16 x i8> @vsra_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {256; CHECK-LABEL: vsra_vx_v16i8_unmasked:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma259; CHECK-NEXT: vsra.vx v8, v8, a0260; CHECK-NEXT: ret261 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0262 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer263 %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)264 ret <16 x i8> %v265}266 267define <16 x i8> @vsra_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {268; CHECK-LABEL: vsra_vi_v16i8:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma271; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t272; CHECK-NEXT: ret273 %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> %m, i32 %evl)274 ret <16 x i8> %v275}276 277define <16 x i8> @vsra_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {278; CHECK-LABEL: vsra_vi_v16i8_unmasked:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma281; CHECK-NEXT: vsra.vi v8, v8, 5282; CHECK-NEXT: ret283 %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> splat (i1 true), i32 %evl)284 ret <16 x i8> %v285}286 287define <2 x i16> @vsra_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {288; CHECK-LABEL: vsra_vv_v2i16:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma291; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t292; CHECK-NEXT: ret293 %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)294 ret <2 x i16> %v295}296 297define <2 x i16> @vsra_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {298; CHECK-LABEL: vsra_vv_v2i16_unmasked:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma301; CHECK-NEXT: vsra.vv v8, v8, v9302; CHECK-NEXT: ret303 %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)304 ret <2 x i16> %v305}306 307define <2 x i16> @vsra_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {308; CHECK-LABEL: vsra_vx_v2i16:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma311; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t312; CHECK-NEXT: ret313 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0314 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer315 %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)316 ret <2 x i16> %v317}318 319define <2 x i16> @vsra_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {320; CHECK-LABEL: vsra_vx_v2i16_unmasked:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma323; CHECK-NEXT: vsra.vx v8, v8, a0324; CHECK-NEXT: ret325 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0326 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer327 %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)328 ret <2 x i16> %v329}330 331define <2 x i16> @vsra_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: vsra_vi_v2i16:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma335; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t336; CHECK-NEXT: ret337 %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> %m, i32 %evl)338 ret <2 x i16> %v339}340 341define <2 x i16> @vsra_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {342; CHECK-LABEL: vsra_vi_v2i16_unmasked:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma345; CHECK-NEXT: vsra.vi v8, v8, 5346; CHECK-NEXT: ret347 %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> splat (i1 true), i32 %evl)348 ret <2 x i16> %v349}350 351define <4 x i16> @vsra_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {352; CHECK-LABEL: vsra_vv_v4i16:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma355; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t356; CHECK-NEXT: ret357 %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)358 ret <4 x i16> %v359}360 361define <4 x i16> @vsra_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {362; CHECK-LABEL: vsra_vv_v4i16_unmasked:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma365; CHECK-NEXT: vsra.vv v8, v8, v9366; CHECK-NEXT: ret367 %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)368 ret <4 x i16> %v369}370 371define <4 x i16> @vsra_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vsra_vx_v4i16:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma375; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t376; CHECK-NEXT: ret377 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0378 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer379 %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)380 ret <4 x i16> %v381}382 383define <4 x i16> @vsra_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {384; CHECK-LABEL: vsra_vx_v4i16_unmasked:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma387; CHECK-NEXT: vsra.vx v8, v8, a0388; CHECK-NEXT: ret389 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0390 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer391 %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)392 ret <4 x i16> %v393}394 395define <4 x i16> @vsra_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {396; CHECK-LABEL: vsra_vi_v4i16:397; CHECK: # %bb.0:398; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma399; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t400; CHECK-NEXT: ret401 %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> %m, i32 %evl)402 ret <4 x i16> %v403}404 405define <4 x i16> @vsra_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {406; CHECK-LABEL: vsra_vi_v4i16_unmasked:407; CHECK: # %bb.0:408; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma409; CHECK-NEXT: vsra.vi v8, v8, 5410; CHECK-NEXT: ret411 %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> splat (i1 true), i32 %evl)412 ret <4 x i16> %v413}414 415define <8 x i16> @vsra_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {416; CHECK-LABEL: vsra_vv_v8i16:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma419; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t420; CHECK-NEXT: ret421 %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)422 ret <8 x i16> %v423}424 425define <8 x i16> @vsra_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {426; CHECK-LABEL: vsra_vv_v8i16_unmasked:427; CHECK: # %bb.0:428; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma429; CHECK-NEXT: vsra.vv v8, v8, v9430; CHECK-NEXT: ret431 %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)432 ret <8 x i16> %v433}434 435define <8 x i16> @vsra_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {436; CHECK-LABEL: vsra_vx_v8i16:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma439; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t440; CHECK-NEXT: ret441 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0442 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer443 %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)444 ret <8 x i16> %v445}446 447define <8 x i16> @vsra_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {448; CHECK-LABEL: vsra_vx_v8i16_unmasked:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma451; CHECK-NEXT: vsra.vx v8, v8, a0452; CHECK-NEXT: ret453 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0454 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer455 %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)456 ret <8 x i16> %v457}458 459define <8 x i16> @vsra_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: vsra_vi_v8i16:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma463; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t464; CHECK-NEXT: ret465 %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> %m, i32 %evl)466 ret <8 x i16> %v467}468 469define <8 x i16> @vsra_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {470; CHECK-LABEL: vsra_vi_v8i16_unmasked:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma473; CHECK-NEXT: vsra.vi v8, v8, 5474; CHECK-NEXT: ret475 %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> splat (i1 true), i32 %evl)476 ret <8 x i16> %v477}478 479define <16 x i16> @vsra_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: vsra_vv_v16i16:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma483; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t484; CHECK-NEXT: ret485 %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)486 ret <16 x i16> %v487}488 489define <16 x i16> @vsra_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {490; CHECK-LABEL: vsra_vv_v16i16_unmasked:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma493; CHECK-NEXT: vsra.vv v8, v8, v10494; CHECK-NEXT: ret495 %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)496 ret <16 x i16> %v497}498 499define <16 x i16> @vsra_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {500; CHECK-LABEL: vsra_vx_v16i16:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma503; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t504; CHECK-NEXT: ret505 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0506 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer507 %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)508 ret <16 x i16> %v509}510 511define <16 x i16> @vsra_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {512; CHECK-LABEL: vsra_vx_v16i16_unmasked:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma515; CHECK-NEXT: vsra.vx v8, v8, a0516; CHECK-NEXT: ret517 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0518 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer519 %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)520 ret <16 x i16> %v521}522 523define <16 x i16> @vsra_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {524; CHECK-LABEL: vsra_vi_v16i16:525; CHECK: # %bb.0:526; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma527; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t528; CHECK-NEXT: ret529 %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> %m, i32 %evl)530 ret <16 x i16> %v531}532 533define <16 x i16> @vsra_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {534; CHECK-LABEL: vsra_vi_v16i16_unmasked:535; CHECK: # %bb.0:536; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma537; CHECK-NEXT: vsra.vi v8, v8, 5538; CHECK-NEXT: ret539 %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> splat (i1 true), i32 %evl)540 ret <16 x i16> %v541}542 543define <2 x i32> @vsra_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {544; CHECK-LABEL: vsra_vv_v2i32:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma547; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t548; CHECK-NEXT: ret549 %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)550 ret <2 x i32> %v551}552 553define <2 x i32> @vsra_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {554; CHECK-LABEL: vsra_vv_v2i32_unmasked:555; CHECK: # %bb.0:556; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma557; CHECK-NEXT: vsra.vv v8, v8, v9558; CHECK-NEXT: ret559 %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)560 ret <2 x i32> %v561}562 563define <2 x i32> @vsra_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {564; CHECK-LABEL: vsra_vx_v2i32:565; CHECK: # %bb.0:566; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma567; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t568; CHECK-NEXT: ret569 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0570 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer571 %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)572 ret <2 x i32> %v573}574 575define <2 x i32> @vsra_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {576; CHECK-LABEL: vsra_vx_v2i32_unmasked:577; CHECK: # %bb.0:578; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma579; CHECK-NEXT: vsra.vx v8, v8, a0580; CHECK-NEXT: ret581 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0582 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer583 %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)584 ret <2 x i32> %v585}586 587define <2 x i32> @vsra_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {588; CHECK-LABEL: vsra_vi_v2i32:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma591; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t592; CHECK-NEXT: ret593 %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> %m, i32 %evl)594 ret <2 x i32> %v595}596 597define <2 x i32> @vsra_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {598; CHECK-LABEL: vsra_vi_v2i32_unmasked:599; CHECK: # %bb.0:600; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma601; CHECK-NEXT: vsra.vi v8, v8, 5602; CHECK-NEXT: ret603 %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> splat (i1 true), i32 %evl)604 ret <2 x i32> %v605}606 607define <4 x i32> @vsra_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {608; CHECK-LABEL: vsra_vv_v4i32:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma611; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t612; CHECK-NEXT: ret613 %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)614 ret <4 x i32> %v615}616 617define <4 x i32> @vsra_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {618; CHECK-LABEL: vsra_vv_v4i32_unmasked:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma621; CHECK-NEXT: vsra.vv v8, v8, v9622; CHECK-NEXT: ret623 %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)624 ret <4 x i32> %v625}626 627define <4 x i32> @vsra_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {628; CHECK-LABEL: vsra_vx_v4i32:629; CHECK: # %bb.0:630; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma631; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t632; CHECK-NEXT: ret633 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0634 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer635 %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)636 ret <4 x i32> %v637}638 639define <4 x i32> @vsra_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {640; CHECK-LABEL: vsra_vx_v4i32_unmasked:641; CHECK: # %bb.0:642; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma643; CHECK-NEXT: vsra.vx v8, v8, a0644; CHECK-NEXT: ret645 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0646 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer647 %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)648 ret <4 x i32> %v649}650 651define <4 x i32> @vsra_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {652; CHECK-LABEL: vsra_vi_v4i32:653; CHECK: # %bb.0:654; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma655; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t656; CHECK-NEXT: ret657 %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> %m, i32 %evl)658 ret <4 x i32> %v659}660 661define <4 x i32> @vsra_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {662; CHECK-LABEL: vsra_vi_v4i32_unmasked:663; CHECK: # %bb.0:664; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma665; CHECK-NEXT: vsra.vi v8, v8, 5666; CHECK-NEXT: ret667 %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> splat (i1 true), i32 %evl)668 ret <4 x i32> %v669}670 671define <8 x i32> @vsra_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {672; CHECK-LABEL: vsra_vv_v8i32:673; CHECK: # %bb.0:674; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma675; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t676; CHECK-NEXT: ret677 %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)678 ret <8 x i32> %v679}680 681define <8 x i32> @vsra_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {682; CHECK-LABEL: vsra_vv_v8i32_unmasked:683; CHECK: # %bb.0:684; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma685; CHECK-NEXT: vsra.vv v8, v8, v10686; CHECK-NEXT: ret687 %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)688 ret <8 x i32> %v689}690 691define <8 x i32> @vsra_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {692; CHECK-LABEL: vsra_vx_v8i32:693; CHECK: # %bb.0:694; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma695; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t696; CHECK-NEXT: ret697 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0698 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer699 %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)700 ret <8 x i32> %v701}702 703define <8 x i32> @vsra_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {704; CHECK-LABEL: vsra_vx_v8i32_unmasked:705; CHECK: # %bb.0:706; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma707; CHECK-NEXT: vsra.vx v8, v8, a0708; CHECK-NEXT: ret709 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0710 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer711 %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)712 ret <8 x i32> %v713}714 715define <8 x i32> @vsra_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {716; CHECK-LABEL: vsra_vi_v8i32:717; CHECK: # %bb.0:718; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma719; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t720; CHECK-NEXT: ret721 %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> %m, i32 %evl)722 ret <8 x i32> %v723}724 725define <8 x i32> @vsra_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {726; CHECK-LABEL: vsra_vi_v8i32_unmasked:727; CHECK: # %bb.0:728; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma729; CHECK-NEXT: vsra.vi v8, v8, 5730; CHECK-NEXT: ret731 %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> splat (i1 true), i32 %evl)732 ret <8 x i32> %v733}734 735define <16 x i32> @vsra_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vsra_vv_v16i32:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma739; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t740; CHECK-NEXT: ret741 %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)742 ret <16 x i32> %v743}744 745define <16 x i32> @vsra_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {746; CHECK-LABEL: vsra_vv_v16i32_unmasked:747; CHECK: # %bb.0:748; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma749; CHECK-NEXT: vsra.vv v8, v8, v12750; CHECK-NEXT: ret751 %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)752 ret <16 x i32> %v753}754 755define <16 x i32> @vsra_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {756; CHECK-LABEL: vsra_vx_v16i32:757; CHECK: # %bb.0:758; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma759; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t760; CHECK-NEXT: ret761 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0762 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer763 %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)764 ret <16 x i32> %v765}766 767define <16 x i32> @vsra_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {768; CHECK-LABEL: vsra_vx_v16i32_unmasked:769; CHECK: # %bb.0:770; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma771; CHECK-NEXT: vsra.vx v8, v8, a0772; CHECK-NEXT: ret773 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0774 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer775 %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)776 ret <16 x i32> %v777}778 779define <16 x i32> @vsra_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {780; CHECK-LABEL: vsra_vi_v16i32:781; CHECK: # %bb.0:782; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma783; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t784; CHECK-NEXT: ret785 %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> %m, i32 %evl)786 ret <16 x i32> %v787}788 789define <16 x i32> @vsra_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {790; CHECK-LABEL: vsra_vi_v16i32_unmasked:791; CHECK: # %bb.0:792; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma793; CHECK-NEXT: vsra.vi v8, v8, 5794; CHECK-NEXT: ret795 %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> splat (i1 true), i32 %evl)796 ret <16 x i32> %v797}798 799define <2 x i64> @vsra_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {800; CHECK-LABEL: vsra_vv_v2i64:801; CHECK: # %bb.0:802; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma803; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t804; CHECK-NEXT: ret805 %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)806 ret <2 x i64> %v807}808 809define <2 x i64> @vsra_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {810; CHECK-LABEL: vsra_vv_v2i64_unmasked:811; CHECK: # %bb.0:812; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma813; CHECK-NEXT: vsra.vv v8, v8, v9814; CHECK-NEXT: ret815 %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)816 ret <2 x i64> %v817}818 819define <2 x i64> @vsra_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {820; RV32-LABEL: vsra_vx_v2i64:821; RV32: # %bb.0:822; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma823; RV32-NEXT: vsra.vx v8, v8, a0, v0.t824; RV32-NEXT: ret825;826; RV64-LABEL: vsra_vx_v2i64:827; RV64: # %bb.0:828; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma829; RV64-NEXT: vsra.vx v8, v8, a0, v0.t830; RV64-NEXT: ret831 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0832 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer833 %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)834 ret <2 x i64> %v835}836 837define <2 x i64> @vsra_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {838; RV32-LABEL: vsra_vx_v2i64_unmasked:839; RV32: # %bb.0:840; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma841; RV32-NEXT: vsra.vx v8, v8, a0842; RV32-NEXT: ret843;844; RV64-LABEL: vsra_vx_v2i64_unmasked:845; RV64: # %bb.0:846; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma847; RV64-NEXT: vsra.vx v8, v8, a0848; RV64-NEXT: ret849 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0850 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer851 %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)852 ret <2 x i64> %v853}854 855define <2 x i64> @vsra_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {856; CHECK-LABEL: vsra_vi_v2i64:857; CHECK: # %bb.0:858; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma859; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t860; CHECK-NEXT: ret861 %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> %m, i32 %evl)862 ret <2 x i64> %v863}864 865define <2 x i64> @vsra_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {866; CHECK-LABEL: vsra_vi_v2i64_unmasked:867; CHECK: # %bb.0:868; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma869; CHECK-NEXT: vsra.vi v8, v8, 5870; CHECK-NEXT: ret871 %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> splat (i1 true), i32 %evl)872 ret <2 x i64> %v873}874 875define <4 x i64> @vsra_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {876; CHECK-LABEL: vsra_vv_v4i64:877; CHECK: # %bb.0:878; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma879; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t880; CHECK-NEXT: ret881 %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)882 ret <4 x i64> %v883}884 885define <4 x i64> @vsra_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {886; CHECK-LABEL: vsra_vv_v4i64_unmasked:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma889; CHECK-NEXT: vsra.vv v8, v8, v10890; CHECK-NEXT: ret891 %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)892 ret <4 x i64> %v893}894 895define <4 x i64> @vsra_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {896; RV32-LABEL: vsra_vx_v4i64:897; RV32: # %bb.0:898; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma899; RV32-NEXT: vsra.vx v8, v8, a0, v0.t900; RV32-NEXT: ret901;902; RV64-LABEL: vsra_vx_v4i64:903; RV64: # %bb.0:904; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma905; RV64-NEXT: vsra.vx v8, v8, a0, v0.t906; RV64-NEXT: ret907 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0908 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer909 %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)910 ret <4 x i64> %v911}912 913define <4 x i64> @vsra_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {914; RV32-LABEL: vsra_vx_v4i64_unmasked:915; RV32: # %bb.0:916; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma917; RV32-NEXT: vsra.vx v8, v8, a0918; RV32-NEXT: ret919;920; RV64-LABEL: vsra_vx_v4i64_unmasked:921; RV64: # %bb.0:922; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma923; RV64-NEXT: vsra.vx v8, v8, a0924; RV64-NEXT: ret925 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0926 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer927 %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)928 ret <4 x i64> %v929}930 931define <4 x i64> @vsra_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {932; CHECK-LABEL: vsra_vi_v4i64:933; CHECK: # %bb.0:934; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma935; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t936; CHECK-NEXT: ret937 %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> %m, i32 %evl)938 ret <4 x i64> %v939}940 941define <4 x i64> @vsra_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {942; CHECK-LABEL: vsra_vi_v4i64_unmasked:943; CHECK: # %bb.0:944; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma945; CHECK-NEXT: vsra.vi v8, v8, 5946; CHECK-NEXT: ret947 %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> splat (i1 true), i32 %evl)948 ret <4 x i64> %v949}950 951define <8 x i64> @vsra_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {952; CHECK-LABEL: vsra_vv_v8i64:953; CHECK: # %bb.0:954; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma955; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t956; CHECK-NEXT: ret957 %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)958 ret <8 x i64> %v959}960 961define <8 x i64> @vsra_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {962; CHECK-LABEL: vsra_vv_v8i64_unmasked:963; CHECK: # %bb.0:964; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma965; CHECK-NEXT: vsra.vv v8, v8, v12966; CHECK-NEXT: ret967 %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)968 ret <8 x i64> %v969}970 971define <8 x i64> @vsra_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {972; RV32-LABEL: vsra_vx_v8i64:973; RV32: # %bb.0:974; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma975; RV32-NEXT: vsra.vx v8, v8, a0, v0.t976; RV32-NEXT: ret977;978; RV64-LABEL: vsra_vx_v8i64:979; RV64: # %bb.0:980; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma981; RV64-NEXT: vsra.vx v8, v8, a0, v0.t982; RV64-NEXT: ret983 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0984 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer985 %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)986 ret <8 x i64> %v987}988 989define <8 x i64> @vsra_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {990; RV32-LABEL: vsra_vx_v8i64_unmasked:991; RV32: # %bb.0:992; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma993; RV32-NEXT: vsra.vx v8, v8, a0994; RV32-NEXT: ret995;996; RV64-LABEL: vsra_vx_v8i64_unmasked:997; RV64: # %bb.0:998; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma999; RV64-NEXT: vsra.vx v8, v8, a01000; RV64-NEXT: ret1001 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01002 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1003 %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)1004 ret <8 x i64> %v1005}1006 1007define <8 x i64> @vsra_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1008; CHECK-LABEL: vsra_vi_v8i64:1009; CHECK: # %bb.0:1010; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1011; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1012; CHECK-NEXT: ret1013 %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> %m, i32 %evl)1014 ret <8 x i64> %v1015}1016 1017define <8 x i64> @vsra_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1018; CHECK-LABEL: vsra_vi_v8i64_unmasked:1019; CHECK: # %bb.0:1020; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1021; CHECK-NEXT: vsra.vi v8, v8, 51022; CHECK-NEXT: ret1023 %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> splat (i1 true), i32 %evl)1024 ret <8 x i64> %v1025}1026 1027define <16 x i64> @vsra_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {1028; CHECK-LABEL: vsra_vv_v16i64:1029; CHECK: # %bb.0:1030; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1031; CHECK-NEXT: vsra.vv v8, v8, v16, v0.t1032; CHECK-NEXT: ret1033 %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)1034 ret <16 x i64> %v1035}1036 1037define <16 x i64> @vsra_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {1038; CHECK-LABEL: vsra_vv_v16i64_unmasked:1039; CHECK: # %bb.0:1040; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1041; CHECK-NEXT: vsra.vv v8, v8, v161042; CHECK-NEXT: ret1043 %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)1044 ret <16 x i64> %v1045}1046 1047define <16 x i64> @vsra_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {1048; RV32-LABEL: vsra_vx_v16i64:1049; RV32: # %bb.0:1050; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1051; RV32-NEXT: vsra.vx v8, v8, a0, v0.t1052; RV32-NEXT: ret1053;1054; RV64-LABEL: vsra_vx_v16i64:1055; RV64: # %bb.0:1056; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1057; RV64-NEXT: vsra.vx v8, v8, a0, v0.t1058; RV64-NEXT: ret1059 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01060 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1061 %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)1062 ret <16 x i64> %v1063}1064 1065define <16 x i64> @vsra_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {1066; RV32-LABEL: vsra_vx_v16i64_unmasked:1067; RV32: # %bb.0:1068; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1069; RV32-NEXT: vsra.vx v8, v8, a01070; RV32-NEXT: ret1071;1072; RV64-LABEL: vsra_vx_v16i64_unmasked:1073; RV64: # %bb.0:1074; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1075; RV64-NEXT: vsra.vx v8, v8, a01076; RV64-NEXT: ret1077 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01078 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1079 %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)1080 ret <16 x i64> %v1081}1082 1083define <16 x i64> @vsra_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1084; CHECK-LABEL: vsra_vi_v16i64:1085; CHECK: # %bb.0:1086; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1087; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1088; CHECK-NEXT: ret1089 %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> %m, i32 %evl)1090 ret <16 x i64> %v1091}1092 1093define <16 x i64> @vsra_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1094; CHECK-LABEL: vsra_vi_v16i64_unmasked:1095; CHECK: # %bb.0:1096; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1097; CHECK-NEXT: vsra.vi v8, v8, 51098; CHECK-NEXT: ret1099 %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> splat (i1 true), i32 %evl)1100 ret <16 x i64> %v1101}1102