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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vssub_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vssub_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma11; CHECK-NEXT: vadd.vv v9, v9, v912; CHECK-NEXT: vadd.vv v8, v8, v813; CHECK-NEXT: li a1, 6314; CHECK-NEXT: vsra.vi v9, v9, 115; CHECK-NEXT: vsra.vi v8, v8, 116; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma17; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t18; CHECK-NEXT: vmin.vx v8, v8, a1, v0.t19; CHECK-NEXT: li a0, 19220; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t21; CHECK-NEXT: ret22 %v = call <8 x i7> @llvm.vp.ssub.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)23 ret <8 x i7> %v24}25 26define <2 x i8> @vssub_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {27; CHECK-LABEL: vssub_vv_v2i8:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma30; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t31; CHECK-NEXT: ret32 %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)33 ret <2 x i8> %v34}35 36define <2 x i8> @vssub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {37; CHECK-LABEL: vssub_vv_v2i8_unmasked:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma40; CHECK-NEXT: vssub.vv v8, v8, v941; CHECK-NEXT: ret42 %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)43 ret <2 x i8> %v44}45 46define <2 x i8> @vssub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {47; CHECK-LABEL: vssub_vx_v2i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma50; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t51; CHECK-NEXT: ret52 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 053 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer54 %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)55 ret <2 x i8> %v56}57 58define <2 x i8> @vssub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {59; CHECK-LABEL: vssub_vx_v2i8_unmasked:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma62; CHECK-NEXT: vssub.vx v8, v8, a063; CHECK-NEXT: ret64 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 065 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer66 %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)67 ret <2 x i8> %v68}69 70define <2 x i8> @vssub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {71; CHECK-LABEL: vssub_vi_v2i8:72; CHECK: # %bb.0:73; CHECK-NEXT: li a1, -174; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma75; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t76; CHECK-NEXT: ret77 %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)78 ret <2 x i8> %v79}80 81define <2 x i8> @vssub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {82; CHECK-LABEL: vssub_vi_v2i8_unmasked:83; CHECK: # %bb.0:84; CHECK-NEXT: li a1, -185; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma86; CHECK-NEXT: vssub.vx v8, v8, a187; CHECK-NEXT: ret88 %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)89 ret <2 x i8> %v90}91 92define <4 x i8> @vssub_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {93; CHECK-LABEL: vssub_vv_v4i8:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma96; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t97; CHECK-NEXT: ret98 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)99 ret <4 x i8> %v100}101 102define <4 x i8> @vssub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {103; CHECK-LABEL: vssub_vv_v4i8_unmasked:104; CHECK: # %bb.0:105; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma106; CHECK-NEXT: vssub.vv v8, v8, v9107; CHECK-NEXT: ret108 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)109 ret <4 x i8> %v110}111 112define <4 x i8> @vssub_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {113; CHECK-LABEL: vssub_vx_v4i8:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma116; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t117; CHECK-NEXT: ret118 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0119 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer120 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)121 ret <4 x i8> %v122}123 124define <4 x i8> @vssub_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {125; CHECK-LABEL: vssub_vx_v4i8_commute:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma128; CHECK-NEXT: vmv.v.x v9, a0129; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma130; CHECK-NEXT: vssub.vv v8, v9, v8, v0.t131; CHECK-NEXT: ret132 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0133 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer134 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)135 ret <4 x i8> %v136}137 138define <4 x i8> @vssub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {139; CHECK-LABEL: vssub_vx_v4i8_unmasked:140; CHECK: # %bb.0:141; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma142; CHECK-NEXT: vssub.vx v8, v8, a0143; CHECK-NEXT: ret144 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0145 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer146 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)147 ret <4 x i8> %v148}149 150define <4 x i8> @vssub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {151; CHECK-LABEL: vssub_vi_v4i8:152; CHECK: # %bb.0:153; CHECK-NEXT: li a1, -1154; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma155; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t156; CHECK-NEXT: ret157 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)158 ret <4 x i8> %v159}160 161define <4 x i8> @vssub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {162; CHECK-LABEL: vssub_vi_v4i8_unmasked:163; CHECK: # %bb.0:164; CHECK-NEXT: li a1, -1165; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma166; CHECK-NEXT: vssub.vx v8, v8, a1167; CHECK-NEXT: ret168 %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)169 ret <4 x i8> %v170}171 172define <5 x i8> @vssub_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {173; CHECK-LABEL: vssub_vv_v5i8:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma176; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t177; CHECK-NEXT: ret178 %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)179 ret <5 x i8> %v180}181 182define <5 x i8> @vssub_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {183; CHECK-LABEL: vssub_vv_v5i8_unmasked:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma186; CHECK-NEXT: vssub.vv v8, v8, v9187; CHECK-NEXT: ret188 %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)189 ret <5 x i8> %v190}191 192define <5 x i8> @vssub_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {193; CHECK-LABEL: vssub_vx_v5i8:194; CHECK: # %bb.0:195; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma196; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t197; CHECK-NEXT: ret198 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0199 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer200 %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)201 ret <5 x i8> %v202}203 204define <5 x i8> @vssub_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {205; CHECK-LABEL: vssub_vx_v5i8_unmasked:206; CHECK: # %bb.0:207; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma208; CHECK-NEXT: vssub.vx v8, v8, a0209; CHECK-NEXT: ret210 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0211 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer212 %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)213 ret <5 x i8> %v214}215 216define <5 x i8> @vssub_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {217; CHECK-LABEL: vssub_vi_v5i8:218; CHECK: # %bb.0:219; CHECK-NEXT: li a1, -1220; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma221; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t222; CHECK-NEXT: ret223 %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)224 ret <5 x i8> %v225}226 227define <5 x i8> @vssub_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {228; CHECK-LABEL: vssub_vi_v5i8_unmasked:229; CHECK: # %bb.0:230; CHECK-NEXT: li a1, -1231; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma232; CHECK-NEXT: vssub.vx v8, v8, a1233; CHECK-NEXT: ret234 %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)235 ret <5 x i8> %v236}237 238define <8 x i8> @vssub_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {239; CHECK-LABEL: vssub_vv_v8i8:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma242; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t243; CHECK-NEXT: ret244 %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)245 ret <8 x i8> %v246}247 248define <8 x i8> @vssub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {249; CHECK-LABEL: vssub_vv_v8i8_unmasked:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma252; CHECK-NEXT: vssub.vv v8, v8, v9253; CHECK-NEXT: ret254 %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)255 ret <8 x i8> %v256}257 258define <8 x i8> @vssub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {259; CHECK-LABEL: vssub_vx_v8i8:260; CHECK: # %bb.0:261; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma262; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t263; CHECK-NEXT: ret264 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0265 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer266 %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)267 ret <8 x i8> %v268}269 270define <8 x i8> @vssub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {271; CHECK-LABEL: vssub_vx_v8i8_unmasked:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma274; CHECK-NEXT: vssub.vx v8, v8, a0275; CHECK-NEXT: ret276 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0277 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer278 %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)279 ret <8 x i8> %v280}281 282define <8 x i8> @vssub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {283; CHECK-LABEL: vssub_vi_v8i8:284; CHECK: # %bb.0:285; CHECK-NEXT: li a1, -1286; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma287; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t288; CHECK-NEXT: ret289 %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)290 ret <8 x i8> %v291}292 293define <8 x i8> @vssub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {294; CHECK-LABEL: vssub_vi_v8i8_unmasked:295; CHECK: # %bb.0:296; CHECK-NEXT: li a1, -1297; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma298; CHECK-NEXT: vssub.vx v8, v8, a1299; CHECK-NEXT: ret300 %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)301 ret <8 x i8> %v302}303 304define <16 x i8> @vssub_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {305; CHECK-LABEL: vssub_vv_v16i8:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma308; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t309; CHECK-NEXT: ret310 %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)311 ret <16 x i8> %v312}313 314define <16 x i8> @vssub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {315; CHECK-LABEL: vssub_vv_v16i8_unmasked:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma318; CHECK-NEXT: vssub.vv v8, v8, v9319; CHECK-NEXT: ret320 %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)321 ret <16 x i8> %v322}323 324define <16 x i8> @vssub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {325; CHECK-LABEL: vssub_vx_v16i8:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma328; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t329; CHECK-NEXT: ret330 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0331 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer332 %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)333 ret <16 x i8> %v334}335 336define <16 x i8> @vssub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {337; CHECK-LABEL: vssub_vx_v16i8_unmasked:338; CHECK: # %bb.0:339; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma340; CHECK-NEXT: vssub.vx v8, v8, a0341; CHECK-NEXT: ret342 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0343 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer344 %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)345 ret <16 x i8> %v346}347 348define <16 x i8> @vssub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {349; CHECK-LABEL: vssub_vi_v16i8:350; CHECK: # %bb.0:351; CHECK-NEXT: li a1, -1352; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma353; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t354; CHECK-NEXT: ret355 %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)356 ret <16 x i8> %v357}358 359define <16 x i8> @vssub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {360; CHECK-LABEL: vssub_vi_v16i8_unmasked:361; CHECK: # %bb.0:362; CHECK-NEXT: li a1, -1363; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma364; CHECK-NEXT: vssub.vx v8, v8, a1365; CHECK-NEXT: ret366 %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)367 ret <16 x i8> %v368}369 370define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {371; CHECK-LABEL: vssub_vi_v258i8:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma374; CHECK-NEXT: vmv1r.v v24, v0375; CHECK-NEXT: li a2, 128376; CHECK-NEXT: addi a3, a1, -128377; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma378; CHECK-NEXT: vlm.v v0, (a0)379; CHECK-NEXT: sltu a0, a1, a3380; CHECK-NEXT: addi a0, a0, -1381; CHECK-NEXT: and a3, a0, a3382; CHECK-NEXT: li a0, -1383; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma384; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t385; CHECK-NEXT: bltu a1, a2, .LBB32_2386; CHECK-NEXT: # %bb.1:387; CHECK-NEXT: li a1, 128388; CHECK-NEXT: .LBB32_2:389; CHECK-NEXT: vmv1r.v v0, v24390; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma391; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t392; CHECK-NEXT: ret393 %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)394 ret <256 x i8> %v395}396 397define <256 x i8> @vssub_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {398; CHECK-LABEL: vssub_vi_v258i8_unmasked:399; CHECK: # %bb.0:400; CHECK-NEXT: li a2, 128401; CHECK-NEXT: mv a1, a0402; CHECK-NEXT: bltu a0, a2, .LBB33_2403; CHECK-NEXT: # %bb.1:404; CHECK-NEXT: li a1, 128405; CHECK-NEXT: .LBB33_2:406; CHECK-NEXT: li a2, -1407; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma408; CHECK-NEXT: vssub.vx v8, v8, a2409; CHECK-NEXT: addi a1, a0, -128410; CHECK-NEXT: sltu a0, a0, a1411; CHECK-NEXT: addi a0, a0, -1412; CHECK-NEXT: and a0, a0, a1413; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma414; CHECK-NEXT: vssub.vx v16, v16, a2415; CHECK-NEXT: ret416 %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)417 ret <256 x i8> %v418}419 420; Test splitting when the %evl is a known constant.421 422define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {423; CHECK-LABEL: vssub_vi_v258i8_evl129:424; CHECK: # %bb.0:425; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma426; CHECK-NEXT: vlm.v v24, (a0)427; CHECK-NEXT: li a0, 128428; CHECK-NEXT: li a1, -1429; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma430; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t431; CHECK-NEXT: vmv1r.v v0, v24432; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma433; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t434; CHECK-NEXT: ret435 %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)436 ret <256 x i8> %v437}438 439define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {440; CHECK-LABEL: vssub_vi_v258i8_evl128:441; CHECK: # %bb.0:442; CHECK-NEXT: li a0, 128443; CHECK-NEXT: li a1, -1444; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma445; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t446; CHECK-NEXT: ret447 %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)448 ret <256 x i8> %v449}450 451define <2 x i16> @vssub_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {452; CHECK-LABEL: vssub_vv_v2i16:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma455; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t456; CHECK-NEXT: ret457 %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)458 ret <2 x i16> %v459}460 461define <2 x i16> @vssub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {462; CHECK-LABEL: vssub_vv_v2i16_unmasked:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma465; CHECK-NEXT: vssub.vv v8, v8, v9466; CHECK-NEXT: ret467 %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)468 ret <2 x i16> %v469}470 471define <2 x i16> @vssub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {472; CHECK-LABEL: vssub_vx_v2i16:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma475; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t476; CHECK-NEXT: ret477 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0478 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer479 %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)480 ret <2 x i16> %v481}482 483define <2 x i16> @vssub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {484; CHECK-LABEL: vssub_vx_v2i16_unmasked:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma487; CHECK-NEXT: vssub.vx v8, v8, a0488; CHECK-NEXT: ret489 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0490 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer491 %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)492 ret <2 x i16> %v493}494 495define <2 x i16> @vssub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {496; CHECK-LABEL: vssub_vi_v2i16:497; CHECK: # %bb.0:498; CHECK-NEXT: li a1, -1499; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma500; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t501; CHECK-NEXT: ret502 %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)503 ret <2 x i16> %v504}505 506define <2 x i16> @vssub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {507; CHECK-LABEL: vssub_vi_v2i16_unmasked:508; CHECK: # %bb.0:509; CHECK-NEXT: li a1, -1510; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma511; CHECK-NEXT: vssub.vx v8, v8, a1512; CHECK-NEXT: ret513 %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)514 ret <2 x i16> %v515}516 517define <4 x i16> @vssub_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {518; CHECK-LABEL: vssub_vv_v4i16:519; CHECK: # %bb.0:520; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma521; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t522; CHECK-NEXT: ret523 %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)524 ret <4 x i16> %v525}526 527define <4 x i16> @vssub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {528; CHECK-LABEL: vssub_vv_v4i16_unmasked:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma531; CHECK-NEXT: vssub.vv v8, v8, v9532; CHECK-NEXT: ret533 %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)534 ret <4 x i16> %v535}536 537define <4 x i16> @vssub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {538; CHECK-LABEL: vssub_vx_v4i16:539; CHECK: # %bb.0:540; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma541; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t542; CHECK-NEXT: ret543 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0544 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer545 %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)546 ret <4 x i16> %v547}548 549define <4 x i16> @vssub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {550; CHECK-LABEL: vssub_vx_v4i16_unmasked:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma553; CHECK-NEXT: vssub.vx v8, v8, a0554; CHECK-NEXT: ret555 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0556 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer557 %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)558 ret <4 x i16> %v559}560 561define <4 x i16> @vssub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {562; CHECK-LABEL: vssub_vi_v4i16:563; CHECK: # %bb.0:564; CHECK-NEXT: li a1, -1565; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma566; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t567; CHECK-NEXT: ret568 %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)569 ret <4 x i16> %v570}571 572define <4 x i16> @vssub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {573; CHECK-LABEL: vssub_vi_v4i16_unmasked:574; CHECK: # %bb.0:575; CHECK-NEXT: li a1, -1576; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma577; CHECK-NEXT: vssub.vx v8, v8, a1578; CHECK-NEXT: ret579 %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)580 ret <4 x i16> %v581}582 583define <8 x i16> @vssub_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {584; CHECK-LABEL: vssub_vv_v8i16:585; CHECK: # %bb.0:586; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma587; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t588; CHECK-NEXT: ret589 %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)590 ret <8 x i16> %v591}592 593define <8 x i16> @vssub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {594; CHECK-LABEL: vssub_vv_v8i16_unmasked:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma597; CHECK-NEXT: vssub.vv v8, v8, v9598; CHECK-NEXT: ret599 %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)600 ret <8 x i16> %v601}602 603define <8 x i16> @vssub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {604; CHECK-LABEL: vssub_vx_v8i16:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma607; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t608; CHECK-NEXT: ret609 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0610 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer611 %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)612 ret <8 x i16> %v613}614 615define <8 x i16> @vssub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {616; CHECK-LABEL: vssub_vx_v8i16_unmasked:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma619; CHECK-NEXT: vssub.vx v8, v8, a0620; CHECK-NEXT: ret621 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0622 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer623 %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)624 ret <8 x i16> %v625}626 627define <8 x i16> @vssub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {628; CHECK-LABEL: vssub_vi_v8i16:629; CHECK: # %bb.0:630; CHECK-NEXT: li a1, -1631; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma632; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t633; CHECK-NEXT: ret634 %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)635 ret <8 x i16> %v636}637 638define <8 x i16> @vssub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {639; CHECK-LABEL: vssub_vi_v8i16_unmasked:640; CHECK: # %bb.0:641; CHECK-NEXT: li a1, -1642; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma643; CHECK-NEXT: vssub.vx v8, v8, a1644; CHECK-NEXT: ret645 %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)646 ret <8 x i16> %v647}648 649define <16 x i16> @vssub_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {650; CHECK-LABEL: vssub_vv_v16i16:651; CHECK: # %bb.0:652; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma653; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t654; CHECK-NEXT: ret655 %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)656 ret <16 x i16> %v657}658 659define <16 x i16> @vssub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {660; CHECK-LABEL: vssub_vv_v16i16_unmasked:661; CHECK: # %bb.0:662; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma663; CHECK-NEXT: vssub.vv v8, v8, v10664; CHECK-NEXT: ret665 %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)666 ret <16 x i16> %v667}668 669define <16 x i16> @vssub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {670; CHECK-LABEL: vssub_vx_v16i16:671; CHECK: # %bb.0:672; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma673; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t674; CHECK-NEXT: ret675 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0676 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer677 %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)678 ret <16 x i16> %v679}680 681define <16 x i16> @vssub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {682; CHECK-LABEL: vssub_vx_v16i16_unmasked:683; CHECK: # %bb.0:684; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma685; CHECK-NEXT: vssub.vx v8, v8, a0686; CHECK-NEXT: ret687 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0688 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer689 %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)690 ret <16 x i16> %v691}692 693define <16 x i16> @vssub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {694; CHECK-LABEL: vssub_vi_v16i16:695; CHECK: # %bb.0:696; CHECK-NEXT: li a1, -1697; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma698; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t699; CHECK-NEXT: ret700 %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)701 ret <16 x i16> %v702}703 704define <16 x i16> @vssub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {705; CHECK-LABEL: vssub_vi_v16i16_unmasked:706; CHECK: # %bb.0:707; CHECK-NEXT: li a1, -1708; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma709; CHECK-NEXT: vssub.vx v8, v8, a1710; CHECK-NEXT: ret711 %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)712 ret <16 x i16> %v713}714 715define <2 x i32> @vssub_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {716; CHECK-LABEL: vssub_vv_v2i32:717; CHECK: # %bb.0:718; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma719; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t720; CHECK-NEXT: ret721 %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)722 ret <2 x i32> %v723}724 725define <2 x i32> @vssub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {726; CHECK-LABEL: vssub_vv_v2i32_unmasked:727; CHECK: # %bb.0:728; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma729; CHECK-NEXT: vssub.vv v8, v8, v9730; CHECK-NEXT: ret731 %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)732 ret <2 x i32> %v733}734 735define <2 x i32> @vssub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vssub_vx_v2i32:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma739; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t740; CHECK-NEXT: ret741 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0742 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer743 %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)744 ret <2 x i32> %v745}746 747define <2 x i32> @vssub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {748; CHECK-LABEL: vssub_vx_v2i32_unmasked:749; CHECK: # %bb.0:750; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma751; CHECK-NEXT: vssub.vx v8, v8, a0752; CHECK-NEXT: ret753 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0754 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer755 %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)756 ret <2 x i32> %v757}758 759define <2 x i32> @vssub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {760; CHECK-LABEL: vssub_vi_v2i32:761; CHECK: # %bb.0:762; CHECK-NEXT: li a1, -1763; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma764; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t765; CHECK-NEXT: ret766 %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)767 ret <2 x i32> %v768}769 770define <2 x i32> @vssub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {771; CHECK-LABEL: vssub_vi_v2i32_unmasked:772; CHECK: # %bb.0:773; CHECK-NEXT: li a1, -1774; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma775; CHECK-NEXT: vssub.vx v8, v8, a1776; CHECK-NEXT: ret777 %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)778 ret <2 x i32> %v779}780 781define <4 x i32> @vssub_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {782; CHECK-LABEL: vssub_vv_v4i32:783; CHECK: # %bb.0:784; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma785; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t786; CHECK-NEXT: ret787 %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)788 ret <4 x i32> %v789}790 791define <4 x i32> @vssub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {792; CHECK-LABEL: vssub_vv_v4i32_unmasked:793; CHECK: # %bb.0:794; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma795; CHECK-NEXT: vssub.vv v8, v8, v9796; CHECK-NEXT: ret797 %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)798 ret <4 x i32> %v799}800 801define <4 x i32> @vssub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {802; CHECK-LABEL: vssub_vx_v4i32:803; CHECK: # %bb.0:804; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma805; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t806; CHECK-NEXT: ret807 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0808 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer809 %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)810 ret <4 x i32> %v811}812 813define <4 x i32> @vssub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {814; CHECK-LABEL: vssub_vx_v4i32_unmasked:815; CHECK: # %bb.0:816; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma817; CHECK-NEXT: vssub.vx v8, v8, a0818; CHECK-NEXT: ret819 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0820 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer821 %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)822 ret <4 x i32> %v823}824 825define <4 x i32> @vssub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {826; CHECK-LABEL: vssub_vi_v4i32:827; CHECK: # %bb.0:828; CHECK-NEXT: li a1, -1829; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma830; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t831; CHECK-NEXT: ret832 %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)833 ret <4 x i32> %v834}835 836define <4 x i32> @vssub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {837; CHECK-LABEL: vssub_vi_v4i32_unmasked:838; CHECK: # %bb.0:839; CHECK-NEXT: li a1, -1840; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma841; CHECK-NEXT: vssub.vx v8, v8, a1842; CHECK-NEXT: ret843 %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)844 ret <4 x i32> %v845}846 847define <8 x i32> @vssub_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {848; CHECK-LABEL: vssub_vv_v8i32:849; CHECK: # %bb.0:850; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma851; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t852; CHECK-NEXT: ret853 %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)854 ret <8 x i32> %v855}856 857define <8 x i32> @vssub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {858; CHECK-LABEL: vssub_vv_v8i32_unmasked:859; CHECK: # %bb.0:860; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma861; CHECK-NEXT: vssub.vv v8, v8, v10862; CHECK-NEXT: ret863 %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)864 ret <8 x i32> %v865}866 867define <8 x i32> @vssub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {868; CHECK-LABEL: vssub_vx_v8i32:869; CHECK: # %bb.0:870; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma871; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t872; CHECK-NEXT: ret873 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0874 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer875 %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)876 ret <8 x i32> %v877}878 879define <8 x i32> @vssub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {880; CHECK-LABEL: vssub_vx_v8i32_unmasked:881; CHECK: # %bb.0:882; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma883; CHECK-NEXT: vssub.vx v8, v8, a0884; CHECK-NEXT: ret885 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0886 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer887 %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)888 ret <8 x i32> %v889}890 891define <8 x i32> @vssub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {892; CHECK-LABEL: vssub_vi_v8i32:893; CHECK: # %bb.0:894; CHECK-NEXT: li a1, -1895; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma896; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t897; CHECK-NEXT: ret898 %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)899 ret <8 x i32> %v900}901 902define <8 x i32> @vssub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {903; CHECK-LABEL: vssub_vi_v8i32_unmasked:904; CHECK: # %bb.0:905; CHECK-NEXT: li a1, -1906; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma907; CHECK-NEXT: vssub.vx v8, v8, a1908; CHECK-NEXT: ret909 %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)910 ret <8 x i32> %v911}912 913define <16 x i32> @vssub_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {914; CHECK-LABEL: vssub_vv_v16i32:915; CHECK: # %bb.0:916; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma917; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t918; CHECK-NEXT: ret919 %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)920 ret <16 x i32> %v921}922 923define <16 x i32> @vssub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {924; CHECK-LABEL: vssub_vv_v16i32_unmasked:925; CHECK: # %bb.0:926; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma927; CHECK-NEXT: vssub.vv v8, v8, v12928; CHECK-NEXT: ret929 %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)930 ret <16 x i32> %v931}932 933define <16 x i32> @vssub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {934; CHECK-LABEL: vssub_vx_v16i32:935; CHECK: # %bb.0:936; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma937; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t938; CHECK-NEXT: ret939 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0940 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer941 %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)942 ret <16 x i32> %v943}944 945define <16 x i32> @vssub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {946; CHECK-LABEL: vssub_vx_v16i32_unmasked:947; CHECK: # %bb.0:948; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma949; CHECK-NEXT: vssub.vx v8, v8, a0950; CHECK-NEXT: ret951 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0952 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer953 %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)954 ret <16 x i32> %v955}956 957define <16 x i32> @vssub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {958; CHECK-LABEL: vssub_vi_v16i32:959; CHECK: # %bb.0:960; CHECK-NEXT: li a1, -1961; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma962; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t963; CHECK-NEXT: ret964 %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)965 ret <16 x i32> %v966}967 968define <16 x i32> @vssub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {969; CHECK-LABEL: vssub_vi_v16i32_unmasked:970; CHECK: # %bb.0:971; CHECK-NEXT: li a1, -1972; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma973; CHECK-NEXT: vssub.vx v8, v8, a1974; CHECK-NEXT: ret975 %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)976 ret <16 x i32> %v977}978 979define <2 x i64> @vssub_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {980; CHECK-LABEL: vssub_vv_v2i64:981; CHECK: # %bb.0:982; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma983; CHECK-NEXT: vssub.vv v8, v8, v9, v0.t984; CHECK-NEXT: ret985 %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)986 ret <2 x i64> %v987}988 989define <2 x i64> @vssub_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {990; CHECK-LABEL: vssub_vv_v2i64_unmasked:991; CHECK: # %bb.0:992; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma993; CHECK-NEXT: vssub.vv v8, v8, v9994; CHECK-NEXT: ret995 %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)996 ret <2 x i64> %v997}998 999define <2 x i64> @vssub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {1000; RV32-LABEL: vssub_vx_v2i64:1001; RV32: # %bb.0:1002; RV32-NEXT: addi sp, sp, -161003; RV32-NEXT: .cfi_def_cfa_offset 161004; RV32-NEXT: sw a0, 8(sp)1005; RV32-NEXT: sw a1, 12(sp)1006; RV32-NEXT: addi a0, sp, 81007; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1008; RV32-NEXT: vlse64.v v9, (a0), zero1009; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1010; RV32-NEXT: vssub.vv v8, v8, v9, v0.t1011; RV32-NEXT: addi sp, sp, 161012; RV32-NEXT: .cfi_def_cfa_offset 01013; RV32-NEXT: ret1014;1015; RV64-LABEL: vssub_vx_v2i64:1016; RV64: # %bb.0:1017; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1018; RV64-NEXT: vssub.vx v8, v8, a0, v0.t1019; RV64-NEXT: ret1020 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01021 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1022 %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)1023 ret <2 x i64> %v1024}1025 1026define <2 x i64> @vssub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {1027; RV32-LABEL: vssub_vx_v2i64_unmasked:1028; RV32: # %bb.0:1029; RV32-NEXT: addi sp, sp, -161030; RV32-NEXT: .cfi_def_cfa_offset 161031; RV32-NEXT: sw a0, 8(sp)1032; RV32-NEXT: sw a1, 12(sp)1033; RV32-NEXT: addi a0, sp, 81034; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1035; RV32-NEXT: vlse64.v v9, (a0), zero1036; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1037; RV32-NEXT: vssub.vv v8, v8, v91038; RV32-NEXT: addi sp, sp, 161039; RV32-NEXT: .cfi_def_cfa_offset 01040; RV32-NEXT: ret1041;1042; RV64-LABEL: vssub_vx_v2i64_unmasked:1043; RV64: # %bb.0:1044; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1045; RV64-NEXT: vssub.vx v8, v8, a01046; RV64-NEXT: ret1047 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01048 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1049 %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)1050 ret <2 x i64> %v1051}1052 1053define <2 x i64> @vssub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {1054; CHECK-LABEL: vssub_vi_v2i64:1055; CHECK: # %bb.0:1056; CHECK-NEXT: li a1, -11057; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1058; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t1059; CHECK-NEXT: ret1060 %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)1061 ret <2 x i64> %v1062}1063 1064define <2 x i64> @vssub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {1065; CHECK-LABEL: vssub_vi_v2i64_unmasked:1066; CHECK: # %bb.0:1067; CHECK-NEXT: li a1, -11068; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1069; CHECK-NEXT: vssub.vx v8, v8, a11070; CHECK-NEXT: ret1071 %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)1072 ret <2 x i64> %v1073}1074 1075define <4 x i64> @vssub_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {1076; CHECK-LABEL: vssub_vv_v4i64:1077; CHECK: # %bb.0:1078; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1079; CHECK-NEXT: vssub.vv v8, v8, v10, v0.t1080; CHECK-NEXT: ret1081 %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)1082 ret <4 x i64> %v1083}1084 1085define <4 x i64> @vssub_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {1086; CHECK-LABEL: vssub_vv_v4i64_unmasked:1087; CHECK: # %bb.0:1088; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1089; CHECK-NEXT: vssub.vv v8, v8, v101090; CHECK-NEXT: ret1091 %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)1092 ret <4 x i64> %v1093}1094 1095define <4 x i64> @vssub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {1096; RV32-LABEL: vssub_vx_v4i64:1097; RV32: # %bb.0:1098; RV32-NEXT: addi sp, sp, -161099; RV32-NEXT: .cfi_def_cfa_offset 161100; RV32-NEXT: sw a0, 8(sp)1101; RV32-NEXT: sw a1, 12(sp)1102; RV32-NEXT: addi a0, sp, 81103; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1104; RV32-NEXT: vlse64.v v10, (a0), zero1105; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1106; RV32-NEXT: vssub.vv v8, v8, v10, v0.t1107; RV32-NEXT: addi sp, sp, 161108; RV32-NEXT: .cfi_def_cfa_offset 01109; RV32-NEXT: ret1110;1111; RV64-LABEL: vssub_vx_v4i64:1112; RV64: # %bb.0:1113; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1114; RV64-NEXT: vssub.vx v8, v8, a0, v0.t1115; RV64-NEXT: ret1116 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01117 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1118 %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)1119 ret <4 x i64> %v1120}1121 1122define <4 x i64> @vssub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {1123; RV32-LABEL: vssub_vx_v4i64_unmasked:1124; RV32: # %bb.0:1125; RV32-NEXT: addi sp, sp, -161126; RV32-NEXT: .cfi_def_cfa_offset 161127; RV32-NEXT: sw a0, 8(sp)1128; RV32-NEXT: sw a1, 12(sp)1129; RV32-NEXT: addi a0, sp, 81130; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1131; RV32-NEXT: vlse64.v v10, (a0), zero1132; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1133; RV32-NEXT: vssub.vv v8, v8, v101134; RV32-NEXT: addi sp, sp, 161135; RV32-NEXT: .cfi_def_cfa_offset 01136; RV32-NEXT: ret1137;1138; RV64-LABEL: vssub_vx_v4i64_unmasked:1139; RV64: # %bb.0:1140; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1141; RV64-NEXT: vssub.vx v8, v8, a01142; RV64-NEXT: ret1143 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01144 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1145 %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)1146 ret <4 x i64> %v1147}1148 1149define <4 x i64> @vssub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1150; CHECK-LABEL: vssub_vi_v4i64:1151; CHECK: # %bb.0:1152; CHECK-NEXT: li a1, -11153; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1154; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t1155; CHECK-NEXT: ret1156 %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)1157 ret <4 x i64> %v1158}1159 1160define <4 x i64> @vssub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1161; CHECK-LABEL: vssub_vi_v4i64_unmasked:1162; CHECK: # %bb.0:1163; CHECK-NEXT: li a1, -11164; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1165; CHECK-NEXT: vssub.vx v8, v8, a11166; CHECK-NEXT: ret1167 %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)1168 ret <4 x i64> %v1169}1170 1171define <8 x i64> @vssub_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {1172; CHECK-LABEL: vssub_vv_v8i64:1173; CHECK: # %bb.0:1174; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1175; CHECK-NEXT: vssub.vv v8, v8, v12, v0.t1176; CHECK-NEXT: ret1177 %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)1178 ret <8 x i64> %v1179}1180 1181define <8 x i64> @vssub_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {1182; CHECK-LABEL: vssub_vv_v8i64_unmasked:1183; CHECK: # %bb.0:1184; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1185; CHECK-NEXT: vssub.vv v8, v8, v121186; CHECK-NEXT: ret1187 %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)1188 ret <8 x i64> %v1189}1190 1191define <8 x i64> @vssub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {1192; RV32-LABEL: vssub_vx_v8i64:1193; RV32: # %bb.0:1194; RV32-NEXT: addi sp, sp, -161195; RV32-NEXT: .cfi_def_cfa_offset 161196; RV32-NEXT: sw a0, 8(sp)1197; RV32-NEXT: sw a1, 12(sp)1198; RV32-NEXT: addi a0, sp, 81199; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1200; RV32-NEXT: vlse64.v v12, (a0), zero1201; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1202; RV32-NEXT: vssub.vv v8, v8, v12, v0.t1203; RV32-NEXT: addi sp, sp, 161204; RV32-NEXT: .cfi_def_cfa_offset 01205; RV32-NEXT: ret1206;1207; RV64-LABEL: vssub_vx_v8i64:1208; RV64: # %bb.0:1209; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1210; RV64-NEXT: vssub.vx v8, v8, a0, v0.t1211; RV64-NEXT: ret1212 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01213 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1214 %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)1215 ret <8 x i64> %v1216}1217 1218define <8 x i64> @vssub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {1219; RV32-LABEL: vssub_vx_v8i64_unmasked:1220; RV32: # %bb.0:1221; RV32-NEXT: addi sp, sp, -161222; RV32-NEXT: .cfi_def_cfa_offset 161223; RV32-NEXT: sw a0, 8(sp)1224; RV32-NEXT: sw a1, 12(sp)1225; RV32-NEXT: addi a0, sp, 81226; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1227; RV32-NEXT: vlse64.v v12, (a0), zero1228; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1229; RV32-NEXT: vssub.vv v8, v8, v121230; RV32-NEXT: addi sp, sp, 161231; RV32-NEXT: .cfi_def_cfa_offset 01232; RV32-NEXT: ret1233;1234; RV64-LABEL: vssub_vx_v8i64_unmasked:1235; RV64: # %bb.0:1236; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1237; RV64-NEXT: vssub.vx v8, v8, a01238; RV64-NEXT: ret1239 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01240 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1241 %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)1242 ret <8 x i64> %v1243}1244 1245define <8 x i64> @vssub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1246; CHECK-LABEL: vssub_vi_v8i64:1247; CHECK: # %bb.0:1248; CHECK-NEXT: li a1, -11249; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1250; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t1251; CHECK-NEXT: ret1252 %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)1253 ret <8 x i64> %v1254}1255 1256define <8 x i64> @vssub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1257; CHECK-LABEL: vssub_vi_v8i64_unmasked:1258; CHECK: # %bb.0:1259; CHECK-NEXT: li a1, -11260; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1261; CHECK-NEXT: vssub.vx v8, v8, a11262; CHECK-NEXT: ret1263 %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)1264 ret <8 x i64> %v1265}1266 1267define <16 x i64> @vssub_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {1268; CHECK-LABEL: vssub_vv_v16i64:1269; CHECK: # %bb.0:1270; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1271; CHECK-NEXT: vssub.vv v8, v8, v16, v0.t1272; CHECK-NEXT: ret1273 %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)1274 ret <16 x i64> %v1275}1276 1277define <16 x i64> @vssub_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {1278; CHECK-LABEL: vssub_vv_v16i64_unmasked:1279; CHECK: # %bb.0:1280; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1281; CHECK-NEXT: vssub.vv v8, v8, v161282; CHECK-NEXT: ret1283 %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)1284 ret <16 x i64> %v1285}1286 1287define <16 x i64> @vssub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {1288; RV32-LABEL: vssub_vx_v16i64:1289; RV32: # %bb.0:1290; RV32-NEXT: addi sp, sp, -161291; RV32-NEXT: .cfi_def_cfa_offset 161292; RV32-NEXT: sw a0, 8(sp)1293; RV32-NEXT: sw a1, 12(sp)1294; RV32-NEXT: addi a0, sp, 81295; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1296; RV32-NEXT: vlse64.v v16, (a0), zero1297; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1298; RV32-NEXT: vssub.vv v8, v8, v16, v0.t1299; RV32-NEXT: addi sp, sp, 161300; RV32-NEXT: .cfi_def_cfa_offset 01301; RV32-NEXT: ret1302;1303; RV64-LABEL: vssub_vx_v16i64:1304; RV64: # %bb.0:1305; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1306; RV64-NEXT: vssub.vx v8, v8, a0, v0.t1307; RV64-NEXT: ret1308 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01309 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1310 %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)1311 ret <16 x i64> %v1312}1313 1314define <16 x i64> @vssub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {1315; RV32-LABEL: vssub_vx_v16i64_unmasked:1316; RV32: # %bb.0:1317; RV32-NEXT: addi sp, sp, -161318; RV32-NEXT: .cfi_def_cfa_offset 161319; RV32-NEXT: sw a0, 8(sp)1320; RV32-NEXT: sw a1, 12(sp)1321; RV32-NEXT: addi a0, sp, 81322; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1323; RV32-NEXT: vlse64.v v16, (a0), zero1324; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1325; RV32-NEXT: vssub.vv v8, v8, v161326; RV32-NEXT: addi sp, sp, 161327; RV32-NEXT: .cfi_def_cfa_offset 01328; RV32-NEXT: ret1329;1330; RV64-LABEL: vssub_vx_v16i64_unmasked:1331; RV64: # %bb.0:1332; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1333; RV64-NEXT: vssub.vx v8, v8, a01334; RV64-NEXT: ret1335 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01336 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1337 %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)1338 ret <16 x i64> %v1339}1340 1341define <16 x i64> @vssub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1342; CHECK-LABEL: vssub_vi_v16i64:1343; CHECK: # %bb.0:1344; CHECK-NEXT: li a1, -11345; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1346; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t1347; CHECK-NEXT: ret1348 %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)1349 ret <16 x i64> %v1350}1351 1352define <16 x i64> @vssub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1353; CHECK-LABEL: vssub_vi_v16i64_unmasked:1354; CHECK: # %bb.0:1355; CHECK-NEXT: li a1, -11356; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1357; CHECK-NEXT: vssub.vx v8, v8, a11358; CHECK-NEXT: ret1359 %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)1360 ret <16 x i64> %v1361}1362 1363; Test that split-legalization works as expected.1364 1365define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1366; CHECK-LABEL: vssub_vx_v32i64:1367; CHECK: # %bb.0:1368; CHECK-NEXT: li a2, 161369; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1370; CHECK-NEXT: vslidedown.vi v24, v0, 21371; CHECK-NEXT: mv a1, a01372; CHECK-NEXT: bltu a0, a2, .LBB108_21373; CHECK-NEXT: # %bb.1:1374; CHECK-NEXT: li a1, 161375; CHECK-NEXT: .LBB108_2:1376; CHECK-NEXT: li a2, -11377; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1378; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t1379; CHECK-NEXT: addi a1, a0, -161380; CHECK-NEXT: sltu a0, a0, a11381; CHECK-NEXT: addi a0, a0, -11382; CHECK-NEXT: and a0, a0, a11383; CHECK-NEXT: vmv1r.v v0, v241384; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1385; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t1386; CHECK-NEXT: ret1387 %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)1388 ret <32 x i64> %v1389}1390 1391define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1392; CHECK-LABEL: vssub_vi_v32i64_unmasked:1393; CHECK: # %bb.0:1394; CHECK-NEXT: li a2, 161395; CHECK-NEXT: mv a1, a01396; CHECK-NEXT: bltu a0, a2, .LBB109_21397; CHECK-NEXT: # %bb.1:1398; CHECK-NEXT: li a1, 161399; CHECK-NEXT: .LBB109_2:1400; CHECK-NEXT: li a2, -11401; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1402; CHECK-NEXT: vssub.vx v8, v8, a21403; CHECK-NEXT: addi a1, a0, -161404; CHECK-NEXT: sltu a0, a0, a11405; CHECK-NEXT: addi a0, a0, -11406; CHECK-NEXT: and a0, a0, a11407; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1408; CHECK-NEXT: vssub.vx v16, v16, a21409; CHECK-NEXT: ret1410 %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)1411 ret <32 x i64> %v1412}1413 1414define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {1415; CHECK-LABEL: vssub_vx_v32i64_evl12:1416; CHECK: # %bb.0:1417; CHECK-NEXT: li a0, -11418; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma1419; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t1420; CHECK-NEXT: ret1421 %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)1422 ret <32 x i64> %v1423}1424 1425define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {1426; CHECK-LABEL: vssub_vx_v32i64_evl27:1427; CHECK: # %bb.0:1428; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1429; CHECK-NEXT: vslidedown.vi v24, v0, 21430; CHECK-NEXT: li a0, -11431; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1432; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t1433; CHECK-NEXT: vmv1r.v v0, v241434; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma1435; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t1436; CHECK-NEXT: ret1437 %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)1438 ret <32 x i64> %v1439}1440