1435 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <8 x i7> @vssubu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vssubu_vv_v8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: li a1, 12711; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma12; CHECK-NEXT: vand.vx v9, v9, a113; CHECK-NEXT: vand.vx v8, v8, a114; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma15; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t16; CHECK-NEXT: ret17 %v = call <8 x i7> @llvm.vp.usub.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)18 ret <8 x i7> %v19}20 21define <2 x i8> @vssubu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: vssubu_vv_v2i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma25; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t26; CHECK-NEXT: ret27 %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)28 ret <2 x i8> %v29}30 31define <2 x i8> @vssubu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {32; CHECK-LABEL: vssubu_vv_v2i8_unmasked:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma35; CHECK-NEXT: vssubu.vv v8, v8, v936; CHECK-NEXT: ret37 %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)38 ret <2 x i8> %v39}40 41define <2 x i8> @vssubu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {42; CHECK-LABEL: vssubu_vx_v2i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma45; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t46; CHECK-NEXT: ret47 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 048 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer49 %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)50 ret <2 x i8> %v51}52 53define <2 x i8> @vssubu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {54; CHECK-LABEL: vssubu_vx_v2i8_unmasked:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma57; CHECK-NEXT: vssubu.vx v8, v8, a058; CHECK-NEXT: ret59 %elt.head = insertelement <2 x i8> poison, i8 %b, i32 060 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer61 %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)62 ret <2 x i8> %v63}64 65define <2 x i8> @vssubu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {66; CHECK-LABEL: vssubu_vi_v2i8:67; CHECK: # %bb.0:68; CHECK-NEXT: li a1, -169; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma70; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t71; CHECK-NEXT: ret72 %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)73 ret <2 x i8> %v74}75 76define <2 x i8> @vssubu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {77; CHECK-LABEL: vssubu_vi_v2i8_unmasked:78; CHECK: # %bb.0:79; CHECK-NEXT: li a1, -180; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma81; CHECK-NEXT: vssubu.vx v8, v8, a182; CHECK-NEXT: ret83 %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)84 ret <2 x i8> %v85}86 87define <4 x i8> @vssubu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {88; CHECK-LABEL: vssubu_vv_v4i8:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma91; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t92; CHECK-NEXT: ret93 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)94 ret <4 x i8> %v95}96 97define <4 x i8> @vssubu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {98; CHECK-LABEL: vssubu_vv_v4i8_unmasked:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma101; CHECK-NEXT: vssubu.vv v8, v8, v9102; CHECK-NEXT: ret103 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)104 ret <4 x i8> %v105}106 107define <4 x i8> @vssubu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {108; CHECK-LABEL: vssubu_vx_v4i8:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma111; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t112; CHECK-NEXT: ret113 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0114 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer115 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)116 ret <4 x i8> %v117}118 119define <4 x i8> @vssubu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vssubu_vx_v4i8_commute:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma123; CHECK-NEXT: vmv.v.x v9, a0124; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma125; CHECK-NEXT: vssubu.vv v8, v9, v8, v0.t126; CHECK-NEXT: ret127 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0128 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer129 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)130 ret <4 x i8> %v131}132 133define <4 x i8> @vssubu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {134; CHECK-LABEL: vssubu_vx_v4i8_unmasked:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma137; CHECK-NEXT: vssubu.vx v8, v8, a0138; CHECK-NEXT: ret139 %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0140 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer141 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)142 ret <4 x i8> %v143}144 145define <4 x i8> @vssubu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {146; CHECK-LABEL: vssubu_vi_v4i8:147; CHECK: # %bb.0:148; CHECK-NEXT: li a1, -1149; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma150; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t151; CHECK-NEXT: ret152 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)153 ret <4 x i8> %v154}155 156define <4 x i8> @vssubu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {157; CHECK-LABEL: vssubu_vi_v4i8_unmasked:158; CHECK: # %bb.0:159; CHECK-NEXT: li a1, -1160; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma161; CHECK-NEXT: vssubu.vx v8, v8, a1162; CHECK-NEXT: ret163 %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)164 ret <4 x i8> %v165}166 167define <5 x i8> @vssubu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {168; CHECK-LABEL: vssubu_vv_v5i8:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma171; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t172; CHECK-NEXT: ret173 %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)174 ret <5 x i8> %v175}176 177define <5 x i8> @vssubu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {178; CHECK-LABEL: vssubu_vv_v5i8_unmasked:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma181; CHECK-NEXT: vssubu.vv v8, v8, v9182; CHECK-NEXT: ret183 %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)184 ret <5 x i8> %v185}186 187define <5 x i8> @vssubu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {188; CHECK-LABEL: vssubu_vx_v5i8:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma191; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t192; CHECK-NEXT: ret193 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0194 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer195 %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)196 ret <5 x i8> %v197}198 199define <5 x i8> @vssubu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {200; CHECK-LABEL: vssubu_vx_v5i8_unmasked:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma203; CHECK-NEXT: vssubu.vx v8, v8, a0204; CHECK-NEXT: ret205 %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0206 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer207 %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)208 ret <5 x i8> %v209}210 211define <5 x i8> @vssubu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {212; CHECK-LABEL: vssubu_vi_v5i8:213; CHECK: # %bb.0:214; CHECK-NEXT: li a1, -1215; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma216; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t217; CHECK-NEXT: ret218 %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)219 ret <5 x i8> %v220}221 222define <5 x i8> @vssubu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {223; CHECK-LABEL: vssubu_vi_v5i8_unmasked:224; CHECK: # %bb.0:225; CHECK-NEXT: li a1, -1226; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma227; CHECK-NEXT: vssubu.vx v8, v8, a1228; CHECK-NEXT: ret229 %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)230 ret <5 x i8> %v231}232 233define <8 x i8> @vssubu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {234; CHECK-LABEL: vssubu_vv_v8i8:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma237; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t238; CHECK-NEXT: ret239 %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)240 ret <8 x i8> %v241}242 243define <8 x i8> @vssubu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {244; CHECK-LABEL: vssubu_vv_v8i8_unmasked:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma247; CHECK-NEXT: vssubu.vv v8, v8, v9248; CHECK-NEXT: ret249 %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)250 ret <8 x i8> %v251}252 253define <8 x i8> @vssubu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {254; CHECK-LABEL: vssubu_vx_v8i8:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma257; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t258; CHECK-NEXT: ret259 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0260 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer261 %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)262 ret <8 x i8> %v263}264 265define <8 x i8> @vssubu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {266; CHECK-LABEL: vssubu_vx_v8i8_unmasked:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma269; CHECK-NEXT: vssubu.vx v8, v8, a0270; CHECK-NEXT: ret271 %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0272 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer273 %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)274 ret <8 x i8> %v275}276 277define <8 x i8> @vssubu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {278; CHECK-LABEL: vssubu_vi_v8i8:279; CHECK: # %bb.0:280; CHECK-NEXT: li a1, -1281; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma282; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t283; CHECK-NEXT: ret284 %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)285 ret <8 x i8> %v286}287 288define <8 x i8> @vssubu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {289; CHECK-LABEL: vssubu_vi_v8i8_unmasked:290; CHECK: # %bb.0:291; CHECK-NEXT: li a1, -1292; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma293; CHECK-NEXT: vssubu.vx v8, v8, a1294; CHECK-NEXT: ret295 %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)296 ret <8 x i8> %v297}298 299define <16 x i8> @vssubu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {300; CHECK-LABEL: vssubu_vv_v16i8:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma303; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t304; CHECK-NEXT: ret305 %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)306 ret <16 x i8> %v307}308 309define <16 x i8> @vssubu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {310; CHECK-LABEL: vssubu_vv_v16i8_unmasked:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma313; CHECK-NEXT: vssubu.vv v8, v8, v9314; CHECK-NEXT: ret315 %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)316 ret <16 x i8> %v317}318 319define <16 x i8> @vssubu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {320; CHECK-LABEL: vssubu_vx_v16i8:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma323; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t324; CHECK-NEXT: ret325 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0326 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer327 %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)328 ret <16 x i8> %v329}330 331define <16 x i8> @vssubu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {332; CHECK-LABEL: vssubu_vx_v16i8_unmasked:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma335; CHECK-NEXT: vssubu.vx v8, v8, a0336; CHECK-NEXT: ret337 %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0338 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer339 %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)340 ret <16 x i8> %v341}342 343define <16 x i8> @vssubu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {344; CHECK-LABEL: vssubu_vi_v16i8:345; CHECK: # %bb.0:346; CHECK-NEXT: li a1, -1347; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma348; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t349; CHECK-NEXT: ret350 %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)351 ret <16 x i8> %v352}353 354define <16 x i8> @vssubu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {355; CHECK-LABEL: vssubu_vi_v16i8_unmasked:356; CHECK: # %bb.0:357; CHECK-NEXT: li a1, -1358; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma359; CHECK-NEXT: vssubu.vx v8, v8, a1360; CHECK-NEXT: ret361 %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)362 ret <16 x i8> %v363}364 365define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {366; CHECK-LABEL: vssubu_vi_v258i8:367; CHECK: # %bb.0:368; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma369; CHECK-NEXT: vmv1r.v v24, v0370; CHECK-NEXT: li a2, 128371; CHECK-NEXT: addi a3, a1, -128372; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma373; CHECK-NEXT: vlm.v v0, (a0)374; CHECK-NEXT: sltu a0, a1, a3375; CHECK-NEXT: addi a0, a0, -1376; CHECK-NEXT: and a3, a0, a3377; CHECK-NEXT: li a0, -1378; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma379; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t380; CHECK-NEXT: bltu a1, a2, .LBB32_2381; CHECK-NEXT: # %bb.1:382; CHECK-NEXT: li a1, 128383; CHECK-NEXT: .LBB32_2:384; CHECK-NEXT: vmv1r.v v0, v24385; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma386; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t387; CHECK-NEXT: ret388 %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)389 ret <256 x i8> %v390}391 392define <256 x i8> @vssubu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {393; CHECK-LABEL: vssubu_vi_v258i8_unmasked:394; CHECK: # %bb.0:395; CHECK-NEXT: li a2, 128396; CHECK-NEXT: mv a1, a0397; CHECK-NEXT: bltu a0, a2, .LBB33_2398; CHECK-NEXT: # %bb.1:399; CHECK-NEXT: li a1, 128400; CHECK-NEXT: .LBB33_2:401; CHECK-NEXT: li a2, -1402; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma403; CHECK-NEXT: vssubu.vx v8, v8, a2404; CHECK-NEXT: addi a1, a0, -128405; CHECK-NEXT: sltu a0, a0, a1406; CHECK-NEXT: addi a0, a0, -1407; CHECK-NEXT: and a0, a0, a1408; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma409; CHECK-NEXT: vssubu.vx v16, v16, a2410; CHECK-NEXT: ret411 %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)412 ret <256 x i8> %v413}414 415; Test splitting when the %evl is a known constant.416 417define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {418; CHECK-LABEL: vssubu_vi_v258i8_evl129:419; CHECK: # %bb.0:420; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma421; CHECK-NEXT: vlm.v v24, (a0)422; CHECK-NEXT: li a0, 128423; CHECK-NEXT: li a1, -1424; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma425; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t426; CHECK-NEXT: vmv1r.v v0, v24427; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma428; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t429; CHECK-NEXT: ret430 %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)431 ret <256 x i8> %v432}433 434define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {435; CHECK-LABEL: vssubu_vi_v258i8_evl128:436; CHECK: # %bb.0:437; CHECK-NEXT: li a0, 128438; CHECK-NEXT: li a1, -1439; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma440; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t441; CHECK-NEXT: ret442 %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)443 ret <256 x i8> %v444}445 446define <2 x i16> @vssubu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {447; CHECK-LABEL: vssubu_vv_v2i16:448; CHECK: # %bb.0:449; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma450; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t451; CHECK-NEXT: ret452 %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)453 ret <2 x i16> %v454}455 456define <2 x i16> @vssubu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {457; CHECK-LABEL: vssubu_vv_v2i16_unmasked:458; CHECK: # %bb.0:459; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma460; CHECK-NEXT: vssubu.vv v8, v8, v9461; CHECK-NEXT: ret462 %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)463 ret <2 x i16> %v464}465 466define <2 x i16> @vssubu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {467; CHECK-LABEL: vssubu_vx_v2i16:468; CHECK: # %bb.0:469; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma470; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t471; CHECK-NEXT: ret472 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0473 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer474 %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)475 ret <2 x i16> %v476}477 478define <2 x i16> @vssubu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {479; CHECK-LABEL: vssubu_vx_v2i16_unmasked:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma482; CHECK-NEXT: vssubu.vx v8, v8, a0483; CHECK-NEXT: ret484 %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0485 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer486 %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)487 ret <2 x i16> %v488}489 490define <2 x i16> @vssubu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {491; CHECK-LABEL: vssubu_vi_v2i16:492; CHECK: # %bb.0:493; CHECK-NEXT: li a1, -1494; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma495; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t496; CHECK-NEXT: ret497 %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)498 ret <2 x i16> %v499}500 501define <2 x i16> @vssubu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {502; CHECK-LABEL: vssubu_vi_v2i16_unmasked:503; CHECK: # %bb.0:504; CHECK-NEXT: li a1, -1505; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma506; CHECK-NEXT: vssubu.vx v8, v8, a1507; CHECK-NEXT: ret508 %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)509 ret <2 x i16> %v510}511 512define <4 x i16> @vssubu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {513; CHECK-LABEL: vssubu_vv_v4i16:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma516; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t517; CHECK-NEXT: ret518 %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)519 ret <4 x i16> %v520}521 522define <4 x i16> @vssubu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {523; CHECK-LABEL: vssubu_vv_v4i16_unmasked:524; CHECK: # %bb.0:525; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma526; CHECK-NEXT: vssubu.vv v8, v8, v9527; CHECK-NEXT: ret528 %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)529 ret <4 x i16> %v530}531 532define <4 x i16> @vssubu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {533; CHECK-LABEL: vssubu_vx_v4i16:534; CHECK: # %bb.0:535; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma536; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t537; CHECK-NEXT: ret538 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0539 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer540 %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)541 ret <4 x i16> %v542}543 544define <4 x i16> @vssubu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {545; CHECK-LABEL: vssubu_vx_v4i16_unmasked:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma548; CHECK-NEXT: vssubu.vx v8, v8, a0549; CHECK-NEXT: ret550 %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0551 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer552 %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)553 ret <4 x i16> %v554}555 556define <4 x i16> @vssubu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {557; CHECK-LABEL: vssubu_vi_v4i16:558; CHECK: # %bb.0:559; CHECK-NEXT: li a1, -1560; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma561; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t562; CHECK-NEXT: ret563 %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)564 ret <4 x i16> %v565}566 567define <4 x i16> @vssubu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {568; CHECK-LABEL: vssubu_vi_v4i16_unmasked:569; CHECK: # %bb.0:570; CHECK-NEXT: li a1, -1571; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma572; CHECK-NEXT: vssubu.vx v8, v8, a1573; CHECK-NEXT: ret574 %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)575 ret <4 x i16> %v576}577 578define <8 x i16> @vssubu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {579; CHECK-LABEL: vssubu_vv_v8i16:580; CHECK: # %bb.0:581; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma582; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t583; CHECK-NEXT: ret584 %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)585 ret <8 x i16> %v586}587 588define <8 x i16> @vssubu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {589; CHECK-LABEL: vssubu_vv_v8i16_unmasked:590; CHECK: # %bb.0:591; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma592; CHECK-NEXT: vssubu.vv v8, v8, v9593; CHECK-NEXT: ret594 %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)595 ret <8 x i16> %v596}597 598define <8 x i16> @vssubu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {599; CHECK-LABEL: vssubu_vx_v8i16:600; CHECK: # %bb.0:601; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma602; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t603; CHECK-NEXT: ret604 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0605 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer606 %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)607 ret <8 x i16> %v608}609 610define <8 x i16> @vssubu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {611; CHECK-LABEL: vssubu_vx_v8i16_unmasked:612; CHECK: # %bb.0:613; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma614; CHECK-NEXT: vssubu.vx v8, v8, a0615; CHECK-NEXT: ret616 %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0617 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer618 %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)619 ret <8 x i16> %v620}621 622define <8 x i16> @vssubu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {623; CHECK-LABEL: vssubu_vi_v8i16:624; CHECK: # %bb.0:625; CHECK-NEXT: li a1, -1626; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma627; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t628; CHECK-NEXT: ret629 %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)630 ret <8 x i16> %v631}632 633define <8 x i16> @vssubu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {634; CHECK-LABEL: vssubu_vi_v8i16_unmasked:635; CHECK: # %bb.0:636; CHECK-NEXT: li a1, -1637; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma638; CHECK-NEXT: vssubu.vx v8, v8, a1639; CHECK-NEXT: ret640 %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)641 ret <8 x i16> %v642}643 644define <16 x i16> @vssubu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {645; CHECK-LABEL: vssubu_vv_v16i16:646; CHECK: # %bb.0:647; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma648; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t649; CHECK-NEXT: ret650 %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)651 ret <16 x i16> %v652}653 654define <16 x i16> @vssubu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {655; CHECK-LABEL: vssubu_vv_v16i16_unmasked:656; CHECK: # %bb.0:657; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma658; CHECK-NEXT: vssubu.vv v8, v8, v10659; CHECK-NEXT: ret660 %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)661 ret <16 x i16> %v662}663 664define <16 x i16> @vssubu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {665; CHECK-LABEL: vssubu_vx_v16i16:666; CHECK: # %bb.0:667; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma668; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t669; CHECK-NEXT: ret670 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0671 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer672 %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)673 ret <16 x i16> %v674}675 676define <16 x i16> @vssubu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {677; CHECK-LABEL: vssubu_vx_v16i16_unmasked:678; CHECK: # %bb.0:679; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma680; CHECK-NEXT: vssubu.vx v8, v8, a0681; CHECK-NEXT: ret682 %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0683 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer684 %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)685 ret <16 x i16> %v686}687 688define <16 x i16> @vssubu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {689; CHECK-LABEL: vssubu_vi_v16i16:690; CHECK: # %bb.0:691; CHECK-NEXT: li a1, -1692; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma693; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t694; CHECK-NEXT: ret695 %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)696 ret <16 x i16> %v697}698 699define <16 x i16> @vssubu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {700; CHECK-LABEL: vssubu_vi_v16i16_unmasked:701; CHECK: # %bb.0:702; CHECK-NEXT: li a1, -1703; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma704; CHECK-NEXT: vssubu.vx v8, v8, a1705; CHECK-NEXT: ret706 %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)707 ret <16 x i16> %v708}709 710define <2 x i32> @vssubu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {711; CHECK-LABEL: vssubu_vv_v2i32:712; CHECK: # %bb.0:713; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma714; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t715; CHECK-NEXT: ret716 %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)717 ret <2 x i32> %v718}719 720define <2 x i32> @vssubu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {721; CHECK-LABEL: vssubu_vv_v2i32_unmasked:722; CHECK: # %bb.0:723; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma724; CHECK-NEXT: vssubu.vv v8, v8, v9725; CHECK-NEXT: ret726 %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)727 ret <2 x i32> %v728}729 730define <2 x i32> @vssubu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {731; CHECK-LABEL: vssubu_vx_v2i32:732; CHECK: # %bb.0:733; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma734; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t735; CHECK-NEXT: ret736 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0737 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer738 %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)739 ret <2 x i32> %v740}741 742define <2 x i32> @vssubu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {743; CHECK-LABEL: vssubu_vx_v2i32_unmasked:744; CHECK: # %bb.0:745; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma746; CHECK-NEXT: vssubu.vx v8, v8, a0747; CHECK-NEXT: ret748 %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0749 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer750 %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)751 ret <2 x i32> %v752}753 754define <2 x i32> @vssubu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {755; CHECK-LABEL: vssubu_vi_v2i32:756; CHECK: # %bb.0:757; CHECK-NEXT: li a1, -1758; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma759; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t760; CHECK-NEXT: ret761 %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)762 ret <2 x i32> %v763}764 765define <2 x i32> @vssubu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {766; CHECK-LABEL: vssubu_vi_v2i32_unmasked:767; CHECK: # %bb.0:768; CHECK-NEXT: li a1, -1769; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma770; CHECK-NEXT: vssubu.vx v8, v8, a1771; CHECK-NEXT: ret772 %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)773 ret <2 x i32> %v774}775 776define <4 x i32> @vssubu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {777; CHECK-LABEL: vssubu_vv_v4i32:778; CHECK: # %bb.0:779; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma780; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t781; CHECK-NEXT: ret782 %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)783 ret <4 x i32> %v784}785 786define <4 x i32> @vssubu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {787; CHECK-LABEL: vssubu_vv_v4i32_unmasked:788; CHECK: # %bb.0:789; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma790; CHECK-NEXT: vssubu.vv v8, v8, v9791; CHECK-NEXT: ret792 %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)793 ret <4 x i32> %v794}795 796define <4 x i32> @vssubu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {797; CHECK-LABEL: vssubu_vx_v4i32:798; CHECK: # %bb.0:799; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma800; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t801; CHECK-NEXT: ret802 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0803 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer804 %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)805 ret <4 x i32> %v806}807 808define <4 x i32> @vssubu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {809; CHECK-LABEL: vssubu_vx_v4i32_unmasked:810; CHECK: # %bb.0:811; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma812; CHECK-NEXT: vssubu.vx v8, v8, a0813; CHECK-NEXT: ret814 %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0815 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer816 %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)817 ret <4 x i32> %v818}819 820define <4 x i32> @vssubu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {821; CHECK-LABEL: vssubu_vi_v4i32:822; CHECK: # %bb.0:823; CHECK-NEXT: li a1, -1824; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma825; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t826; CHECK-NEXT: ret827 %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)828 ret <4 x i32> %v829}830 831define <4 x i32> @vssubu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {832; CHECK-LABEL: vssubu_vi_v4i32_unmasked:833; CHECK: # %bb.0:834; CHECK-NEXT: li a1, -1835; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma836; CHECK-NEXT: vssubu.vx v8, v8, a1837; CHECK-NEXT: ret838 %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)839 ret <4 x i32> %v840}841 842define <8 x i32> @vssubu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {843; CHECK-LABEL: vssubu_vv_v8i32:844; CHECK: # %bb.0:845; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma846; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t847; CHECK-NEXT: ret848 %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)849 ret <8 x i32> %v850}851 852define <8 x i32> @vssubu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {853; CHECK-LABEL: vssubu_vv_v8i32_unmasked:854; CHECK: # %bb.0:855; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma856; CHECK-NEXT: vssubu.vv v8, v8, v10857; CHECK-NEXT: ret858 %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)859 ret <8 x i32> %v860}861 862define <8 x i32> @vssubu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {863; CHECK-LABEL: vssubu_vx_v8i32:864; CHECK: # %bb.0:865; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma866; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t867; CHECK-NEXT: ret868 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0869 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer870 %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)871 ret <8 x i32> %v872}873 874define <8 x i32> @vssubu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {875; CHECK-LABEL: vssubu_vx_v8i32_unmasked:876; CHECK: # %bb.0:877; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma878; CHECK-NEXT: vssubu.vx v8, v8, a0879; CHECK-NEXT: ret880 %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0881 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer882 %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)883 ret <8 x i32> %v884}885 886define <8 x i32> @vssubu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {887; CHECK-LABEL: vssubu_vi_v8i32:888; CHECK: # %bb.0:889; CHECK-NEXT: li a1, -1890; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma891; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t892; CHECK-NEXT: ret893 %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)894 ret <8 x i32> %v895}896 897define <8 x i32> @vssubu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {898; CHECK-LABEL: vssubu_vi_v8i32_unmasked:899; CHECK: # %bb.0:900; CHECK-NEXT: li a1, -1901; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma902; CHECK-NEXT: vssubu.vx v8, v8, a1903; CHECK-NEXT: ret904 %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)905 ret <8 x i32> %v906}907 908define <16 x i32> @vssubu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {909; CHECK-LABEL: vssubu_vv_v16i32:910; CHECK: # %bb.0:911; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma912; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t913; CHECK-NEXT: ret914 %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)915 ret <16 x i32> %v916}917 918define <16 x i32> @vssubu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {919; CHECK-LABEL: vssubu_vv_v16i32_unmasked:920; CHECK: # %bb.0:921; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma922; CHECK-NEXT: vssubu.vv v8, v8, v12923; CHECK-NEXT: ret924 %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)925 ret <16 x i32> %v926}927 928define <16 x i32> @vssubu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {929; CHECK-LABEL: vssubu_vx_v16i32:930; CHECK: # %bb.0:931; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma932; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t933; CHECK-NEXT: ret934 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0935 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer936 %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)937 ret <16 x i32> %v938}939 940define <16 x i32> @vssubu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {941; CHECK-LABEL: vssubu_vx_v16i32_unmasked:942; CHECK: # %bb.0:943; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma944; CHECK-NEXT: vssubu.vx v8, v8, a0945; CHECK-NEXT: ret946 %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0947 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer948 %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)949 ret <16 x i32> %v950}951 952define <16 x i32> @vssubu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {953; CHECK-LABEL: vssubu_vi_v16i32:954; CHECK: # %bb.0:955; CHECK-NEXT: li a1, -1956; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma957; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t958; CHECK-NEXT: ret959 %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)960 ret <16 x i32> %v961}962 963define <16 x i32> @vssubu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {964; CHECK-LABEL: vssubu_vi_v16i32_unmasked:965; CHECK: # %bb.0:966; CHECK-NEXT: li a1, -1967; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma968; CHECK-NEXT: vssubu.vx v8, v8, a1969; CHECK-NEXT: ret970 %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)971 ret <16 x i32> %v972}973 974define <2 x i64> @vssubu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {975; CHECK-LABEL: vssubu_vv_v2i64:976; CHECK: # %bb.0:977; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma978; CHECK-NEXT: vssubu.vv v8, v8, v9, v0.t979; CHECK-NEXT: ret980 %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)981 ret <2 x i64> %v982}983 984define <2 x i64> @vssubu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {985; CHECK-LABEL: vssubu_vv_v2i64_unmasked:986; CHECK: # %bb.0:987; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma988; CHECK-NEXT: vssubu.vv v8, v8, v9989; CHECK-NEXT: ret990 %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)991 ret <2 x i64> %v992}993 994define <2 x i64> @vssubu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {995; RV32-LABEL: vssubu_vx_v2i64:996; RV32: # %bb.0:997; RV32-NEXT: addi sp, sp, -16998; RV32-NEXT: .cfi_def_cfa_offset 16999; RV32-NEXT: sw a0, 8(sp)1000; RV32-NEXT: sw a1, 12(sp)1001; RV32-NEXT: addi a0, sp, 81002; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1003; RV32-NEXT: vlse64.v v9, (a0), zero1004; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1005; RV32-NEXT: vssubu.vv v8, v8, v9, v0.t1006; RV32-NEXT: addi sp, sp, 161007; RV32-NEXT: .cfi_def_cfa_offset 01008; RV32-NEXT: ret1009;1010; RV64-LABEL: vssubu_vx_v2i64:1011; RV64: # %bb.0:1012; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1013; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t1014; RV64-NEXT: ret1015 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01016 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1017 %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)1018 ret <2 x i64> %v1019}1020 1021define <2 x i64> @vssubu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {1022; RV32-LABEL: vssubu_vx_v2i64_unmasked:1023; RV32: # %bb.0:1024; RV32-NEXT: addi sp, sp, -161025; RV32-NEXT: .cfi_def_cfa_offset 161026; RV32-NEXT: sw a0, 8(sp)1027; RV32-NEXT: sw a1, 12(sp)1028; RV32-NEXT: addi a0, sp, 81029; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma1030; RV32-NEXT: vlse64.v v9, (a0), zero1031; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1032; RV32-NEXT: vssubu.vv v8, v8, v91033; RV32-NEXT: addi sp, sp, 161034; RV32-NEXT: .cfi_def_cfa_offset 01035; RV32-NEXT: ret1036;1037; RV64-LABEL: vssubu_vx_v2i64_unmasked:1038; RV64: # %bb.0:1039; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1040; RV64-NEXT: vssubu.vx v8, v8, a01041; RV64-NEXT: ret1042 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 01043 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer1044 %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)1045 ret <2 x i64> %v1046}1047 1048define <2 x i64> @vssubu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {1049; CHECK-LABEL: vssubu_vi_v2i64:1050; CHECK: # %bb.0:1051; CHECK-NEXT: li a1, -11052; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1053; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t1054; CHECK-NEXT: ret1055 %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)1056 ret <2 x i64> %v1057}1058 1059define <2 x i64> @vssubu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {1060; CHECK-LABEL: vssubu_vi_v2i64_unmasked:1061; CHECK: # %bb.0:1062; CHECK-NEXT: li a1, -11063; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1064; CHECK-NEXT: vssubu.vx v8, v8, a11065; CHECK-NEXT: ret1066 %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)1067 ret <2 x i64> %v1068}1069 1070define <4 x i64> @vssubu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {1071; CHECK-LABEL: vssubu_vv_v4i64:1072; CHECK: # %bb.0:1073; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1074; CHECK-NEXT: vssubu.vv v8, v8, v10, v0.t1075; CHECK-NEXT: ret1076 %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)1077 ret <4 x i64> %v1078}1079 1080define <4 x i64> @vssubu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {1081; CHECK-LABEL: vssubu_vv_v4i64_unmasked:1082; CHECK: # %bb.0:1083; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1084; CHECK-NEXT: vssubu.vv v8, v8, v101085; CHECK-NEXT: ret1086 %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)1087 ret <4 x i64> %v1088}1089 1090define <4 x i64> @vssubu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {1091; RV32-LABEL: vssubu_vx_v4i64:1092; RV32: # %bb.0:1093; RV32-NEXT: addi sp, sp, -161094; RV32-NEXT: .cfi_def_cfa_offset 161095; RV32-NEXT: sw a0, 8(sp)1096; RV32-NEXT: sw a1, 12(sp)1097; RV32-NEXT: addi a0, sp, 81098; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1099; RV32-NEXT: vlse64.v v10, (a0), zero1100; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1101; RV32-NEXT: vssubu.vv v8, v8, v10, v0.t1102; RV32-NEXT: addi sp, sp, 161103; RV32-NEXT: .cfi_def_cfa_offset 01104; RV32-NEXT: ret1105;1106; RV64-LABEL: vssubu_vx_v4i64:1107; RV64: # %bb.0:1108; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1109; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t1110; RV64-NEXT: ret1111 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01112 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1113 %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)1114 ret <4 x i64> %v1115}1116 1117define <4 x i64> @vssubu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {1118; RV32-LABEL: vssubu_vx_v4i64_unmasked:1119; RV32: # %bb.0:1120; RV32-NEXT: addi sp, sp, -161121; RV32-NEXT: .cfi_def_cfa_offset 161122; RV32-NEXT: sw a0, 8(sp)1123; RV32-NEXT: sw a1, 12(sp)1124; RV32-NEXT: addi a0, sp, 81125; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma1126; RV32-NEXT: vlse64.v v10, (a0), zero1127; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1128; RV32-NEXT: vssubu.vv v8, v8, v101129; RV32-NEXT: addi sp, sp, 161130; RV32-NEXT: .cfi_def_cfa_offset 01131; RV32-NEXT: ret1132;1133; RV64-LABEL: vssubu_vx_v4i64_unmasked:1134; RV64: # %bb.0:1135; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1136; RV64-NEXT: vssubu.vx v8, v8, a01137; RV64-NEXT: ret1138 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 01139 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer1140 %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)1141 ret <4 x i64> %v1142}1143 1144define <4 x i64> @vssubu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {1145; CHECK-LABEL: vssubu_vi_v4i64:1146; CHECK: # %bb.0:1147; CHECK-NEXT: li a1, -11148; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1149; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t1150; CHECK-NEXT: ret1151 %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)1152 ret <4 x i64> %v1153}1154 1155define <4 x i64> @vssubu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {1156; CHECK-LABEL: vssubu_vi_v4i64_unmasked:1157; CHECK: # %bb.0:1158; CHECK-NEXT: li a1, -11159; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1160; CHECK-NEXT: vssubu.vx v8, v8, a11161; CHECK-NEXT: ret1162 %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)1163 ret <4 x i64> %v1164}1165 1166define <8 x i64> @vssubu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {1167; CHECK-LABEL: vssubu_vv_v8i64:1168; CHECK: # %bb.0:1169; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1170; CHECK-NEXT: vssubu.vv v8, v8, v12, v0.t1171; CHECK-NEXT: ret1172 %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)1173 ret <8 x i64> %v1174}1175 1176define <8 x i64> @vssubu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {1177; CHECK-LABEL: vssubu_vv_v8i64_unmasked:1178; CHECK: # %bb.0:1179; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1180; CHECK-NEXT: vssubu.vv v8, v8, v121181; CHECK-NEXT: ret1182 %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)1183 ret <8 x i64> %v1184}1185 1186define <8 x i64> @vssubu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {1187; RV32-LABEL: vssubu_vx_v8i64:1188; RV32: # %bb.0:1189; RV32-NEXT: addi sp, sp, -161190; RV32-NEXT: .cfi_def_cfa_offset 161191; RV32-NEXT: sw a0, 8(sp)1192; RV32-NEXT: sw a1, 12(sp)1193; RV32-NEXT: addi a0, sp, 81194; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1195; RV32-NEXT: vlse64.v v12, (a0), zero1196; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1197; RV32-NEXT: vssubu.vv v8, v8, v12, v0.t1198; RV32-NEXT: addi sp, sp, 161199; RV32-NEXT: .cfi_def_cfa_offset 01200; RV32-NEXT: ret1201;1202; RV64-LABEL: vssubu_vx_v8i64:1203; RV64: # %bb.0:1204; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1205; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t1206; RV64-NEXT: ret1207 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01208 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1209 %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)1210 ret <8 x i64> %v1211}1212 1213define <8 x i64> @vssubu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {1214; RV32-LABEL: vssubu_vx_v8i64_unmasked:1215; RV32: # %bb.0:1216; RV32-NEXT: addi sp, sp, -161217; RV32-NEXT: .cfi_def_cfa_offset 161218; RV32-NEXT: sw a0, 8(sp)1219; RV32-NEXT: sw a1, 12(sp)1220; RV32-NEXT: addi a0, sp, 81221; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma1222; RV32-NEXT: vlse64.v v12, (a0), zero1223; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1224; RV32-NEXT: vssubu.vv v8, v8, v121225; RV32-NEXT: addi sp, sp, 161226; RV32-NEXT: .cfi_def_cfa_offset 01227; RV32-NEXT: ret1228;1229; RV64-LABEL: vssubu_vx_v8i64_unmasked:1230; RV64: # %bb.0:1231; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1232; RV64-NEXT: vssubu.vx v8, v8, a01233; RV64-NEXT: ret1234 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 01235 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer1236 %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)1237 ret <8 x i64> %v1238}1239 1240define <8 x i64> @vssubu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {1241; CHECK-LABEL: vssubu_vi_v8i64:1242; CHECK: # %bb.0:1243; CHECK-NEXT: li a1, -11244; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1245; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t1246; CHECK-NEXT: ret1247 %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)1248 ret <8 x i64> %v1249}1250 1251define <8 x i64> @vssubu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {1252; CHECK-LABEL: vssubu_vi_v8i64_unmasked:1253; CHECK: # %bb.0:1254; CHECK-NEXT: li a1, -11255; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1256; CHECK-NEXT: vssubu.vx v8, v8, a11257; CHECK-NEXT: ret1258 %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)1259 ret <8 x i64> %v1260}1261 1262define <16 x i64> @vssubu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {1263; CHECK-LABEL: vssubu_vv_v16i64:1264; CHECK: # %bb.0:1265; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1266; CHECK-NEXT: vssubu.vv v8, v8, v16, v0.t1267; CHECK-NEXT: ret1268 %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)1269 ret <16 x i64> %v1270}1271 1272define <16 x i64> @vssubu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {1273; CHECK-LABEL: vssubu_vv_v16i64_unmasked:1274; CHECK: # %bb.0:1275; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1276; CHECK-NEXT: vssubu.vv v8, v8, v161277; CHECK-NEXT: ret1278 %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)1279 ret <16 x i64> %v1280}1281 1282define <16 x i64> @vssubu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {1283; RV32-LABEL: vssubu_vx_v16i64:1284; RV32: # %bb.0:1285; RV32-NEXT: addi sp, sp, -161286; RV32-NEXT: .cfi_def_cfa_offset 161287; RV32-NEXT: sw a0, 8(sp)1288; RV32-NEXT: sw a1, 12(sp)1289; RV32-NEXT: addi a0, sp, 81290; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1291; RV32-NEXT: vlse64.v v16, (a0), zero1292; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1293; RV32-NEXT: vssubu.vv v8, v8, v16, v0.t1294; RV32-NEXT: addi sp, sp, 161295; RV32-NEXT: .cfi_def_cfa_offset 01296; RV32-NEXT: ret1297;1298; RV64-LABEL: vssubu_vx_v16i64:1299; RV64: # %bb.0:1300; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1301; RV64-NEXT: vssubu.vx v8, v8, a0, v0.t1302; RV64-NEXT: ret1303 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01304 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1305 %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)1306 ret <16 x i64> %v1307}1308 1309define <16 x i64> @vssubu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {1310; RV32-LABEL: vssubu_vx_v16i64_unmasked:1311; RV32: # %bb.0:1312; RV32-NEXT: addi sp, sp, -161313; RV32-NEXT: .cfi_def_cfa_offset 161314; RV32-NEXT: sw a0, 8(sp)1315; RV32-NEXT: sw a1, 12(sp)1316; RV32-NEXT: addi a0, sp, 81317; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma1318; RV32-NEXT: vlse64.v v16, (a0), zero1319; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1320; RV32-NEXT: vssubu.vv v8, v8, v161321; RV32-NEXT: addi sp, sp, 161322; RV32-NEXT: .cfi_def_cfa_offset 01323; RV32-NEXT: ret1324;1325; RV64-LABEL: vssubu_vx_v16i64_unmasked:1326; RV64: # %bb.0:1327; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1328; RV64-NEXT: vssubu.vx v8, v8, a01329; RV64-NEXT: ret1330 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 01331 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer1332 %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)1333 ret <16 x i64> %v1334}1335 1336define <16 x i64> @vssubu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {1337; CHECK-LABEL: vssubu_vi_v16i64:1338; CHECK: # %bb.0:1339; CHECK-NEXT: li a1, -11340; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1341; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t1342; CHECK-NEXT: ret1343 %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)1344 ret <16 x i64> %v1345}1346 1347define <16 x i64> @vssubu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {1348; CHECK-LABEL: vssubu_vi_v16i64_unmasked:1349; CHECK: # %bb.0:1350; CHECK-NEXT: li a1, -11351; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1352; CHECK-NEXT: vssubu.vx v8, v8, a11353; CHECK-NEXT: ret1354 %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)1355 ret <16 x i64> %v1356}1357 1358; Test that split-legalization works as expected.1359 1360define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {1361; CHECK-LABEL: vssubu_vx_v32i64:1362; CHECK: # %bb.0:1363; CHECK-NEXT: li a2, 161364; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1365; CHECK-NEXT: vslidedown.vi v24, v0, 21366; CHECK-NEXT: mv a1, a01367; CHECK-NEXT: bltu a0, a2, .LBB108_21368; CHECK-NEXT: # %bb.1:1369; CHECK-NEXT: li a1, 161370; CHECK-NEXT: .LBB108_2:1371; CHECK-NEXT: li a2, -11372; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1373; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t1374; CHECK-NEXT: addi a1, a0, -161375; CHECK-NEXT: sltu a0, a0, a11376; CHECK-NEXT: addi a0, a0, -11377; CHECK-NEXT: and a0, a0, a11378; CHECK-NEXT: vmv1r.v v0, v241379; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1380; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t1381; CHECK-NEXT: ret1382 %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)1383 ret <32 x i64> %v1384}1385 1386define <32 x i64> @vssubu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {1387; CHECK-LABEL: vssubu_vi_v32i64_unmasked:1388; CHECK: # %bb.0:1389; CHECK-NEXT: li a2, 161390; CHECK-NEXT: mv a1, a01391; CHECK-NEXT: bltu a0, a2, .LBB109_21392; CHECK-NEXT: # %bb.1:1393; CHECK-NEXT: li a1, 161394; CHECK-NEXT: .LBB109_2:1395; CHECK-NEXT: li a2, -11396; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1397; CHECK-NEXT: vssubu.vx v8, v8, a21398; CHECK-NEXT: addi a1, a0, -161399; CHECK-NEXT: sltu a0, a0, a11400; CHECK-NEXT: addi a0, a0, -11401; CHECK-NEXT: and a0, a0, a11402; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1403; CHECK-NEXT: vssubu.vx v16, v16, a21404; CHECK-NEXT: ret1405 %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)1406 ret <32 x i64> %v1407}1408 1409define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {1410; CHECK-LABEL: vssubu_vx_v32i64_evl12:1411; CHECK: # %bb.0:1412; CHECK-NEXT: li a0, -11413; CHECK-NEXT: vsetivli zero, 12, e64, m8, ta, ma1414; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t1415; CHECK-NEXT: ret1416 %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)1417 ret <32 x i64> %v1418}1419 1420define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {1421; CHECK-LABEL: vssubu_vx_v32i64_evl27:1422; CHECK: # %bb.0:1423; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma1424; CHECK-NEXT: vslidedown.vi v24, v0, 21425; CHECK-NEXT: li a0, -11426; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma1427; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t1428; CHECK-NEXT: vmv1r.v v0, v241429; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma1430; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t1431; CHECK-NEXT: ret1432 %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)1433 ret <32 x i64> %v1434}1435