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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=1 | FileCheck %s --check-prefixes=NO_FOLDING13; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=1 | FileCheck %s --check-prefixes=NO_FOLDING14; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=2 | FileCheck %s --check-prefixes=NO_FOLDING25; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=2 | FileCheck %s --check-prefixes=NO_FOLDING26; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=3 | FileCheck %s --check-prefixes=FOLDING7; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=3 | FileCheck %s --check-prefixes=FOLDING8; Check that the default value enables the web folding and9; that it is bigger than 3.10; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=FOLDING11; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=FOLDING12 13 14; Check that the add/sub/mul operations are all promoted into their15; vw counterpart when the folding of the web size is increased to 3.16; We need the web size to be at least 3 for the folding to happen, because17; %c has 3 uses.18define <2 x i16> @vwmul_v2i16_multiple_users(ptr %x, ptr %y, ptr %z) {19; NO_FOLDING1-LABEL: vwmul_v2i16_multiple_users:20; NO_FOLDING1: # %bb.0:21; NO_FOLDING1-NEXT: vsetivli zero, 2, e16, mf4, ta, ma22; NO_FOLDING1-NEXT: vle8.v v8, (a0)23; NO_FOLDING1-NEXT: vle8.v v9, (a1)24; NO_FOLDING1-NEXT: vle8.v v10, (a2)25; NO_FOLDING1-NEXT: vsext.vf2 v11, v826; NO_FOLDING1-NEXT: vsext.vf2 v8, v927; NO_FOLDING1-NEXT: vsext.vf2 v9, v1028; NO_FOLDING1-NEXT: vmul.vv v8, v11, v829; NO_FOLDING1-NEXT: vadd.vv v10, v11, v930; NO_FOLDING1-NEXT: vsub.vv v9, v11, v931; NO_FOLDING1-NEXT: vor.vv v8, v8, v1032; NO_FOLDING1-NEXT: vor.vv v8, v8, v933; NO_FOLDING1-NEXT: ret34;35; NO_FOLDING2-LABEL: vwmul_v2i16_multiple_users:36; NO_FOLDING2: # %bb.0:37; NO_FOLDING2-NEXT: vsetivli zero, 2, e16, mf4, ta, ma38; NO_FOLDING2-NEXT: vle8.v v8, (a0)39; NO_FOLDING2-NEXT: vle8.v v9, (a1)40; NO_FOLDING2-NEXT: vle8.v v10, (a2)41; NO_FOLDING2-NEXT: vsext.vf2 v11, v842; NO_FOLDING2-NEXT: vsext.vf2 v8, v943; NO_FOLDING2-NEXT: vmul.vv v8, v11, v844; NO_FOLDING2-NEXT: vsetvli zero, zero, e8, mf8, ta, ma45; NO_FOLDING2-NEXT: vwadd.wv v9, v11, v1046; NO_FOLDING2-NEXT: vwsub.wv v11, v11, v1047; NO_FOLDING2-NEXT: vsetvli zero, zero, e16, mf4, ta, ma48; NO_FOLDING2-NEXT: vor.vv v8, v8, v949; NO_FOLDING2-NEXT: vor.vv v8, v8, v1150; NO_FOLDING2-NEXT: ret51;52; FOLDING-LABEL: vwmul_v2i16_multiple_users:53; FOLDING: # %bb.0:54; FOLDING-NEXT: vsetivli zero, 2, e8, mf8, ta, ma55; FOLDING-NEXT: vle8.v v8, (a0)56; FOLDING-NEXT: vle8.v v9, (a1)57; FOLDING-NEXT: vle8.v v10, (a2)58; FOLDING-NEXT: vwmul.vv v11, v8, v959; FOLDING-NEXT: vwadd.vv v9, v8, v1060; FOLDING-NEXT: vwsub.vv v12, v8, v1061; FOLDING-NEXT: vsetvli zero, zero, e16, mf4, ta, ma62; FOLDING-NEXT: vor.vv v8, v11, v963; FOLDING-NEXT: vor.vv v8, v8, v1264; FOLDING-NEXT: ret65 %a = load <2 x i8>, ptr %x66 %b = load <2 x i8>, ptr %y67 %b2 = load <2 x i8>, ptr %z68 %c = sext <2 x i8> %a to <2 x i16>69 %d = sext <2 x i8> %b to <2 x i16>70 %d2 = sext <2 x i8> %b2 to <2 x i16>71 %e = mul <2 x i16> %c, %d72 %f = add <2 x i16> %c, %d273 %g = sub <2 x i16> %c, %d274 %h = or <2 x i16> %e, %f75 %i = or <2 x i16> %h, %g76 ret <2 x i16> %i77}78 79; Make sure we have a vsext.vl and a vwaddu.vx.80define <4 x i32> @pr159152(<4 x i8> %x) {81; NO_FOLDING-LABEL: pr159152:82; NO_FOLDING: # %bb.0:83; NO_FOLDING-NEXT: vsetivli zero, 4, e16, mf2, ta, ma84; NO_FOLDING-NEXT: vsext.vf2 v9, v885; NO_FOLDING-NEXT: li a0, 986; NO_FOLDING-NEXT: vwaddu.vx v8, v9, a087; NO_FOLDING-NEXT: ret88;89; FOLDING-LABEL: pr159152:90; FOLDING: # %bb.0:91; FOLDING-NEXT: vsetivli zero, 4, e16, mf2, ta, ma92; FOLDING-NEXT: vsext.vf2 v9, v893; FOLDING-NEXT: li a0, 994; FOLDING-NEXT: vwaddu.vx v8, v9, a095; FOLDING-NEXT: ret96 %a = sext <4 x i8> %x to <4 x i16>97 %b = zext <4 x i16> %a to <4 x i32>98 %c = add <4 x i32> %b, <i32 9, i32 9, i32 9, i32 9>99 ret <4 x i32> %c100}101