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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <2 x i16> @vwaddu_v2i16(ptr %x, ptr %y) {6; CHECK-LABEL: vwaddu_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vle8.v v9, (a0)10; CHECK-NEXT: vle8.v v10, (a1)11; CHECK-NEXT: vwaddu.vv v8, v9, v1012; CHECK-NEXT: ret13 %a = load <2 x i8>, ptr %x14 %b = load <2 x i8>, ptr %y15 %c = zext <2 x i8> %a to <2 x i16>16 %d = zext <2 x i8> %b to <2 x i16>17 %e = add <2 x i16> %c, %d18 ret <2 x i16> %e19}20 21define <4 x i16> @vwaddu_v4i16(ptr %x, ptr %y) {22; CHECK-LABEL: vwaddu_v4i16:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma25; CHECK-NEXT: vle8.v v9, (a0)26; CHECK-NEXT: vle8.v v10, (a1)27; CHECK-NEXT: vwaddu.vv v8, v9, v1028; CHECK-NEXT: ret29 %a = load <4 x i8>, ptr %x30 %b = load <4 x i8>, ptr %y31 %c = zext <4 x i8> %a to <4 x i16>32 %d = zext <4 x i8> %b to <4 x i16>33 %e = add <4 x i16> %c, %d34 ret <4 x i16> %e35}36 37define <2 x i32> @vwaddu_v2i32(ptr %x, ptr %y) {38; CHECK-LABEL: vwaddu_v2i32:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma41; CHECK-NEXT: vle16.v v9, (a0)42; CHECK-NEXT: vle16.v v10, (a1)43; CHECK-NEXT: vwaddu.vv v8, v9, v1044; CHECK-NEXT: ret45 %a = load <2 x i16>, ptr %x46 %b = load <2 x i16>, ptr %y47 %c = zext <2 x i16> %a to <2 x i32>48 %d = zext <2 x i16> %b to <2 x i32>49 %e = add <2 x i32> %c, %d50 ret <2 x i32> %e51}52 53define <8 x i16> @vwaddu_v8i16(ptr %x, ptr %y) {54; CHECK-LABEL: vwaddu_v8i16:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma57; CHECK-NEXT: vle8.v v9, (a0)58; CHECK-NEXT: vle8.v v10, (a1)59; CHECK-NEXT: vwaddu.vv v8, v9, v1060; CHECK-NEXT: ret61 %a = load <8 x i8>, ptr %x62 %b = load <8 x i8>, ptr %y63 %c = zext <8 x i8> %a to <8 x i16>64 %d = zext <8 x i8> %b to <8 x i16>65 %e = add <8 x i16> %c, %d66 ret <8 x i16> %e67}68 69define <4 x i32> @vwaddu_v4i32(ptr %x, ptr %y) {70; CHECK-LABEL: vwaddu_v4i32:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma73; CHECK-NEXT: vle16.v v9, (a0)74; CHECK-NEXT: vle16.v v10, (a1)75; CHECK-NEXT: vwaddu.vv v8, v9, v1076; CHECK-NEXT: ret77 %a = load <4 x i16>, ptr %x78 %b = load <4 x i16>, ptr %y79 %c = zext <4 x i16> %a to <4 x i32>80 %d = zext <4 x i16> %b to <4 x i32>81 %e = add <4 x i32> %c, %d82 ret <4 x i32> %e83}84 85define <2 x i64> @vwaddu_v2i64(ptr %x, ptr %y) {86; CHECK-LABEL: vwaddu_v2i64:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma89; CHECK-NEXT: vle32.v v9, (a0)90; CHECK-NEXT: vle32.v v10, (a1)91; CHECK-NEXT: vwaddu.vv v8, v9, v1092; CHECK-NEXT: ret93 %a = load <2 x i32>, ptr %x94 %b = load <2 x i32>, ptr %y95 %c = zext <2 x i32> %a to <2 x i64>96 %d = zext <2 x i32> %b to <2 x i64>97 %e = add <2 x i64> %c, %d98 ret <2 x i64> %e99}100 101define <16 x i16> @vwaddu_v16i16(ptr %x, ptr %y) {102; CHECK-LABEL: vwaddu_v16i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma105; CHECK-NEXT: vle8.v v10, (a0)106; CHECK-NEXT: vle8.v v11, (a1)107; CHECK-NEXT: vwaddu.vv v8, v10, v11108; CHECK-NEXT: ret109 %a = load <16 x i8>, ptr %x110 %b = load <16 x i8>, ptr %y111 %c = zext <16 x i8> %a to <16 x i16>112 %d = zext <16 x i8> %b to <16 x i16>113 %e = add <16 x i16> %c, %d114 ret <16 x i16> %e115}116 117define <8 x i32> @vwaddu_v8i32(ptr %x, ptr %y) {118; CHECK-LABEL: vwaddu_v8i32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma121; CHECK-NEXT: vle16.v v10, (a0)122; CHECK-NEXT: vle16.v v11, (a1)123; CHECK-NEXT: vwaddu.vv v8, v10, v11124; CHECK-NEXT: ret125 %a = load <8 x i16>, ptr %x126 %b = load <8 x i16>, ptr %y127 %c = zext <8 x i16> %a to <8 x i32>128 %d = zext <8 x i16> %b to <8 x i32>129 %e = add <8 x i32> %c, %d130 ret <8 x i32> %e131}132 133define <4 x i64> @vwaddu_v4i64(ptr %x, ptr %y) {134; CHECK-LABEL: vwaddu_v4i64:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma137; CHECK-NEXT: vle32.v v10, (a0)138; CHECK-NEXT: vle32.v v11, (a1)139; CHECK-NEXT: vwaddu.vv v8, v10, v11140; CHECK-NEXT: ret141 %a = load <4 x i32>, ptr %x142 %b = load <4 x i32>, ptr %y143 %c = zext <4 x i32> %a to <4 x i64>144 %d = zext <4 x i32> %b to <4 x i64>145 %e = add <4 x i64> %c, %d146 ret <4 x i64> %e147}148 149define <32 x i16> @vwaddu_v32i16(ptr %x, ptr %y) {150; CHECK-LABEL: vwaddu_v32i16:151; CHECK: # %bb.0:152; CHECK-NEXT: li a2, 32153; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma154; CHECK-NEXT: vle8.v v12, (a0)155; CHECK-NEXT: vle8.v v14, (a1)156; CHECK-NEXT: vwaddu.vv v8, v12, v14157; CHECK-NEXT: ret158 %a = load <32 x i8>, ptr %x159 %b = load <32 x i8>, ptr %y160 %c = zext <32 x i8> %a to <32 x i16>161 %d = zext <32 x i8> %b to <32 x i16>162 %e = add <32 x i16> %c, %d163 ret <32 x i16> %e164}165 166define <16 x i32> @vwaddu_v16i32(ptr %x, ptr %y) {167; CHECK-LABEL: vwaddu_v16i32:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma170; CHECK-NEXT: vle16.v v12, (a0)171; CHECK-NEXT: vle16.v v14, (a1)172; CHECK-NEXT: vwaddu.vv v8, v12, v14173; CHECK-NEXT: ret174 %a = load <16 x i16>, ptr %x175 %b = load <16 x i16>, ptr %y176 %c = zext <16 x i16> %a to <16 x i32>177 %d = zext <16 x i16> %b to <16 x i32>178 %e = add <16 x i32> %c, %d179 ret <16 x i32> %e180}181 182define <8 x i64> @vwaddu_v8i64(ptr %x, ptr %y) {183; CHECK-LABEL: vwaddu_v8i64:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma186; CHECK-NEXT: vle32.v v12, (a0)187; CHECK-NEXT: vle32.v v14, (a1)188; CHECK-NEXT: vwaddu.vv v8, v12, v14189; CHECK-NEXT: ret190 %a = load <8 x i32>, ptr %x191 %b = load <8 x i32>, ptr %y192 %c = zext <8 x i32> %a to <8 x i64>193 %d = zext <8 x i32> %b to <8 x i64>194 %e = add <8 x i64> %c, %d195 ret <8 x i64> %e196}197 198define <64 x i16> @vwaddu_v64i16(ptr %x, ptr %y) {199; CHECK-LABEL: vwaddu_v64i16:200; CHECK: # %bb.0:201; CHECK-NEXT: li a2, 64202; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma203; CHECK-NEXT: vle8.v v16, (a0)204; CHECK-NEXT: vle8.v v20, (a1)205; CHECK-NEXT: vwaddu.vv v8, v16, v20206; CHECK-NEXT: ret207 %a = load <64 x i8>, ptr %x208 %b = load <64 x i8>, ptr %y209 %c = zext <64 x i8> %a to <64 x i16>210 %d = zext <64 x i8> %b to <64 x i16>211 %e = add <64 x i16> %c, %d212 ret <64 x i16> %e213}214 215define <32 x i32> @vwaddu_v32i32(ptr %x, ptr %y) {216; CHECK-LABEL: vwaddu_v32i32:217; CHECK: # %bb.0:218; CHECK-NEXT: li a2, 32219; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma220; CHECK-NEXT: vle16.v v16, (a0)221; CHECK-NEXT: vle16.v v20, (a1)222; CHECK-NEXT: vwaddu.vv v8, v16, v20223; CHECK-NEXT: ret224 %a = load <32 x i16>, ptr %x225 %b = load <32 x i16>, ptr %y226 %c = zext <32 x i16> %a to <32 x i32>227 %d = zext <32 x i16> %b to <32 x i32>228 %e = add <32 x i32> %c, %d229 ret <32 x i32> %e230}231 232define <16 x i64> @vwaddu_v16i64(ptr %x, ptr %y) {233; CHECK-LABEL: vwaddu_v16i64:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma236; CHECK-NEXT: vle32.v v16, (a0)237; CHECK-NEXT: vle32.v v20, (a1)238; CHECK-NEXT: vwaddu.vv v8, v16, v20239; CHECK-NEXT: ret240 %a = load <16 x i32>, ptr %x241 %b = load <16 x i32>, ptr %y242 %c = zext <16 x i32> %a to <16 x i64>243 %d = zext <16 x i32> %b to <16 x i64>244 %e = add <16 x i64> %c, %d245 ret <16 x i64> %e246}247 248define <128 x i16> @vwaddu_v128i16(ptr %x, ptr %y) nounwind {249; CHECK-LABEL: vwaddu_v128i16:250; CHECK: # %bb.0:251; CHECK-NEXT: addi sp, sp, -16252; CHECK-NEXT: csrr a2, vlenb253; CHECK-NEXT: slli a2, a2, 3254; CHECK-NEXT: sub sp, sp, a2255; CHECK-NEXT: li a2, 128256; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma257; CHECK-NEXT: vle8.v v16, (a0)258; CHECK-NEXT: vle8.v v24, (a1)259; CHECK-NEXT: li a0, 64260; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma261; CHECK-NEXT: vslidedown.vx v8, v16, a0262; CHECK-NEXT: addi a1, sp, 16263; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill264; CHECK-NEXT: vslidedown.vx v0, v24, a0265; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma266; CHECK-NEXT: vwaddu.vv v8, v16, v24267; CHECK-NEXT: addi a0, sp, 16268; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload269; CHECK-NEXT: vwaddu.vv v16, v24, v0270; CHECK-NEXT: csrr a0, vlenb271; CHECK-NEXT: slli a0, a0, 3272; CHECK-NEXT: add sp, sp, a0273; CHECK-NEXT: addi sp, sp, 16274; CHECK-NEXT: ret275 %a = load <128 x i8>, ptr %x276 %b = load <128 x i8>, ptr %y277 %c = zext <128 x i8> %a to <128 x i16>278 %d = zext <128 x i8> %b to <128 x i16>279 %e = add <128 x i16> %c, %d280 ret <128 x i16> %e281}282 283define <64 x i32> @vwaddu_v64i32(ptr %x, ptr %y) nounwind {284; CHECK-LABEL: vwaddu_v64i32:285; CHECK: # %bb.0:286; CHECK-NEXT: addi sp, sp, -16287; CHECK-NEXT: csrr a2, vlenb288; CHECK-NEXT: slli a2, a2, 3289; CHECK-NEXT: sub sp, sp, a2290; CHECK-NEXT: li a2, 64291; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma292; CHECK-NEXT: vle16.v v16, (a0)293; CHECK-NEXT: vle16.v v24, (a1)294; CHECK-NEXT: li a0, 32295; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma296; CHECK-NEXT: vslidedown.vx v8, v16, a0297; CHECK-NEXT: addi a1, sp, 16298; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill299; CHECK-NEXT: vslidedown.vx v0, v24, a0300; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma301; CHECK-NEXT: vwaddu.vv v8, v16, v24302; CHECK-NEXT: addi a0, sp, 16303; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload304; CHECK-NEXT: vwaddu.vv v16, v24, v0305; CHECK-NEXT: csrr a0, vlenb306; CHECK-NEXT: slli a0, a0, 3307; CHECK-NEXT: add sp, sp, a0308; CHECK-NEXT: addi sp, sp, 16309; CHECK-NEXT: ret310 %a = load <64 x i16>, ptr %x311 %b = load <64 x i16>, ptr %y312 %c = zext <64 x i16> %a to <64 x i32>313 %d = zext <64 x i16> %b to <64 x i32>314 %e = add <64 x i32> %c, %d315 ret <64 x i32> %e316}317 318define <32 x i64> @vwaddu_v32i64(ptr %x, ptr %y) nounwind {319; CHECK-LABEL: vwaddu_v32i64:320; CHECK: # %bb.0:321; CHECK-NEXT: addi sp, sp, -16322; CHECK-NEXT: csrr a2, vlenb323; CHECK-NEXT: slli a2, a2, 3324; CHECK-NEXT: sub sp, sp, a2325; CHECK-NEXT: li a2, 32326; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma327; CHECK-NEXT: vle32.v v16, (a0)328; CHECK-NEXT: vle32.v v24, (a1)329; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma330; CHECK-NEXT: vslidedown.vi v8, v16, 16331; CHECK-NEXT: addi a0, sp, 16332; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill333; CHECK-NEXT: vslidedown.vi v0, v24, 16334; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma335; CHECK-NEXT: vwaddu.vv v8, v16, v24336; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload337; CHECK-NEXT: vwaddu.vv v16, v24, v0338; CHECK-NEXT: csrr a0, vlenb339; CHECK-NEXT: slli a0, a0, 3340; CHECK-NEXT: add sp, sp, a0341; CHECK-NEXT: addi sp, sp, 16342; CHECK-NEXT: ret343 %a = load <32 x i32>, ptr %x344 %b = load <32 x i32>, ptr %y345 %c = zext <32 x i32> %a to <32 x i64>346 %d = zext <32 x i32> %b to <32 x i64>347 %e = add <32 x i64> %c, %d348 ret <32 x i64> %e349}350 351define <2 x i32> @vwaddu_v2i32_v2i8(ptr %x, ptr %y) {352; CHECK-LABEL: vwaddu_v2i32_v2i8:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma355; CHECK-NEXT: vle8.v v8, (a0)356; CHECK-NEXT: vle8.v v9, (a1)357; CHECK-NEXT: vwaddu.vv v10, v8, v9358; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma359; CHECK-NEXT: vzext.vf2 v8, v10360; CHECK-NEXT: ret361 %a = load <2 x i8>, ptr %x362 %b = load <2 x i8>, ptr %y363 %c = zext <2 x i8> %a to <2 x i32>364 %d = zext <2 x i8> %b to <2 x i32>365 %e = add <2 x i32> %c, %d366 ret <2 x i32> %e367}368 369define <4 x i32> @vwaddu_v4i32_v4i8_v4i16(ptr %x, ptr %y) {370; CHECK-LABEL: vwaddu_v4i32_v4i8_v4i16:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma373; CHECK-NEXT: vle8.v v8, (a0)374; CHECK-NEXT: vle16.v v9, (a1)375; CHECK-NEXT: vzext.vf2 v10, v8376; CHECK-NEXT: vwaddu.vv v8, v10, v9377; CHECK-NEXT: ret378 %a = load <4 x i8>, ptr %x379 %b = load <4 x i16>, ptr %y380 %c = zext <4 x i8> %a to <4 x i32>381 %d = zext <4 x i16> %b to <4 x i32>382 %e = add <4 x i32> %c, %d383 ret <4 x i32> %e384}385 386define <4 x i64> @vwaddu_v4i64_v4i32_v4i8(ptr %x, ptr %y) {387; CHECK-LABEL: vwaddu_v4i64_v4i32_v4i8:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma390; CHECK-NEXT: vle8.v v8, (a1)391; CHECK-NEXT: vle32.v v10, (a0)392; CHECK-NEXT: vzext.vf4 v11, v8393; CHECK-NEXT: vwaddu.vv v8, v10, v11394; CHECK-NEXT: ret395 %a = load <4 x i32>, ptr %x396 %b = load <4 x i8>, ptr %y397 %c = zext <4 x i32> %a to <4 x i64>398 %d = zext <4 x i8> %b to <4 x i64>399 %e = add <4 x i64> %c, %d400 ret <4 x i64> %e401}402 403define <2 x i16> @vwaddu_vx_v2i16(ptr %x, i8 %y) {404; CHECK-LABEL: vwaddu_vx_v2i16:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma407; CHECK-NEXT: vle8.v v9, (a0)408; CHECK-NEXT: vwaddu.vx v8, v9, a1409; CHECK-NEXT: ret410 %a = load <2 x i8>, ptr %x411 %b = insertelement <2 x i8> poison, i8 %y, i32 0412 %c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer413 %d = zext <2 x i8> %a to <2 x i16>414 %e = zext <2 x i8> %c to <2 x i16>415 %f = add <2 x i16> %d, %e416 ret <2 x i16> %f417}418 419define <4 x i16> @vwaddu_vx_v4i16(ptr %x, i8 %y) {420; CHECK-LABEL: vwaddu_vx_v4i16:421; CHECK: # %bb.0:422; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma423; CHECK-NEXT: vle8.v v9, (a0)424; CHECK-NEXT: vwaddu.vx v8, v9, a1425; CHECK-NEXT: ret426 %a = load <4 x i8>, ptr %x427 %b = insertelement <4 x i8> poison, i8 %y, i32 0428 %c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer429 %d = zext <4 x i8> %a to <4 x i16>430 %e = zext <4 x i8> %c to <4 x i16>431 %f = add <4 x i16> %d, %e432 ret <4 x i16> %f433}434 435define <2 x i32> @vwaddu_vx_v2i32(ptr %x, i16 %y) {436; CHECK-LABEL: vwaddu_vx_v2i32:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma439; CHECK-NEXT: vle16.v v9, (a0)440; CHECK-NEXT: vwaddu.vx v8, v9, a1441; CHECK-NEXT: ret442 %a = load <2 x i16>, ptr %x443 %b = insertelement <2 x i16> poison, i16 %y, i32 0444 %c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer445 %d = zext <2 x i16> %a to <2 x i32>446 %e = zext <2 x i16> %c to <2 x i32>447 %f = add <2 x i32> %d, %e448 ret <2 x i32> %f449}450 451define <8 x i16> @vwaddu_vx_v8i16(ptr %x, i8 %y) {452; CHECK-LABEL: vwaddu_vx_v8i16:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma455; CHECK-NEXT: vle8.v v9, (a0)456; CHECK-NEXT: vwaddu.vx v8, v9, a1457; CHECK-NEXT: ret458 %a = load <8 x i8>, ptr %x459 %b = insertelement <8 x i8> poison, i8 %y, i32 0460 %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer461 %d = zext <8 x i8> %a to <8 x i16>462 %e = zext <8 x i8> %c to <8 x i16>463 %f = add <8 x i16> %d, %e464 ret <8 x i16> %f465}466 467define <4 x i32> @vwaddu_vx_v4i32(ptr %x, i16 %y) {468; CHECK-LABEL: vwaddu_vx_v4i32:469; CHECK: # %bb.0:470; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma471; CHECK-NEXT: vle16.v v9, (a0)472; CHECK-NEXT: vwaddu.vx v8, v9, a1473; CHECK-NEXT: ret474 %a = load <4 x i16>, ptr %x475 %b = insertelement <4 x i16> poison, i16 %y, i32 0476 %c = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer477 %d = zext <4 x i16> %a to <4 x i32>478 %e = zext <4 x i16> %c to <4 x i32>479 %f = add <4 x i32> %d, %e480 ret <4 x i32> %f481}482 483define <2 x i64> @vwaddu_vx_v2i64(ptr %x, i32 %y) {484; CHECK-LABEL: vwaddu_vx_v2i64:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma487; CHECK-NEXT: vle32.v v9, (a0)488; CHECK-NEXT: vwaddu.vx v8, v9, a1489; CHECK-NEXT: ret490 %a = load <2 x i32>, ptr %x491 %b = insertelement <2 x i32> poison, i32 %y, i64 0492 %c = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer493 %d = zext <2 x i32> %a to <2 x i64>494 %e = zext <2 x i32> %c to <2 x i64>495 %f = add <2 x i64> %d, %e496 ret <2 x i64> %f497}498 499define <16 x i16> @vwaddu_vx_v16i16(ptr %x, i8 %y) {500; CHECK-LABEL: vwaddu_vx_v16i16:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma503; CHECK-NEXT: vle8.v v10, (a0)504; CHECK-NEXT: vwaddu.vx v8, v10, a1505; CHECK-NEXT: ret506 %a = load <16 x i8>, ptr %x507 %b = insertelement <16 x i8> poison, i8 %y, i32 0508 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer509 %d = zext <16 x i8> %a to <16 x i16>510 %e = zext <16 x i8> %c to <16 x i16>511 %f = add <16 x i16> %d, %e512 ret <16 x i16> %f513}514 515define <8 x i32> @vwaddu_vx_v8i32(ptr %x, i16 %y) {516; CHECK-LABEL: vwaddu_vx_v8i32:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma519; CHECK-NEXT: vle16.v v10, (a0)520; CHECK-NEXT: vwaddu.vx v8, v10, a1521; CHECK-NEXT: ret522 %a = load <8 x i16>, ptr %x523 %b = insertelement <8 x i16> poison, i16 %y, i32 0524 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer525 %d = zext <8 x i16> %a to <8 x i32>526 %e = zext <8 x i16> %c to <8 x i32>527 %f = add <8 x i32> %d, %e528 ret <8 x i32> %f529}530 531define <4 x i64> @vwaddu_vx_v4i64(ptr %x, i32 %y) {532; CHECK-LABEL: vwaddu_vx_v4i64:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma535; CHECK-NEXT: vle32.v v10, (a0)536; CHECK-NEXT: vwaddu.vx v8, v10, a1537; CHECK-NEXT: ret538 %a = load <4 x i32>, ptr %x539 %b = insertelement <4 x i32> poison, i32 %y, i64 0540 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer541 %d = zext <4 x i32> %a to <4 x i64>542 %e = zext <4 x i32> %c to <4 x i64>543 %f = add <4 x i64> %d, %e544 ret <4 x i64> %f545}546 547define <32 x i16> @vwaddu_vx_v32i16(ptr %x, i8 %y) {548; CHECK-LABEL: vwaddu_vx_v32i16:549; CHECK: # %bb.0:550; CHECK-NEXT: li a2, 32551; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma552; CHECK-NEXT: vle8.v v12, (a0)553; CHECK-NEXT: vwaddu.vx v8, v12, a1554; CHECK-NEXT: ret555 %a = load <32 x i8>, ptr %x556 %b = insertelement <32 x i8> poison, i8 %y, i32 0557 %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer558 %d = zext <32 x i8> %a to <32 x i16>559 %e = zext <32 x i8> %c to <32 x i16>560 %f = add <32 x i16> %d, %e561 ret <32 x i16> %f562}563 564define <16 x i32> @vwaddu_vx_v16i32(ptr %x, i16 %y) {565; CHECK-LABEL: vwaddu_vx_v16i32:566; CHECK: # %bb.0:567; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma568; CHECK-NEXT: vle16.v v12, (a0)569; CHECK-NEXT: vwaddu.vx v8, v12, a1570; CHECK-NEXT: ret571 %a = load <16 x i16>, ptr %x572 %b = insertelement <16 x i16> poison, i16 %y, i32 0573 %c = shufflevector <16 x i16> %b, <16 x i16> poison, <16 x i32> zeroinitializer574 %d = zext <16 x i16> %a to <16 x i32>575 %e = zext <16 x i16> %c to <16 x i32>576 %f = add <16 x i32> %d, %e577 ret <16 x i32> %f578}579 580define <8 x i64> @vwaddu_vx_v8i64(ptr %x, i32 %y) {581; CHECK-LABEL: vwaddu_vx_v8i64:582; CHECK: # %bb.0:583; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma584; CHECK-NEXT: vle32.v v12, (a0)585; CHECK-NEXT: vwaddu.vx v8, v12, a1586; CHECK-NEXT: ret587 %a = load <8 x i32>, ptr %x588 %b = insertelement <8 x i32> poison, i32 %y, i64 0589 %c = shufflevector <8 x i32> %b, <8 x i32> poison, <8 x i32> zeroinitializer590 %d = zext <8 x i32> %a to <8 x i64>591 %e = zext <8 x i32> %c to <8 x i64>592 %f = add <8 x i64> %d, %e593 ret <8 x i64> %f594}595 596define <64 x i16> @vwaddu_vx_v64i16(ptr %x, i8 %y) {597; CHECK-LABEL: vwaddu_vx_v64i16:598; CHECK: # %bb.0:599; CHECK-NEXT: li a2, 64600; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma601; CHECK-NEXT: vle8.v v16, (a0)602; CHECK-NEXT: vwaddu.vx v8, v16, a1603; CHECK-NEXT: ret604 %a = load <64 x i8>, ptr %x605 %b = insertelement <64 x i8> poison, i8 %y, i32 0606 %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer607 %d = zext <64 x i8> %a to <64 x i16>608 %e = zext <64 x i8> %c to <64 x i16>609 %f = add <64 x i16> %d, %e610 ret <64 x i16> %f611}612 613define <32 x i32> @vwaddu_vx_v32i32(ptr %x, i16 %y) {614; CHECK-LABEL: vwaddu_vx_v32i32:615; CHECK: # %bb.0:616; CHECK-NEXT: li a2, 32617; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma618; CHECK-NEXT: vle16.v v16, (a0)619; CHECK-NEXT: vwaddu.vx v8, v16, a1620; CHECK-NEXT: ret621 %a = load <32 x i16>, ptr %x622 %b = insertelement <32 x i16> poison, i16 %y, i32 0623 %c = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer624 %d = zext <32 x i16> %a to <32 x i32>625 %e = zext <32 x i16> %c to <32 x i32>626 %f = add <32 x i32> %d, %e627 ret <32 x i32> %f628}629 630define <16 x i64> @vwaddu_vx_v16i64(ptr %x, i32 %y) {631; CHECK-LABEL: vwaddu_vx_v16i64:632; CHECK: # %bb.0:633; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma634; CHECK-NEXT: vle32.v v16, (a0)635; CHECK-NEXT: vwaddu.vx v8, v16, a1636; CHECK-NEXT: ret637 %a = load <16 x i32>, ptr %x638 %b = insertelement <16 x i32> poison, i32 %y, i64 0639 %c = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer640 %d = zext <16 x i32> %a to <16 x i64>641 %e = zext <16 x i32> %c to <16 x i64>642 %f = add <16 x i64> %d, %e643 ret <16 x i64> %f644}645 646define <8 x i16> @vwaddu_vx_v8i16_i8(ptr %x, ptr %y) {647; CHECK-LABEL: vwaddu_vx_v8i16_i8:648; CHECK: # %bb.0:649; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma650; CHECK-NEXT: vle8.v v9, (a0)651; CHECK-NEXT: lbu a0, 0(a1)652; CHECK-NEXT: vwaddu.vx v8, v9, a0653; CHECK-NEXT: ret654 %a = load <8 x i8>, ptr %x655 %b = load i8, ptr %y656 %c = zext i8 %b to i16657 %d = insertelement <8 x i16> poison, i16 %c, i32 0658 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer659 %f = zext <8 x i8> %a to <8 x i16>660 %g = add <8 x i16> %e, %f661 ret <8 x i16> %g662}663 664define <8 x i16> @vwaddu_vx_v8i16_i16(ptr %x, ptr %y) {665; CHECK-LABEL: vwaddu_vx_v8i16_i16:666; CHECK: # %bb.0:667; CHECK-NEXT: lh a1, 0(a1)668; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma669; CHECK-NEXT: vle8.v v9, (a0)670; CHECK-NEXT: vmv.v.x v8, a1671; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma672; CHECK-NEXT: vwaddu.wv v8, v8, v9673; CHECK-NEXT: ret674 %a = load <8 x i8>, ptr %x675 %b = load i16, ptr %y676 %d = insertelement <8 x i16> poison, i16 %b, i32 0677 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer678 %f = zext <8 x i8> %a to <8 x i16>679 %g = add <8 x i16> %e, %f680 ret <8 x i16> %g681}682 683define <4 x i32> @vwaddu_vx_v4i32_i8(ptr %x, ptr %y) {684; CHECK-LABEL: vwaddu_vx_v4i32_i8:685; CHECK: # %bb.0:686; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma687; CHECK-NEXT: vle16.v v9, (a0)688; CHECK-NEXT: lbu a0, 0(a1)689; CHECK-NEXT: vwaddu.vx v8, v9, a0690; CHECK-NEXT: ret691 %a = load <4 x i16>, ptr %x692 %b = load i8, ptr %y693 %c = zext i8 %b to i32694 %d = insertelement <4 x i32> poison, i32 %c, i32 0695 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer696 %f = zext <4 x i16> %a to <4 x i32>697 %g = add <4 x i32> %e, %f698 ret <4 x i32> %g699}700 701define <4 x i32> @vwaddu_vx_v4i32_i16(ptr %x, ptr %y) {702; CHECK-LABEL: vwaddu_vx_v4i32_i16:703; CHECK: # %bb.0:704; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma705; CHECK-NEXT: vle16.v v9, (a0)706; CHECK-NEXT: lhu a0, 0(a1)707; CHECK-NEXT: vwaddu.vx v8, v9, a0708; CHECK-NEXT: ret709 %a = load <4 x i16>, ptr %x710 %b = load i16, ptr %y711 %c = zext i16 %b to i32712 %d = insertelement <4 x i32> poison, i32 %c, i32 0713 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer714 %f = zext <4 x i16> %a to <4 x i32>715 %g = add <4 x i32> %e, %f716 ret <4 x i32> %g717}718 719define <4 x i32> @vwaddu_vx_v4i32_i32(ptr %x, ptr %y) {720; CHECK-LABEL: vwaddu_vx_v4i32_i32:721; CHECK: # %bb.0:722; CHECK-NEXT: lw a1, 0(a1)723; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma724; CHECK-NEXT: vle16.v v9, (a0)725; CHECK-NEXT: vmv.v.x v8, a1726; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma727; CHECK-NEXT: vwaddu.wv v8, v8, v9728; CHECK-NEXT: ret729 %a = load <4 x i16>, ptr %x730 %b = load i32, ptr %y731 %d = insertelement <4 x i32> poison, i32 %b, i32 0732 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer733 %f = zext <4 x i16> %a to <4 x i32>734 %g = add <4 x i32> %e, %f735 ret <4 x i32> %g736}737 738define <2 x i64> @vwaddu_vx_v2i64_i8(ptr %x, ptr %y) nounwind {739; RV32-LABEL: vwaddu_vx_v2i64_i8:740; RV32: # %bb.0:741; RV32-NEXT: addi sp, sp, -16742; RV32-NEXT: lbu a1, 0(a1)743; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma744; RV32-NEXT: vle32.v v9, (a0)745; RV32-NEXT: sw a1, 8(sp)746; RV32-NEXT: sw zero, 12(sp)747; RV32-NEXT: addi a0, sp, 8748; RV32-NEXT: vlse64.v v8, (a0), zero749; RV32-NEXT: vwaddu.wv v8, v8, v9750; RV32-NEXT: addi sp, sp, 16751; RV32-NEXT: ret752;753; RV64-LABEL: vwaddu_vx_v2i64_i8:754; RV64: # %bb.0:755; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma756; RV64-NEXT: vle32.v v9, (a0)757; RV64-NEXT: lbu a0, 0(a1)758; RV64-NEXT: vwaddu.vx v8, v9, a0759; RV64-NEXT: ret760 %a = load <2 x i32>, ptr %x761 %b = load i8, ptr %y762 %c = zext i8 %b to i64763 %d = insertelement <2 x i64> poison, i64 %c, i64 0764 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer765 %f = zext <2 x i32> %a to <2 x i64>766 %g = add <2 x i64> %e, %f767 ret <2 x i64> %g768}769 770define <2 x i64> @vwaddu_vx_v2i64_i16(ptr %x, ptr %y) nounwind {771; RV32-LABEL: vwaddu_vx_v2i64_i16:772; RV32: # %bb.0:773; RV32-NEXT: addi sp, sp, -16774; RV32-NEXT: lhu a1, 0(a1)775; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma776; RV32-NEXT: vle32.v v9, (a0)777; RV32-NEXT: sw a1, 8(sp)778; RV32-NEXT: sw zero, 12(sp)779; RV32-NEXT: addi a0, sp, 8780; RV32-NEXT: vlse64.v v8, (a0), zero781; RV32-NEXT: vwaddu.wv v8, v8, v9782; RV32-NEXT: addi sp, sp, 16783; RV32-NEXT: ret784;785; RV64-LABEL: vwaddu_vx_v2i64_i16:786; RV64: # %bb.0:787; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma788; RV64-NEXT: vle32.v v9, (a0)789; RV64-NEXT: lhu a0, 0(a1)790; RV64-NEXT: vwaddu.vx v8, v9, a0791; RV64-NEXT: ret792 %a = load <2 x i32>, ptr %x793 %b = load i16, ptr %y794 %c = zext i16 %b to i64795 %d = insertelement <2 x i64> poison, i64 %c, i64 0796 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer797 %f = zext <2 x i32> %a to <2 x i64>798 %g = add <2 x i64> %e, %f799 ret <2 x i64> %g800}801 802define <2 x i64> @vwaddu_vx_v2i64_i32(ptr %x, ptr %y) nounwind {803; RV32-LABEL: vwaddu_vx_v2i64_i32:804; RV32: # %bb.0:805; RV32-NEXT: addi sp, sp, -16806; RV32-NEXT: lw a1, 0(a1)807; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma808; RV32-NEXT: vle32.v v9, (a0)809; RV32-NEXT: sw a1, 8(sp)810; RV32-NEXT: sw zero, 12(sp)811; RV32-NEXT: addi a0, sp, 8812; RV32-NEXT: vlse64.v v8, (a0), zero813; RV32-NEXT: vwaddu.wv v8, v8, v9814; RV32-NEXT: addi sp, sp, 16815; RV32-NEXT: ret816;817; RV64-LABEL: vwaddu_vx_v2i64_i32:818; RV64: # %bb.0:819; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma820; RV64-NEXT: vle32.v v9, (a0)821; RV64-NEXT: lw a0, 0(a1)822; RV64-NEXT: vwaddu.vx v8, v9, a0823; RV64-NEXT: ret824 %a = load <2 x i32>, ptr %x825 %b = load i32, ptr %y826 %c = zext i32 %b to i64827 %d = insertelement <2 x i64> poison, i64 %c, i64 0828 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer829 %f = zext <2 x i32> %a to <2 x i64>830 %g = add <2 x i64> %e, %f831 ret <2 x i64> %g832}833 834define <2 x i64> @vwaddu_vx_v2i64_i64(ptr %x, ptr %y) nounwind {835; RV32-LABEL: vwaddu_vx_v2i64_i64:836; RV32: # %bb.0:837; RV32-NEXT: addi sp, sp, -16838; RV32-NEXT: lw a2, 0(a1)839; RV32-NEXT: lw a1, 4(a1)840; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma841; RV32-NEXT: vle32.v v9, (a0)842; RV32-NEXT: sw a2, 8(sp)843; RV32-NEXT: sw a1, 12(sp)844; RV32-NEXT: addi a0, sp, 8845; RV32-NEXT: vlse64.v v8, (a0), zero846; RV32-NEXT: vwaddu.wv v8, v8, v9847; RV32-NEXT: addi sp, sp, 16848; RV32-NEXT: ret849;850; RV64-LABEL: vwaddu_vx_v2i64_i64:851; RV64: # %bb.0:852; RV64-NEXT: ld a1, 0(a1)853; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma854; RV64-NEXT: vle32.v v9, (a0)855; RV64-NEXT: vmv.v.x v8, a1856; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma857; RV64-NEXT: vwaddu.wv v8, v8, v9858; RV64-NEXT: ret859 %a = load <2 x i32>, ptr %x860 %b = load i64, ptr %y861 %d = insertelement <2 x i64> poison, i64 %b, i64 0862 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer863 %f = zext <2 x i32> %a to <2 x i64>864 %g = add <2 x i64> %e, %f865 ret <2 x i64> %g866}867 868define <4 x i64> @crash(<4 x i16> %x, <4 x i16> %y) {869; CHECK-LABEL: crash:870; CHECK: # %bb.0:871; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma872; CHECK-NEXT: vmv1r.v v10, v9873; CHECK-NEXT: vmv1r.v v11, v8874; CHECK-NEXT: vsext.vf4 v8, v11875; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma876; CHECK-NEXT: vzext.vf2 v11, v10877; CHECK-NEXT: vwaddu.wv v8, v8, v11878; CHECK-NEXT: ret879 %a = sext <4 x i16> %x to <4 x i64>880 %b = zext <4 x i16> %y to <4 x i64>881 %c = add <4 x i64> %a, %b882 ret <4 x i64> %c883}884 885define <2 x i32> @vwaddu_v2i32_of_v2i8(ptr %x, ptr %y) {886; CHECK-LABEL: vwaddu_v2i32_of_v2i8:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma889; CHECK-NEXT: vle8.v v8, (a0)890; CHECK-NEXT: vle8.v v9, (a1)891; CHECK-NEXT: vwaddu.vv v10, v8, v9892; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma893; CHECK-NEXT: vzext.vf2 v8, v10894; CHECK-NEXT: ret895 %a = load <2 x i8>, ptr %x896 %b = load <2 x i8>, ptr %y897 %c = zext <2 x i8> %a to <2 x i32>898 %d = zext <2 x i8> %b to <2 x i32>899 %e = add <2 x i32> %c, %d900 ret <2 x i32> %e901}902 903define <2 x i64> @vwaddu_v2i64_of_v2i8(ptr %x, ptr %y) {904; CHECK-LABEL: vwaddu_v2i64_of_v2i8:905; CHECK: # %bb.0:906; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma907; CHECK-NEXT: vle8.v v8, (a0)908; CHECK-NEXT: vle8.v v9, (a1)909; CHECK-NEXT: vwaddu.vv v10, v8, v9910; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma911; CHECK-NEXT: vzext.vf4 v8, v10912; CHECK-NEXT: ret913 %a = load <2 x i8>, ptr %x914 %b = load <2 x i8>, ptr %y915 %c = zext <2 x i8> %a to <2 x i64>916 %d = zext <2 x i8> %b to <2 x i64>917 %e = add <2 x i64> %c, %d918 ret <2 x i64> %e919}920 921define <2 x i64> @vwaddu_v2i64_of_v2i16(ptr %x, ptr %y) {922; CHECK-LABEL: vwaddu_v2i64_of_v2i16:923; CHECK: # %bb.0:924; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma925; CHECK-NEXT: vle16.v v8, (a0)926; CHECK-NEXT: vle16.v v9, (a1)927; CHECK-NEXT: vwaddu.vv v10, v8, v9928; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma929; CHECK-NEXT: vzext.vf2 v8, v10930; CHECK-NEXT: ret931 %a = load <2 x i16>, ptr %x932 %b = load <2 x i16>, ptr %y933 %c = zext <2 x i16> %a to <2 x i64>934 %d = zext <2 x i16> %b to <2 x i64>935 %e = add <2 x i64> %c, %d936 ret <2 x i64> %e937}938