898 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <2 x i16> @vwmul_v2i16(ptr %x, ptr %y) {6; CHECK-LABEL: vwmul_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vle8.v v9, (a0)10; CHECK-NEXT: vle8.v v10, (a1)11; CHECK-NEXT: vwmul.vv v8, v9, v1012; CHECK-NEXT: ret13 %a = load <2 x i8>, ptr %x14 %b = load <2 x i8>, ptr %y15 %c = sext <2 x i8> %a to <2 x i16>16 %d = sext <2 x i8> %b to <2 x i16>17 %e = mul <2 x i16> %c, %d18 ret <2 x i16> %e19}20 21define <2 x i16> @vwmul_v2i16_multiple_users(ptr %x, ptr %y, ptr %z) {22; CHECK-LABEL: vwmul_v2i16_multiple_users:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma25; CHECK-NEXT: vle8.v v8, (a0)26; CHECK-NEXT: vle8.v v9, (a1)27; CHECK-NEXT: vle8.v v10, (a2)28; CHECK-NEXT: vwmul.vv v11, v8, v929; CHECK-NEXT: vwmul.vv v9, v8, v1030; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma31; CHECK-NEXT: vor.vv v8, v11, v932; CHECK-NEXT: ret33 %a = load <2 x i8>, ptr %x34 %b = load <2 x i8>, ptr %y35 %b2 = load <2 x i8>, ptr %z36 %c = sext <2 x i8> %a to <2 x i16>37 %d = sext <2 x i8> %b to <2 x i16>38 %d2 = sext <2 x i8> %b2 to <2 x i16>39 %e = mul <2 x i16> %c, %d40 %f = mul <2 x i16> %c, %d241 %g = or <2 x i16> %e, %f42 ret <2 x i16> %g43}44 45define <4 x i16> @vwmul_v4i16(ptr %x, ptr %y) {46; CHECK-LABEL: vwmul_v4i16:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma49; CHECK-NEXT: vle8.v v9, (a0)50; CHECK-NEXT: vle8.v v10, (a1)51; CHECK-NEXT: vwmul.vv v8, v9, v1052; CHECK-NEXT: ret53 %a = load <4 x i8>, ptr %x54 %b = load <4 x i8>, ptr %y55 %c = sext <4 x i8> %a to <4 x i16>56 %d = sext <4 x i8> %b to <4 x i16>57 %e = mul <4 x i16> %c, %d58 ret <4 x i16> %e59}60 61define <2 x i32> @vwmul_v2i32(ptr %x, ptr %y) {62; CHECK-LABEL: vwmul_v2i32:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma65; CHECK-NEXT: vle16.v v9, (a0)66; CHECK-NEXT: vle16.v v10, (a1)67; CHECK-NEXT: vwmul.vv v8, v9, v1068; CHECK-NEXT: ret69 %a = load <2 x i16>, ptr %x70 %b = load <2 x i16>, ptr %y71 %c = sext <2 x i16> %a to <2 x i32>72 %d = sext <2 x i16> %b to <2 x i32>73 %e = mul <2 x i32> %c, %d74 ret <2 x i32> %e75}76 77define <8 x i16> @vwmul_v8i16(ptr %x, ptr %y) {78; CHECK-LABEL: vwmul_v8i16:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma81; CHECK-NEXT: vle8.v v9, (a0)82; CHECK-NEXT: vle8.v v10, (a1)83; CHECK-NEXT: vwmul.vv v8, v9, v1084; CHECK-NEXT: ret85 %a = load <8 x i8>, ptr %x86 %b = load <8 x i8>, ptr %y87 %c = sext <8 x i8> %a to <8 x i16>88 %d = sext <8 x i8> %b to <8 x i16>89 %e = mul <8 x i16> %c, %d90 ret <8 x i16> %e91}92 93define <4 x i32> @vwmul_v4i32(ptr %x, ptr %y) {94; CHECK-LABEL: vwmul_v4i32:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma97; CHECK-NEXT: vle16.v v9, (a0)98; CHECK-NEXT: vle16.v v10, (a1)99; CHECK-NEXT: vwmul.vv v8, v9, v10100; CHECK-NEXT: ret101 %a = load <4 x i16>, ptr %x102 %b = load <4 x i16>, ptr %y103 %c = sext <4 x i16> %a to <4 x i32>104 %d = sext <4 x i16> %b to <4 x i32>105 %e = mul <4 x i32> %c, %d106 ret <4 x i32> %e107}108 109define <2 x i64> @vwmul_v2i64(ptr %x, ptr %y) {110; CHECK-LABEL: vwmul_v2i64:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma113; CHECK-NEXT: vle32.v v9, (a0)114; CHECK-NEXT: vle32.v v10, (a1)115; CHECK-NEXT: vwmul.vv v8, v9, v10116; CHECK-NEXT: ret117 %a = load <2 x i32>, ptr %x118 %b = load <2 x i32>, ptr %y119 %c = sext <2 x i32> %a to <2 x i64>120 %d = sext <2 x i32> %b to <2 x i64>121 %e = mul <2 x i64> %c, %d122 ret <2 x i64> %e123}124 125define <16 x i16> @vwmul_v16i16(ptr %x, ptr %y) {126; CHECK-LABEL: vwmul_v16i16:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma129; CHECK-NEXT: vle8.v v10, (a0)130; CHECK-NEXT: vle8.v v11, (a1)131; CHECK-NEXT: vwmul.vv v8, v10, v11132; CHECK-NEXT: ret133 %a = load <16 x i8>, ptr %x134 %b = load <16 x i8>, ptr %y135 %c = sext <16 x i8> %a to <16 x i16>136 %d = sext <16 x i8> %b to <16 x i16>137 %e = mul <16 x i16> %c, %d138 ret <16 x i16> %e139}140 141define <8 x i32> @vwmul_v8i32(ptr %x, ptr %y) {142; CHECK-LABEL: vwmul_v8i32:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma145; CHECK-NEXT: vle16.v v10, (a0)146; CHECK-NEXT: vle16.v v11, (a1)147; CHECK-NEXT: vwmul.vv v8, v10, v11148; CHECK-NEXT: ret149 %a = load <8 x i16>, ptr %x150 %b = load <8 x i16>, ptr %y151 %c = sext <8 x i16> %a to <8 x i32>152 %d = sext <8 x i16> %b to <8 x i32>153 %e = mul <8 x i32> %c, %d154 ret <8 x i32> %e155}156 157define <4 x i64> @vwmul_v4i64(ptr %x, ptr %y) {158; CHECK-LABEL: vwmul_v4i64:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma161; CHECK-NEXT: vle32.v v10, (a0)162; CHECK-NEXT: vle32.v v11, (a1)163; CHECK-NEXT: vwmul.vv v8, v10, v11164; CHECK-NEXT: ret165 %a = load <4 x i32>, ptr %x166 %b = load <4 x i32>, ptr %y167 %c = sext <4 x i32> %a to <4 x i64>168 %d = sext <4 x i32> %b to <4 x i64>169 %e = mul <4 x i64> %c, %d170 ret <4 x i64> %e171}172 173define <32 x i16> @vwmul_v32i16(ptr %x, ptr %y) {174; CHECK-LABEL: vwmul_v32i16:175; CHECK: # %bb.0:176; CHECK-NEXT: li a2, 32177; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma178; CHECK-NEXT: vle8.v v12, (a0)179; CHECK-NEXT: vle8.v v14, (a1)180; CHECK-NEXT: vwmul.vv v8, v12, v14181; CHECK-NEXT: ret182 %a = load <32 x i8>, ptr %x183 %b = load <32 x i8>, ptr %y184 %c = sext <32 x i8> %a to <32 x i16>185 %d = sext <32 x i8> %b to <32 x i16>186 %e = mul <32 x i16> %c, %d187 ret <32 x i16> %e188}189 190define <16 x i32> @vwmul_v16i32(ptr %x, ptr %y) {191; CHECK-LABEL: vwmul_v16i32:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma194; CHECK-NEXT: vle16.v v12, (a0)195; CHECK-NEXT: vle16.v v14, (a1)196; CHECK-NEXT: vwmul.vv v8, v12, v14197; CHECK-NEXT: ret198 %a = load <16 x i16>, ptr %x199 %b = load <16 x i16>, ptr %y200 %c = sext <16 x i16> %a to <16 x i32>201 %d = sext <16 x i16> %b to <16 x i32>202 %e = mul <16 x i32> %c, %d203 ret <16 x i32> %e204}205 206define <8 x i64> @vwmul_v8i64(ptr %x, ptr %y) {207; CHECK-LABEL: vwmul_v8i64:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma210; CHECK-NEXT: vle32.v v12, (a0)211; CHECK-NEXT: vle32.v v14, (a1)212; CHECK-NEXT: vwmul.vv v8, v12, v14213; CHECK-NEXT: ret214 %a = load <8 x i32>, ptr %x215 %b = load <8 x i32>, ptr %y216 %c = sext <8 x i32> %a to <8 x i64>217 %d = sext <8 x i32> %b to <8 x i64>218 %e = mul <8 x i64> %c, %d219 ret <8 x i64> %e220}221 222define <64 x i16> @vwmul_v64i16(ptr %x, ptr %y) {223; CHECK-LABEL: vwmul_v64i16:224; CHECK: # %bb.0:225; CHECK-NEXT: li a2, 64226; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma227; CHECK-NEXT: vle8.v v16, (a0)228; CHECK-NEXT: vle8.v v20, (a1)229; CHECK-NEXT: vwmul.vv v8, v16, v20230; CHECK-NEXT: ret231 %a = load <64 x i8>, ptr %x232 %b = load <64 x i8>, ptr %y233 %c = sext <64 x i8> %a to <64 x i16>234 %d = sext <64 x i8> %b to <64 x i16>235 %e = mul <64 x i16> %c, %d236 ret <64 x i16> %e237}238 239define <32 x i32> @vwmul_v32i32(ptr %x, ptr %y) {240; CHECK-LABEL: vwmul_v32i32:241; CHECK: # %bb.0:242; CHECK-NEXT: li a2, 32243; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma244; CHECK-NEXT: vle16.v v16, (a0)245; CHECK-NEXT: vle16.v v20, (a1)246; CHECK-NEXT: vwmul.vv v8, v16, v20247; CHECK-NEXT: ret248 %a = load <32 x i16>, ptr %x249 %b = load <32 x i16>, ptr %y250 %c = sext <32 x i16> %a to <32 x i32>251 %d = sext <32 x i16> %b to <32 x i32>252 %e = mul <32 x i32> %c, %d253 ret <32 x i32> %e254}255 256define <16 x i64> @vwmul_v16i64(ptr %x, ptr %y) {257; CHECK-LABEL: vwmul_v16i64:258; CHECK: # %bb.0:259; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma260; CHECK-NEXT: vle32.v v16, (a0)261; CHECK-NEXT: vle32.v v20, (a1)262; CHECK-NEXT: vwmul.vv v8, v16, v20263; CHECK-NEXT: ret264 %a = load <16 x i32>, ptr %x265 %b = load <16 x i32>, ptr %y266 %c = sext <16 x i32> %a to <16 x i64>267 %d = sext <16 x i32> %b to <16 x i64>268 %e = mul <16 x i64> %c, %d269 ret <16 x i64> %e270}271 272define <128 x i16> @vwmul_v128i16(ptr %x, ptr %y) {273; CHECK-LABEL: vwmul_v128i16:274; CHECK: # %bb.0:275; CHECK-NEXT: addi sp, sp, -16276; CHECK-NEXT: .cfi_def_cfa_offset 16277; CHECK-NEXT: csrr a2, vlenb278; CHECK-NEXT: slli a2, a2, 3279; CHECK-NEXT: sub sp, sp, a2280; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb281; CHECK-NEXT: li a2, 128282; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma283; CHECK-NEXT: vle8.v v16, (a0)284; CHECK-NEXT: vle8.v v24, (a1)285; CHECK-NEXT: li a0, 64286; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma287; CHECK-NEXT: vslidedown.vx v8, v16, a0288; CHECK-NEXT: addi a1, sp, 16289; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill290; CHECK-NEXT: vslidedown.vx v0, v24, a0291; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma292; CHECK-NEXT: vwmul.vv v8, v16, v24293; CHECK-NEXT: addi a0, sp, 16294; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload295; CHECK-NEXT: vwmul.vv v16, v24, v0296; CHECK-NEXT: csrr a0, vlenb297; CHECK-NEXT: slli a0, a0, 3298; CHECK-NEXT: add sp, sp, a0299; CHECK-NEXT: .cfi_def_cfa sp, 16300; CHECK-NEXT: addi sp, sp, 16301; CHECK-NEXT: .cfi_def_cfa_offset 0302; CHECK-NEXT: ret303 %a = load <128 x i8>, ptr %x304 %b = load <128 x i8>, ptr %y305 %c = sext <128 x i8> %a to <128 x i16>306 %d = sext <128 x i8> %b to <128 x i16>307 %e = mul <128 x i16> %c, %d308 ret <128 x i16> %e309}310 311define <64 x i32> @vwmul_v64i32(ptr %x, ptr %y) {312; CHECK-LABEL: vwmul_v64i32:313; CHECK: # %bb.0:314; CHECK-NEXT: addi sp, sp, -16315; CHECK-NEXT: .cfi_def_cfa_offset 16316; CHECK-NEXT: csrr a2, vlenb317; CHECK-NEXT: slli a2, a2, 3318; CHECK-NEXT: sub sp, sp, a2319; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb320; CHECK-NEXT: li a2, 64321; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma322; CHECK-NEXT: vle16.v v16, (a0)323; CHECK-NEXT: vle16.v v24, (a1)324; CHECK-NEXT: li a0, 32325; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma326; CHECK-NEXT: vslidedown.vx v8, v16, a0327; CHECK-NEXT: addi a1, sp, 16328; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill329; CHECK-NEXT: vslidedown.vx v0, v24, a0330; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma331; CHECK-NEXT: vwmul.vv v8, v16, v24332; CHECK-NEXT: addi a0, sp, 16333; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload334; CHECK-NEXT: vwmul.vv v16, v24, v0335; CHECK-NEXT: csrr a0, vlenb336; CHECK-NEXT: slli a0, a0, 3337; CHECK-NEXT: add sp, sp, a0338; CHECK-NEXT: .cfi_def_cfa sp, 16339; CHECK-NEXT: addi sp, sp, 16340; CHECK-NEXT: .cfi_def_cfa_offset 0341; CHECK-NEXT: ret342 %a = load <64 x i16>, ptr %x343 %b = load <64 x i16>, ptr %y344 %c = sext <64 x i16> %a to <64 x i32>345 %d = sext <64 x i16> %b to <64 x i32>346 %e = mul <64 x i32> %c, %d347 ret <64 x i32> %e348}349 350define <32 x i64> @vwmul_v32i64(ptr %x, ptr %y) {351; CHECK-LABEL: vwmul_v32i64:352; CHECK: # %bb.0:353; CHECK-NEXT: addi sp, sp, -16354; CHECK-NEXT: .cfi_def_cfa_offset 16355; CHECK-NEXT: csrr a2, vlenb356; CHECK-NEXT: slli a2, a2, 3357; CHECK-NEXT: sub sp, sp, a2358; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb359; CHECK-NEXT: li a2, 32360; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma361; CHECK-NEXT: vle32.v v16, (a0)362; CHECK-NEXT: vle32.v v24, (a1)363; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma364; CHECK-NEXT: vslidedown.vi v8, v16, 16365; CHECK-NEXT: addi a0, sp, 16366; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill367; CHECK-NEXT: vslidedown.vi v0, v24, 16368; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma369; CHECK-NEXT: vwmul.vv v8, v16, v24370; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload371; CHECK-NEXT: vwmul.vv v16, v24, v0372; CHECK-NEXT: csrr a0, vlenb373; CHECK-NEXT: slli a0, a0, 3374; CHECK-NEXT: add sp, sp, a0375; CHECK-NEXT: .cfi_def_cfa sp, 16376; CHECK-NEXT: addi sp, sp, 16377; CHECK-NEXT: .cfi_def_cfa_offset 0378; CHECK-NEXT: ret379 %a = load <32 x i32>, ptr %x380 %b = load <32 x i32>, ptr %y381 %c = sext <32 x i32> %a to <32 x i64>382 %d = sext <32 x i32> %b to <32 x i64>383 %e = mul <32 x i64> %c, %d384 ret <32 x i64> %e385}386 387define <2 x i32> @vwmul_v2i32_v2i8(ptr %x, ptr %y) {388; CHECK-LABEL: vwmul_v2i32_v2i8:389; CHECK: # %bb.0:390; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma391; CHECK-NEXT: vle8.v v8, (a0)392; CHECK-NEXT: vle8.v v9, (a1)393; CHECK-NEXT: vsext.vf2 v10, v8394; CHECK-NEXT: vsext.vf2 v11, v9395; CHECK-NEXT: vwmul.vv v8, v10, v11396; CHECK-NEXT: ret397 %a = load <2 x i8>, ptr %x398 %b = load <2 x i8>, ptr %y399 %c = sext <2 x i8> %a to <2 x i32>400 %d = sext <2 x i8> %b to <2 x i32>401 %e = mul <2 x i32> %c, %d402 ret <2 x i32> %e403}404 405define <4 x i32> @vwmul_v4i32_v4i8_v4i16(ptr %x, ptr %y) {406; CHECK-LABEL: vwmul_v4i32_v4i8_v4i16:407; CHECK: # %bb.0:408; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma409; CHECK-NEXT: vle8.v v8, (a0)410; CHECK-NEXT: vle16.v v9, (a1)411; CHECK-NEXT: vsext.vf2 v10, v8412; CHECK-NEXT: vwmul.vv v8, v10, v9413; CHECK-NEXT: ret414 %a = load <4 x i8>, ptr %x415 %b = load <4 x i16>, ptr %y416 %c = sext <4 x i8> %a to <4 x i32>417 %d = sext <4 x i16> %b to <4 x i32>418 %e = mul <4 x i32> %c, %d419 ret <4 x i32> %e420}421 422define <4 x i64> @vwmul_v4i64_v4i32_v4i8(ptr %x, ptr %y) {423; CHECK-LABEL: vwmul_v4i64_v4i32_v4i8:424; CHECK: # %bb.0:425; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma426; CHECK-NEXT: vle8.v v8, (a1)427; CHECK-NEXT: vle32.v v10, (a0)428; CHECK-NEXT: vsext.vf4 v11, v8429; CHECK-NEXT: vwmul.vv v8, v10, v11430; CHECK-NEXT: ret431 %a = load <4 x i32>, ptr %x432 %b = load <4 x i8>, ptr %y433 %c = sext <4 x i32> %a to <4 x i64>434 %d = sext <4 x i8> %b to <4 x i64>435 %e = mul <4 x i64> %c, %d436 ret <4 x i64> %e437}438 439define <2 x i16> @vwmul_vx_v2i16(ptr %x, i8 %y) {440; CHECK-LABEL: vwmul_vx_v2i16:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma443; CHECK-NEXT: vle8.v v9, (a0)444; CHECK-NEXT: vwmul.vx v8, v9, a1445; CHECK-NEXT: ret446 %a = load <2 x i8>, ptr %x447 %b = insertelement <2 x i8> poison, i8 %y, i32 0448 %c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer449 %d = sext <2 x i8> %a to <2 x i16>450 %e = sext <2 x i8> %c to <2 x i16>451 %f = mul <2 x i16> %d, %e452 ret <2 x i16> %f453}454 455define <4 x i16> @vwmul_vx_v4i16(ptr %x, i8 %y) {456; CHECK-LABEL: vwmul_vx_v4i16:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma459; CHECK-NEXT: vle8.v v9, (a0)460; CHECK-NEXT: vwmul.vx v8, v9, a1461; CHECK-NEXT: ret462 %a = load <4 x i8>, ptr %x463 %b = insertelement <4 x i8> poison, i8 %y, i32 0464 %c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer465 %d = sext <4 x i8> %a to <4 x i16>466 %e = sext <4 x i8> %c to <4 x i16>467 %f = mul <4 x i16> %d, %e468 ret <4 x i16> %f469}470 471define <2 x i32> @vwmul_vx_v2i32(ptr %x, i16 %y) {472; CHECK-LABEL: vwmul_vx_v2i32:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma475; CHECK-NEXT: vle16.v v9, (a0)476; CHECK-NEXT: vwmul.vx v8, v9, a1477; CHECK-NEXT: ret478 %a = load <2 x i16>, ptr %x479 %b = insertelement <2 x i16> poison, i16 %y, i32 0480 %c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer481 %d = sext <2 x i16> %a to <2 x i32>482 %e = sext <2 x i16> %c to <2 x i32>483 %f = mul <2 x i32> %d, %e484 ret <2 x i32> %f485}486 487define <8 x i16> @vwmul_vx_v8i16(ptr %x, i8 %y) {488; CHECK-LABEL: vwmul_vx_v8i16:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma491; CHECK-NEXT: vle8.v v9, (a0)492; CHECK-NEXT: vwmul.vx v8, v9, a1493; CHECK-NEXT: ret494 %a = load <8 x i8>, ptr %x495 %b = insertelement <8 x i8> poison, i8 %y, i32 0496 %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer497 %d = sext <8 x i8> %a to <8 x i16>498 %e = sext <8 x i8> %c to <8 x i16>499 %f = mul <8 x i16> %d, %e500 ret <8 x i16> %f501}502 503define <4 x i32> @vwmul_vx_v4i32(ptr %x, i16 %y) {504; CHECK-LABEL: vwmul_vx_v4i32:505; CHECK: # %bb.0:506; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma507; CHECK-NEXT: vle16.v v9, (a0)508; CHECK-NEXT: vwmul.vx v8, v9, a1509; CHECK-NEXT: ret510 %a = load <4 x i16>, ptr %x511 %b = insertelement <4 x i16> poison, i16 %y, i32 0512 %c = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer513 %d = sext <4 x i16> %a to <4 x i32>514 %e = sext <4 x i16> %c to <4 x i32>515 %f = mul <4 x i32> %d, %e516 ret <4 x i32> %f517}518 519define <2 x i64> @vwmul_vx_v2i64(ptr %x, i32 %y) {520; CHECK-LABEL: vwmul_vx_v2i64:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma523; CHECK-NEXT: vle32.v v9, (a0)524; CHECK-NEXT: vwmul.vx v8, v9, a1525; CHECK-NEXT: ret526 %a = load <2 x i32>, ptr %x527 %b = insertelement <2 x i32> poison, i32 %y, i64 0528 %c = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer529 %d = sext <2 x i32> %a to <2 x i64>530 %e = sext <2 x i32> %c to <2 x i64>531 %f = mul <2 x i64> %d, %e532 ret <2 x i64> %f533}534 535define <16 x i16> @vwmul_vx_v16i16(ptr %x, i8 %y) {536; CHECK-LABEL: vwmul_vx_v16i16:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma539; CHECK-NEXT: vle8.v v10, (a0)540; CHECK-NEXT: vwmul.vx v8, v10, a1541; CHECK-NEXT: ret542 %a = load <16 x i8>, ptr %x543 %b = insertelement <16 x i8> poison, i8 %y, i32 0544 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer545 %d = sext <16 x i8> %a to <16 x i16>546 %e = sext <16 x i8> %c to <16 x i16>547 %f = mul <16 x i16> %d, %e548 ret <16 x i16> %f549}550 551define <8 x i32> @vwmul_vx_v8i32(ptr %x, i16 %y) {552; CHECK-LABEL: vwmul_vx_v8i32:553; CHECK: # %bb.0:554; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma555; CHECK-NEXT: vle16.v v10, (a0)556; CHECK-NEXT: vwmul.vx v8, v10, a1557; CHECK-NEXT: ret558 %a = load <8 x i16>, ptr %x559 %b = insertelement <8 x i16> poison, i16 %y, i32 0560 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer561 %d = sext <8 x i16> %a to <8 x i32>562 %e = sext <8 x i16> %c to <8 x i32>563 %f = mul <8 x i32> %d, %e564 ret <8 x i32> %f565}566 567define <4 x i64> @vwmul_vx_v4i64(ptr %x, i32 %y) {568; CHECK-LABEL: vwmul_vx_v4i64:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma571; CHECK-NEXT: vle32.v v10, (a0)572; CHECK-NEXT: vwmul.vx v8, v10, a1573; CHECK-NEXT: ret574 %a = load <4 x i32>, ptr %x575 %b = insertelement <4 x i32> poison, i32 %y, i64 0576 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer577 %d = sext <4 x i32> %a to <4 x i64>578 %e = sext <4 x i32> %c to <4 x i64>579 %f = mul <4 x i64> %d, %e580 ret <4 x i64> %f581}582 583define <32 x i16> @vwmul_vx_v32i16(ptr %x, i8 %y) {584; CHECK-LABEL: vwmul_vx_v32i16:585; CHECK: # %bb.0:586; CHECK-NEXT: li a2, 32587; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma588; CHECK-NEXT: vle8.v v12, (a0)589; CHECK-NEXT: vwmul.vx v8, v12, a1590; CHECK-NEXT: ret591 %a = load <32 x i8>, ptr %x592 %b = insertelement <32 x i8> poison, i8 %y, i32 0593 %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer594 %d = sext <32 x i8> %a to <32 x i16>595 %e = sext <32 x i8> %c to <32 x i16>596 %f = mul <32 x i16> %d, %e597 ret <32 x i16> %f598}599 600define <16 x i32> @vwmul_vx_v16i32(ptr %x, i16 %y) {601; CHECK-LABEL: vwmul_vx_v16i32:602; CHECK: # %bb.0:603; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma604; CHECK-NEXT: vle16.v v12, (a0)605; CHECK-NEXT: vwmul.vx v8, v12, a1606; CHECK-NEXT: ret607 %a = load <16 x i16>, ptr %x608 %b = insertelement <16 x i16> poison, i16 %y, i32 0609 %c = shufflevector <16 x i16> %b, <16 x i16> poison, <16 x i32> zeroinitializer610 %d = sext <16 x i16> %a to <16 x i32>611 %e = sext <16 x i16> %c to <16 x i32>612 %f = mul <16 x i32> %d, %e613 ret <16 x i32> %f614}615 616define <8 x i64> @vwmul_vx_v8i64(ptr %x, i32 %y) {617; CHECK-LABEL: vwmul_vx_v8i64:618; CHECK: # %bb.0:619; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma620; CHECK-NEXT: vle32.v v12, (a0)621; CHECK-NEXT: vwmul.vx v8, v12, a1622; CHECK-NEXT: ret623 %a = load <8 x i32>, ptr %x624 %b = insertelement <8 x i32> poison, i32 %y, i64 0625 %c = shufflevector <8 x i32> %b, <8 x i32> poison, <8 x i32> zeroinitializer626 %d = sext <8 x i32> %a to <8 x i64>627 %e = sext <8 x i32> %c to <8 x i64>628 %f = mul <8 x i64> %d, %e629 ret <8 x i64> %f630}631 632define <64 x i16> @vwmul_vx_v64i16(ptr %x, i8 %y) {633; CHECK-LABEL: vwmul_vx_v64i16:634; CHECK: # %bb.0:635; CHECK-NEXT: li a2, 64636; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma637; CHECK-NEXT: vle8.v v16, (a0)638; CHECK-NEXT: vwmul.vx v8, v16, a1639; CHECK-NEXT: ret640 %a = load <64 x i8>, ptr %x641 %b = insertelement <64 x i8> poison, i8 %y, i32 0642 %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer643 %d = sext <64 x i8> %a to <64 x i16>644 %e = sext <64 x i8> %c to <64 x i16>645 %f = mul <64 x i16> %d, %e646 ret <64 x i16> %f647}648 649define <32 x i32> @vwmul_vx_v32i32(ptr %x, i16 %y) {650; CHECK-LABEL: vwmul_vx_v32i32:651; CHECK: # %bb.0:652; CHECK-NEXT: li a2, 32653; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma654; CHECK-NEXT: vle16.v v16, (a0)655; CHECK-NEXT: vwmul.vx v8, v16, a1656; CHECK-NEXT: ret657 %a = load <32 x i16>, ptr %x658 %b = insertelement <32 x i16> poison, i16 %y, i32 0659 %c = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer660 %d = sext <32 x i16> %a to <32 x i32>661 %e = sext <32 x i16> %c to <32 x i32>662 %f = mul <32 x i32> %d, %e663 ret <32 x i32> %f664}665 666define <16 x i64> @vwmul_vx_v16i64(ptr %x, i32 %y) {667; CHECK-LABEL: vwmul_vx_v16i64:668; CHECK: # %bb.0:669; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma670; CHECK-NEXT: vle32.v v16, (a0)671; CHECK-NEXT: vwmul.vx v8, v16, a1672; CHECK-NEXT: ret673 %a = load <16 x i32>, ptr %x674 %b = insertelement <16 x i32> poison, i32 %y, i64 0675 %c = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer676 %d = sext <16 x i32> %a to <16 x i64>677 %e = sext <16 x i32> %c to <16 x i64>678 %f = mul <16 x i64> %d, %e679 ret <16 x i64> %f680}681 682define <8 x i16> @vwmul_vx_v8i16_i8(ptr %x, ptr %y) {683; CHECK-LABEL: vwmul_vx_v8i16_i8:684; CHECK: # %bb.0:685; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma686; CHECK-NEXT: vle8.v v9, (a0)687; CHECK-NEXT: lb a0, 0(a1)688; CHECK-NEXT: vwmul.vx v8, v9, a0689; CHECK-NEXT: ret690 %a = load <8 x i8>, ptr %x691 %b = load i8, ptr %y692 %c = sext i8 %b to i16693 %d = insertelement <8 x i16> poison, i16 %c, i32 0694 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer695 %f = sext <8 x i8> %a to <8 x i16>696 %g = mul <8 x i16> %e, %f697 ret <8 x i16> %g698}699 700define <8 x i16> @vwmul_vx_v8i16_i16(ptr %x, ptr %y) {701; CHECK-LABEL: vwmul_vx_v8i16_i16:702; CHECK: # %bb.0:703; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma704; CHECK-NEXT: vle8.v v8, (a0)705; CHECK-NEXT: lh a0, 0(a1)706; CHECK-NEXT: vsext.vf2 v9, v8707; CHECK-NEXT: vmul.vx v8, v9, a0708; CHECK-NEXT: ret709 %a = load <8 x i8>, ptr %x710 %b = load i16, ptr %y711 %d = insertelement <8 x i16> poison, i16 %b, i32 0712 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer713 %f = sext <8 x i8> %a to <8 x i16>714 %g = mul <8 x i16> %e, %f715 ret <8 x i16> %g716}717 718define <4 x i32> @vwmul_vx_v4i32_i8(ptr %x, ptr %y) {719; CHECK-LABEL: vwmul_vx_v4i32_i8:720; CHECK: # %bb.0:721; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma722; CHECK-NEXT: vle16.v v9, (a0)723; CHECK-NEXT: lb a0, 0(a1)724; CHECK-NEXT: vwmul.vx v8, v9, a0725; CHECK-NEXT: ret726 %a = load <4 x i16>, ptr %x727 %b = load i8, ptr %y728 %c = sext i8 %b to i32729 %d = insertelement <4 x i32> poison, i32 %c, i32 0730 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer731 %f = sext <4 x i16> %a to <4 x i32>732 %g = mul <4 x i32> %e, %f733 ret <4 x i32> %g734}735 736define <4 x i32> @vwmul_vx_v4i32_i16(ptr %x, ptr %y) {737; CHECK-LABEL: vwmul_vx_v4i32_i16:738; CHECK: # %bb.0:739; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma740; CHECK-NEXT: vle16.v v9, (a0)741; CHECK-NEXT: lh a0, 0(a1)742; CHECK-NEXT: vwmul.vx v8, v9, a0743; CHECK-NEXT: ret744 %a = load <4 x i16>, ptr %x745 %b = load i16, ptr %y746 %c = sext i16 %b to i32747 %d = insertelement <4 x i32> poison, i32 %c, i32 0748 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer749 %f = sext <4 x i16> %a to <4 x i32>750 %g = mul <4 x i32> %e, %f751 ret <4 x i32> %g752}753 754define <4 x i32> @vwmul_vx_v4i32_i32(ptr %x, ptr %y) {755; CHECK-LABEL: vwmul_vx_v4i32_i32:756; CHECK: # %bb.0:757; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma758; CHECK-NEXT: vle16.v v8, (a0)759; CHECK-NEXT: lw a0, 0(a1)760; CHECK-NEXT: vsext.vf2 v9, v8761; CHECK-NEXT: vmul.vx v8, v9, a0762; CHECK-NEXT: ret763 %a = load <4 x i16>, ptr %x764 %b = load i32, ptr %y765 %d = insertelement <4 x i32> poison, i32 %b, i32 0766 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer767 %f = sext <4 x i16> %a to <4 x i32>768 %g = mul <4 x i32> %e, %f769 ret <4 x i32> %g770}771 772define <2 x i64> @vwmul_vx_v2i64_i8(ptr %x, ptr %y) {773; CHECK-LABEL: vwmul_vx_v2i64_i8:774; CHECK: # %bb.0:775; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma776; CHECK-NEXT: vle32.v v9, (a0)777; CHECK-NEXT: lb a0, 0(a1)778; CHECK-NEXT: vwmul.vx v8, v9, a0779; CHECK-NEXT: ret780 %a = load <2 x i32>, ptr %x781 %b = load i8, ptr %y782 %c = sext i8 %b to i64783 %d = insertelement <2 x i64> poison, i64 %c, i64 0784 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer785 %f = sext <2 x i32> %a to <2 x i64>786 %g = mul <2 x i64> %e, %f787 ret <2 x i64> %g788}789 790define <2 x i64> @vwmul_vx_v2i64_i16(ptr %x, ptr %y) {791; CHECK-LABEL: vwmul_vx_v2i64_i16:792; CHECK: # %bb.0:793; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma794; CHECK-NEXT: vle32.v v9, (a0)795; CHECK-NEXT: lh a0, 0(a1)796; CHECK-NEXT: vwmul.vx v8, v9, a0797; CHECK-NEXT: ret798 %a = load <2 x i32>, ptr %x799 %b = load i16, ptr %y800 %c = sext i16 %b to i64801 %d = insertelement <2 x i64> poison, i64 %c, i64 0802 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer803 %f = sext <2 x i32> %a to <2 x i64>804 %g = mul <2 x i64> %e, %f805 ret <2 x i64> %g806}807 808define <2 x i64> @vwmul_vx_v2i64_i32(ptr %x, ptr %y) {809; CHECK-LABEL: vwmul_vx_v2i64_i32:810; CHECK: # %bb.0:811; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma812; CHECK-NEXT: vle32.v v9, (a0)813; CHECK-NEXT: lw a0, 0(a1)814; CHECK-NEXT: vwmul.vx v8, v9, a0815; CHECK-NEXT: ret816 %a = load <2 x i32>, ptr %x817 %b = load i32, ptr %y818 %c = sext i32 %b to i64819 %d = insertelement <2 x i64> poison, i64 %c, i64 0820 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer821 %f = sext <2 x i32> %a to <2 x i64>822 %g = mul <2 x i64> %e, %f823 ret <2 x i64> %g824}825 826define <2 x i64> @vwmul_vx_v2i64_i64(ptr %x, ptr %y) {827; RV32-LABEL: vwmul_vx_v2i64_i64:828; RV32: # %bb.0:829; RV32-NEXT: addi sp, sp, -16830; RV32-NEXT: .cfi_def_cfa_offset 16831; RV32-NEXT: lw a2, 0(a1)832; RV32-NEXT: lw a1, 4(a1)833; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma834; RV32-NEXT: vle32.v v8, (a0)835; RV32-NEXT: sw a2, 8(sp)836; RV32-NEXT: sw a1, 12(sp)837; RV32-NEXT: addi a0, sp, 8838; RV32-NEXT: vlse64.v v9, (a0), zero839; RV32-NEXT: vsext.vf2 v10, v8840; RV32-NEXT: vmul.vv v8, v9, v10841; RV32-NEXT: addi sp, sp, 16842; RV32-NEXT: .cfi_def_cfa_offset 0843; RV32-NEXT: ret844;845; RV64-LABEL: vwmul_vx_v2i64_i64:846; RV64: # %bb.0:847; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma848; RV64-NEXT: vle32.v v8, (a0)849; RV64-NEXT: ld a0, 0(a1)850; RV64-NEXT: vsext.vf2 v9, v8851; RV64-NEXT: vmul.vx v8, v9, a0852; RV64-NEXT: ret853 %a = load <2 x i32>, ptr %x854 %b = load i64, ptr %y855 %d = insertelement <2 x i64> poison, i64 %b, i64 0856 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer857 %f = sext <2 x i32> %a to <2 x i64>858 %g = mul <2 x i64> %e, %f859 ret <2 x i64> %g860}861 862define <2 x i16> @vwmul_v2i16_multiuse(ptr %x, ptr %y, ptr %z, ptr %w) {863; CHECK-LABEL: vwmul_v2i16_multiuse:864; CHECK: # %bb.0:865; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma866; CHECK-NEXT: vle8.v v8, (a1)867; CHECK-NEXT: vle8.v v9, (a2)868; CHECK-NEXT: vsext.vf2 v10, v8869; CHECK-NEXT: vsext.vf2 v8, v9870; CHECK-NEXT: vdivu.vv v8, v10, v8871; CHECK-NEXT: vle8.v v9, (a0)872; CHECK-NEXT: vle8.v v11, (a3)873; CHECK-NEXT: vsext.vf2 v12, v9874; CHECK-NEXT: vsext.vf2 v9, v11875; CHECK-NEXT: vmul.vv v11, v12, v9876; CHECK-NEXT: vmul.vv v9, v10, v9877; CHECK-NEXT: vor.vv v9, v11, v9878; CHECK-NEXT: vor.vv v8, v9, v8879; CHECK-NEXT: ret880 %a = load <2 x i8>, ptr %x881 %b = load <2 x i8>, ptr %y882 %c = load <2 x i8>, ptr %z883 %d = load <2 x i8>, ptr %w884 885 %as = sext <2 x i8> %a to <2 x i16>886 %bs = sext <2 x i8> %b to <2 x i16>887 %cs = sext <2 x i8> %c to <2 x i16>888 %ds = sext <2 x i8> %d to <2 x i16>889 890 %e = mul <2 x i16> %as, %ds891 %f = mul <2 x i16> %bs, %ds ; shares 1 use with %e892 %g = udiv <2 x i16> %bs, %cs ; shares 1 use with %f, and no uses with %e893 894 %h = or <2 x i16> %e, %f895 %i = or <2 x i16> %h, %g896 ret <2 x i16> %i897}898