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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <2 x i16> @vwmulsu_v2i16(ptr %x, ptr %y) {6; CHECK-LABEL: vwmulsu_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vle8.v v9, (a0)10; CHECK-NEXT: vle8.v v10, (a1)11; CHECK-NEXT: vwmulsu.vv v8, v10, v912; CHECK-NEXT: ret13 %a = load <2 x i8>, ptr %x14 %b = load <2 x i8>, ptr %y15 %c = zext <2 x i8> %a to <2 x i16>16 %d = sext <2 x i8> %b to <2 x i16>17 %e = mul <2 x i16> %c, %d18 ret <2 x i16> %e19}20 21define <2 x i16> @vwmulsu_v2i16_swap(ptr %x, ptr %y) {22; CHECK-LABEL: vwmulsu_v2i16_swap:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma25; CHECK-NEXT: vle8.v v9, (a0)26; CHECK-NEXT: vle8.v v10, (a1)27; CHECK-NEXT: vwmulsu.vv v8, v9, v1028; CHECK-NEXT: ret29 %a = load <2 x i8>, ptr %x30 %b = load <2 x i8>, ptr %y31 %c = sext <2 x i8> %a to <2 x i16>32 %d = zext <2 x i8> %b to <2 x i16>33 %e = mul <2 x i16> %c, %d34 ret <2 x i16> %e35}36 37define <4 x i16> @vwmulsu_v4i16(ptr %x, ptr %y) {38; CHECK-LABEL: vwmulsu_v4i16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma41; CHECK-NEXT: vle8.v v9, (a0)42; CHECK-NEXT: vle8.v v10, (a1)43; CHECK-NEXT: vwmulsu.vv v8, v10, v944; CHECK-NEXT: ret45 %a = load <4 x i8>, ptr %x46 %b = load <4 x i8>, ptr %y47 %c = zext <4 x i8> %a to <4 x i16>48 %d = sext <4 x i8> %b to <4 x i16>49 %e = mul <4 x i16> %c, %d50 ret <4 x i16> %e51}52 53define <2 x i32> @vwmulsu_v2i32(ptr %x, ptr %y) {54; CHECK-LABEL: vwmulsu_v2i32:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma57; CHECK-NEXT: vle16.v v9, (a0)58; CHECK-NEXT: vle16.v v10, (a1)59; CHECK-NEXT: vwmulsu.vv v8, v10, v960; CHECK-NEXT: ret61 %a = load <2 x i16>, ptr %x62 %b = load <2 x i16>, ptr %y63 %c = zext <2 x i16> %a to <2 x i32>64 %d = sext <2 x i16> %b to <2 x i32>65 %e = mul <2 x i32> %c, %d66 ret <2 x i32> %e67}68 69define <8 x i16> @vwmulsu_v8i16(ptr %x, ptr %y) {70; CHECK-LABEL: vwmulsu_v8i16:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma73; CHECK-NEXT: vle8.v v9, (a0)74; CHECK-NEXT: vle8.v v10, (a1)75; CHECK-NEXT: vwmulsu.vv v8, v10, v976; CHECK-NEXT: ret77 %a = load <8 x i8>, ptr %x78 %b = load <8 x i8>, ptr %y79 %c = zext <8 x i8> %a to <8 x i16>80 %d = sext <8 x i8> %b to <8 x i16>81 %e = mul <8 x i16> %c, %d82 ret <8 x i16> %e83}84 85define <4 x i32> @vwmulsu_v4i32(ptr %x, ptr %y) {86; CHECK-LABEL: vwmulsu_v4i32:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma89; CHECK-NEXT: vle16.v v9, (a0)90; CHECK-NEXT: vle16.v v10, (a1)91; CHECK-NEXT: vwmulsu.vv v8, v10, v992; CHECK-NEXT: ret93 %a = load <4 x i16>, ptr %x94 %b = load <4 x i16>, ptr %y95 %c = zext <4 x i16> %a to <4 x i32>96 %d = sext <4 x i16> %b to <4 x i32>97 %e = mul <4 x i32> %c, %d98 ret <4 x i32> %e99}100 101define <2 x i64> @vwmulsu_v2i64(ptr %x, ptr %y) {102; CHECK-LABEL: vwmulsu_v2i64:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma105; CHECK-NEXT: vle32.v v9, (a0)106; CHECK-NEXT: vle32.v v10, (a1)107; CHECK-NEXT: vwmulsu.vv v8, v10, v9108; CHECK-NEXT: ret109 %a = load <2 x i32>, ptr %x110 %b = load <2 x i32>, ptr %y111 %c = zext <2 x i32> %a to <2 x i64>112 %d = sext <2 x i32> %b to <2 x i64>113 %e = mul <2 x i64> %c, %d114 ret <2 x i64> %e115}116 117define <16 x i16> @vwmulsu_v16i16(ptr %x, ptr %y) {118; CHECK-LABEL: vwmulsu_v16i16:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma121; CHECK-NEXT: vle8.v v10, (a0)122; CHECK-NEXT: vle8.v v11, (a1)123; CHECK-NEXT: vwmulsu.vv v8, v11, v10124; CHECK-NEXT: ret125 %a = load <16 x i8>, ptr %x126 %b = load <16 x i8>, ptr %y127 %c = zext <16 x i8> %a to <16 x i16>128 %d = sext <16 x i8> %b to <16 x i16>129 %e = mul <16 x i16> %c, %d130 ret <16 x i16> %e131}132 133define <8 x i32> @vwmulsu_v8i32(ptr %x, ptr %y) {134; CHECK-LABEL: vwmulsu_v8i32:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma137; CHECK-NEXT: vle16.v v10, (a0)138; CHECK-NEXT: vle16.v v11, (a1)139; CHECK-NEXT: vwmulsu.vv v8, v11, v10140; CHECK-NEXT: ret141 %a = load <8 x i16>, ptr %x142 %b = load <8 x i16>, ptr %y143 %c = zext <8 x i16> %a to <8 x i32>144 %d = sext <8 x i16> %b to <8 x i32>145 %e = mul <8 x i32> %c, %d146 ret <8 x i32> %e147}148 149define <4 x i64> @vwmulsu_v4i64(ptr %x, ptr %y) {150; CHECK-LABEL: vwmulsu_v4i64:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma153; CHECK-NEXT: vle32.v v10, (a0)154; CHECK-NEXT: vle32.v v11, (a1)155; CHECK-NEXT: vwmulsu.vv v8, v11, v10156; CHECK-NEXT: ret157 %a = load <4 x i32>, ptr %x158 %b = load <4 x i32>, ptr %y159 %c = zext <4 x i32> %a to <4 x i64>160 %d = sext <4 x i32> %b to <4 x i64>161 %e = mul <4 x i64> %c, %d162 ret <4 x i64> %e163}164 165define <32 x i16> @vwmulsu_v32i16(ptr %x, ptr %y) {166; CHECK-LABEL: vwmulsu_v32i16:167; CHECK: # %bb.0:168; CHECK-NEXT: li a2, 32169; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma170; CHECK-NEXT: vle8.v v12, (a0)171; CHECK-NEXT: vle8.v v14, (a1)172; CHECK-NEXT: vwmulsu.vv v8, v14, v12173; CHECK-NEXT: ret174 %a = load <32 x i8>, ptr %x175 %b = load <32 x i8>, ptr %y176 %c = zext <32 x i8> %a to <32 x i16>177 %d = sext <32 x i8> %b to <32 x i16>178 %e = mul <32 x i16> %c, %d179 ret <32 x i16> %e180}181 182define <16 x i32> @vwmulsu_v16i32(ptr %x, ptr %y) {183; CHECK-LABEL: vwmulsu_v16i32:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma186; CHECK-NEXT: vle16.v v12, (a0)187; CHECK-NEXT: vle16.v v14, (a1)188; CHECK-NEXT: vwmulsu.vv v8, v14, v12189; CHECK-NEXT: ret190 %a = load <16 x i16>, ptr %x191 %b = load <16 x i16>, ptr %y192 %c = zext <16 x i16> %a to <16 x i32>193 %d = sext <16 x i16> %b to <16 x i32>194 %e = mul <16 x i32> %c, %d195 ret <16 x i32> %e196}197 198define <8 x i64> @vwmulsu_v8i64(ptr %x, ptr %y) {199; CHECK-LABEL: vwmulsu_v8i64:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma202; CHECK-NEXT: vle32.v v12, (a0)203; CHECK-NEXT: vle32.v v14, (a1)204; CHECK-NEXT: vwmulsu.vv v8, v14, v12205; CHECK-NEXT: ret206 %a = load <8 x i32>, ptr %x207 %b = load <8 x i32>, ptr %y208 %c = zext <8 x i32> %a to <8 x i64>209 %d = sext <8 x i32> %b to <8 x i64>210 %e = mul <8 x i64> %c, %d211 ret <8 x i64> %e212}213 214define <64 x i16> @vwmulsu_v64i16(ptr %x, ptr %y) {215; CHECK-LABEL: vwmulsu_v64i16:216; CHECK: # %bb.0:217; CHECK-NEXT: li a2, 64218; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma219; CHECK-NEXT: vle8.v v16, (a0)220; CHECK-NEXT: vle8.v v20, (a1)221; CHECK-NEXT: vwmulsu.vv v8, v20, v16222; CHECK-NEXT: ret223 %a = load <64 x i8>, ptr %x224 %b = load <64 x i8>, ptr %y225 %c = zext <64 x i8> %a to <64 x i16>226 %d = sext <64 x i8> %b to <64 x i16>227 %e = mul <64 x i16> %c, %d228 ret <64 x i16> %e229}230 231define <32 x i32> @vwmulsu_v32i32(ptr %x, ptr %y) {232; CHECK-LABEL: vwmulsu_v32i32:233; CHECK: # %bb.0:234; CHECK-NEXT: li a2, 32235; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma236; CHECK-NEXT: vle16.v v16, (a0)237; CHECK-NEXT: vle16.v v20, (a1)238; CHECK-NEXT: vwmulsu.vv v8, v20, v16239; CHECK-NEXT: ret240 %a = load <32 x i16>, ptr %x241 %b = load <32 x i16>, ptr %y242 %c = zext <32 x i16> %a to <32 x i32>243 %d = sext <32 x i16> %b to <32 x i32>244 %e = mul <32 x i32> %c, %d245 ret <32 x i32> %e246}247 248define <16 x i64> @vwmulsu_v16i64(ptr %x, ptr %y) {249; CHECK-LABEL: vwmulsu_v16i64:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma252; CHECK-NEXT: vle32.v v16, (a0)253; CHECK-NEXT: vle32.v v20, (a1)254; CHECK-NEXT: vwmulsu.vv v8, v20, v16255; CHECK-NEXT: ret256 %a = load <16 x i32>, ptr %x257 %b = load <16 x i32>, ptr %y258 %c = zext <16 x i32> %a to <16 x i64>259 %d = sext <16 x i32> %b to <16 x i64>260 %e = mul <16 x i64> %c, %d261 ret <16 x i64> %e262}263 264define <128 x i16> @vwmulsu_v128i16(ptr %x, ptr %y) {265; CHECK-LABEL: vwmulsu_v128i16:266; CHECK: # %bb.0:267; CHECK-NEXT: addi sp, sp, -16268; CHECK-NEXT: .cfi_def_cfa_offset 16269; CHECK-NEXT: csrr a2, vlenb270; CHECK-NEXT: slli a2, a2, 3271; CHECK-NEXT: sub sp, sp, a2272; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb273; CHECK-NEXT: li a2, 128274; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma275; CHECK-NEXT: vle8.v v16, (a0)276; CHECK-NEXT: vle8.v v24, (a1)277; CHECK-NEXT: li a0, 64278; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma279; CHECK-NEXT: vslidedown.vx v8, v16, a0280; CHECK-NEXT: addi a1, sp, 16281; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill282; CHECK-NEXT: vslidedown.vx v0, v24, a0283; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma284; CHECK-NEXT: vwmulsu.vv v8, v24, v16285; CHECK-NEXT: addi a0, sp, 16286; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload287; CHECK-NEXT: vwmulsu.vv v16, v0, v24288; CHECK-NEXT: csrr a0, vlenb289; CHECK-NEXT: slli a0, a0, 3290; CHECK-NEXT: add sp, sp, a0291; CHECK-NEXT: .cfi_def_cfa sp, 16292; CHECK-NEXT: addi sp, sp, 16293; CHECK-NEXT: .cfi_def_cfa_offset 0294; CHECK-NEXT: ret295 %a = load <128 x i8>, ptr %x296 %b = load <128 x i8>, ptr %y297 %c = zext <128 x i8> %a to <128 x i16>298 %d = sext <128 x i8> %b to <128 x i16>299 %e = mul <128 x i16> %c, %d300 ret <128 x i16> %e301}302 303define <64 x i32> @vwmulsu_v64i32(ptr %x, ptr %y) {304; CHECK-LABEL: vwmulsu_v64i32:305; CHECK: # %bb.0:306; CHECK-NEXT: addi sp, sp, -16307; CHECK-NEXT: .cfi_def_cfa_offset 16308; CHECK-NEXT: csrr a2, vlenb309; CHECK-NEXT: slli a2, a2, 3310; CHECK-NEXT: sub sp, sp, a2311; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb312; CHECK-NEXT: li a2, 64313; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma314; CHECK-NEXT: vle16.v v16, (a0)315; CHECK-NEXT: vle16.v v24, (a1)316; CHECK-NEXT: li a0, 32317; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma318; CHECK-NEXT: vslidedown.vx v8, v16, a0319; CHECK-NEXT: addi a1, sp, 16320; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill321; CHECK-NEXT: vslidedown.vx v0, v24, a0322; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma323; CHECK-NEXT: vwmulsu.vv v8, v24, v16324; CHECK-NEXT: addi a0, sp, 16325; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload326; CHECK-NEXT: vwmulsu.vv v16, v0, v24327; CHECK-NEXT: csrr a0, vlenb328; CHECK-NEXT: slli a0, a0, 3329; CHECK-NEXT: add sp, sp, a0330; CHECK-NEXT: .cfi_def_cfa sp, 16331; CHECK-NEXT: addi sp, sp, 16332; CHECK-NEXT: .cfi_def_cfa_offset 0333; CHECK-NEXT: ret334 %a = load <64 x i16>, ptr %x335 %b = load <64 x i16>, ptr %y336 %c = zext <64 x i16> %a to <64 x i32>337 %d = sext <64 x i16> %b to <64 x i32>338 %e = mul <64 x i32> %c, %d339 ret <64 x i32> %e340}341 342define <32 x i64> @vwmulsu_v32i64(ptr %x, ptr %y) {343; CHECK-LABEL: vwmulsu_v32i64:344; CHECK: # %bb.0:345; CHECK-NEXT: addi sp, sp, -16346; CHECK-NEXT: .cfi_def_cfa_offset 16347; CHECK-NEXT: csrr a2, vlenb348; CHECK-NEXT: slli a2, a2, 3349; CHECK-NEXT: sub sp, sp, a2350; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb351; CHECK-NEXT: li a2, 32352; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma353; CHECK-NEXT: vle32.v v16, (a0)354; CHECK-NEXT: vle32.v v24, (a1)355; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma356; CHECK-NEXT: vslidedown.vi v8, v16, 16357; CHECK-NEXT: addi a0, sp, 16358; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill359; CHECK-NEXT: vslidedown.vi v0, v24, 16360; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma361; CHECK-NEXT: vwmulsu.vv v8, v24, v16362; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload363; CHECK-NEXT: vwmulsu.vv v16, v0, v24364; CHECK-NEXT: csrr a0, vlenb365; CHECK-NEXT: slli a0, a0, 3366; CHECK-NEXT: add sp, sp, a0367; CHECK-NEXT: .cfi_def_cfa sp, 16368; CHECK-NEXT: addi sp, sp, 16369; CHECK-NEXT: .cfi_def_cfa_offset 0370; CHECK-NEXT: ret371 %a = load <32 x i32>, ptr %x372 %b = load <32 x i32>, ptr %y373 %c = zext <32 x i32> %a to <32 x i64>374 %d = sext <32 x i32> %b to <32 x i64>375 %e = mul <32 x i64> %c, %d376 ret <32 x i64> %e377}378 379define <2 x i32> @vwmulsu_v2i32_v2i8(ptr %x, ptr %y) {380; CHECK-LABEL: vwmulsu_v2i32_v2i8:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma383; CHECK-NEXT: vle8.v v8, (a0)384; CHECK-NEXT: vle8.v v9, (a1)385; CHECK-NEXT: vzext.vf2 v10, v8386; CHECK-NEXT: vsext.vf2 v11, v9387; CHECK-NEXT: vwmulsu.vv v8, v11, v10388; CHECK-NEXT: ret389 %a = load <2 x i8>, ptr %x390 %b = load <2 x i8>, ptr %y391 %c = zext <2 x i8> %a to <2 x i32>392 %d = sext <2 x i8> %b to <2 x i32>393 %e = mul <2 x i32> %c, %d394 ret <2 x i32> %e395}396 397define <4 x i32> @vwmulsu_v4i32_v4i8_v4i16(ptr %x, ptr %y) {398; CHECK-LABEL: vwmulsu_v4i32_v4i8_v4i16:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma401; CHECK-NEXT: vle8.v v8, (a0)402; CHECK-NEXT: vle16.v v9, (a1)403; CHECK-NEXT: vzext.vf2 v10, v8404; CHECK-NEXT: vwmulsu.vv v8, v9, v10405; CHECK-NEXT: ret406 %a = load <4 x i8>, ptr %x407 %b = load <4 x i16>, ptr %y408 %c = zext <4 x i8> %a to <4 x i32>409 %d = sext <4 x i16> %b to <4 x i32>410 %e = mul <4 x i32> %c, %d411 ret <4 x i32> %e412}413 414define <4 x i64> @vwmulsu_v4i64_v4i32_v4i8(ptr %x, ptr %y) {415; CHECK-LABEL: vwmulsu_v4i64_v4i32_v4i8:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma418; CHECK-NEXT: vle8.v v8, (a1)419; CHECK-NEXT: vle32.v v10, (a0)420; CHECK-NEXT: vsext.vf4 v11, v8421; CHECK-NEXT: vwmulsu.vv v8, v11, v10422; CHECK-NEXT: ret423 %a = load <4 x i32>, ptr %x424 %b = load <4 x i8>, ptr %y425 %c = zext <4 x i32> %a to <4 x i64>426 %d = sext <4 x i8> %b to <4 x i64>427 %e = mul <4 x i64> %c, %d428 ret <4 x i64> %e429}430 431define <2 x i16> @vwmulsu_vx_v2i16(ptr %x, i8 %y) {432; CHECK-LABEL: vwmulsu_vx_v2i16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma435; CHECK-NEXT: vle8.v v9, (a0)436; CHECK-NEXT: vwmulsu.vx v8, v9, a1437; CHECK-NEXT: ret438 %a = load <2 x i8>, ptr %x439 %b = insertelement <2 x i8> poison, i8 %y, i32 0440 %c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer441 %d = sext <2 x i8> %a to <2 x i16>442 %e = zext <2 x i8> %c to <2 x i16>443 %f = mul <2 x i16> %d, %e444 ret <2 x i16> %f445}446 447define <2 x i16> @vwmulsu_vx_v2i16_swap(ptr %x, i8 %y) {448; CHECK-LABEL: vwmulsu_vx_v2i16_swap:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma451; CHECK-NEXT: vle8.v v9, (a0)452; CHECK-NEXT: vmv.v.x v10, a1453; CHECK-NEXT: vwmulsu.vv v8, v10, v9454; CHECK-NEXT: ret455 %a = load <2 x i8>, ptr %x456 %b = insertelement <2 x i8> poison, i8 %y, i32 0457 %c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer458 %d = zext <2 x i8> %a to <2 x i16>459 %e = sext <2 x i8> %c to <2 x i16>460 %f = mul <2 x i16> %d, %e461 ret <2 x i16> %f462}463 464define <4 x i16> @vwmulsu_vx_v4i16(ptr %x, i8 %y) {465; CHECK-LABEL: vwmulsu_vx_v4i16:466; CHECK: # %bb.0:467; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma468; CHECK-NEXT: vle8.v v9, (a0)469; CHECK-NEXT: vwmulsu.vx v8, v9, a1470; CHECK-NEXT: ret471 %a = load <4 x i8>, ptr %x472 %b = insertelement <4 x i8> poison, i8 %y, i32 0473 %c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer474 %d = sext <4 x i8> %a to <4 x i16>475 %e = zext <4 x i8> %c to <4 x i16>476 %f = mul <4 x i16> %d, %e477 ret <4 x i16> %f478}479 480define <2 x i32> @vwmulsu_vx_v2i32(ptr %x, i16 %y) {481; CHECK-LABEL: vwmulsu_vx_v2i32:482; CHECK: # %bb.0:483; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma484; CHECK-NEXT: vle16.v v9, (a0)485; CHECK-NEXT: vwmulsu.vx v8, v9, a1486; CHECK-NEXT: ret487 %a = load <2 x i16>, ptr %x488 %b = insertelement <2 x i16> poison, i16 %y, i32 0489 %c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer490 %d = sext <2 x i16> %a to <2 x i32>491 %e = zext <2 x i16> %c to <2 x i32>492 %f = mul <2 x i32> %d, %e493 ret <2 x i32> %f494}495 496define <8 x i16> @vwmulsu_vx_v8i16(ptr %x, i8 %y) {497; CHECK-LABEL: vwmulsu_vx_v8i16:498; CHECK: # %bb.0:499; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma500; CHECK-NEXT: vle8.v v9, (a0)501; CHECK-NEXT: vwmulsu.vx v8, v9, a1502; CHECK-NEXT: ret503 %a = load <8 x i8>, ptr %x504 %b = insertelement <8 x i8> poison, i8 %y, i32 0505 %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer506 %d = sext <8 x i8> %a to <8 x i16>507 %e = zext <8 x i8> %c to <8 x i16>508 %f = mul <8 x i16> %d, %e509 ret <8 x i16> %f510}511 512define <4 x i32> @vwmulsu_vx_v4i32(ptr %x, i16 %y) {513; CHECK-LABEL: vwmulsu_vx_v4i32:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma516; CHECK-NEXT: vle16.v v9, (a0)517; CHECK-NEXT: vwmulsu.vx v8, v9, a1518; CHECK-NEXT: ret519 %a = load <4 x i16>, ptr %x520 %b = insertelement <4 x i16> poison, i16 %y, i32 0521 %c = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer522 %d = sext <4 x i16> %a to <4 x i32>523 %e = zext <4 x i16> %c to <4 x i32>524 %f = mul <4 x i32> %d, %e525 ret <4 x i32> %f526}527 528define <2 x i64> @vwmulsu_vx_v2i64(ptr %x, i32 %y) {529; CHECK-LABEL: vwmulsu_vx_v2i64:530; CHECK: # %bb.0:531; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma532; CHECK-NEXT: vle32.v v9, (a0)533; CHECK-NEXT: vwmulsu.vx v8, v9, a1534; CHECK-NEXT: ret535 %a = load <2 x i32>, ptr %x536 %b = insertelement <2 x i32> poison, i32 %y, i64 0537 %c = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer538 %d = sext <2 x i32> %a to <2 x i64>539 %e = zext <2 x i32> %c to <2 x i64>540 %f = mul <2 x i64> %d, %e541 ret <2 x i64> %f542}543 544define <16 x i16> @vwmulsu_vx_v16i16(ptr %x, i8 %y) {545; CHECK-LABEL: vwmulsu_vx_v16i16:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma548; CHECK-NEXT: vle8.v v10, (a0)549; CHECK-NEXT: vwmulsu.vx v8, v10, a1550; CHECK-NEXT: ret551 %a = load <16 x i8>, ptr %x552 %b = insertelement <16 x i8> poison, i8 %y, i32 0553 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer554 %d = sext <16 x i8> %a to <16 x i16>555 %e = zext <16 x i8> %c to <16 x i16>556 %f = mul <16 x i16> %d, %e557 ret <16 x i16> %f558}559 560define <8 x i32> @vwmulsu_vx_v8i32(ptr %x, i16 %y) {561; CHECK-LABEL: vwmulsu_vx_v8i32:562; CHECK: # %bb.0:563; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma564; CHECK-NEXT: vle16.v v10, (a0)565; CHECK-NEXT: vwmulsu.vx v8, v10, a1566; CHECK-NEXT: ret567 %a = load <8 x i16>, ptr %x568 %b = insertelement <8 x i16> poison, i16 %y, i32 0569 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer570 %d = sext <8 x i16> %a to <8 x i32>571 %e = zext <8 x i16> %c to <8 x i32>572 %f = mul <8 x i32> %d, %e573 ret <8 x i32> %f574}575 576define <4 x i64> @vwmulsu_vx_v4i64(ptr %x, i32 %y) {577; CHECK-LABEL: vwmulsu_vx_v4i64:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma580; CHECK-NEXT: vle32.v v10, (a0)581; CHECK-NEXT: vwmulsu.vx v8, v10, a1582; CHECK-NEXT: ret583 %a = load <4 x i32>, ptr %x584 %b = insertelement <4 x i32> poison, i32 %y, i64 0585 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer586 %d = sext <4 x i32> %a to <4 x i64>587 %e = zext <4 x i32> %c to <4 x i64>588 %f = mul <4 x i64> %d, %e589 ret <4 x i64> %f590}591 592define <32 x i16> @vwmulsu_vx_v32i16(ptr %x, i8 %y) {593; CHECK-LABEL: vwmulsu_vx_v32i16:594; CHECK: # %bb.0:595; CHECK-NEXT: li a2, 32596; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma597; CHECK-NEXT: vle8.v v12, (a0)598; CHECK-NEXT: vwmulsu.vx v8, v12, a1599; CHECK-NEXT: ret600 %a = load <32 x i8>, ptr %x601 %b = insertelement <32 x i8> poison, i8 %y, i32 0602 %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer603 %d = sext <32 x i8> %a to <32 x i16>604 %e = zext <32 x i8> %c to <32 x i16>605 %f = mul <32 x i16> %d, %e606 ret <32 x i16> %f607}608 609define <16 x i32> @vwmulsu_vx_v16i32(ptr %x, i16 %y) {610; CHECK-LABEL: vwmulsu_vx_v16i32:611; CHECK: # %bb.0:612; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma613; CHECK-NEXT: vle16.v v12, (a0)614; CHECK-NEXT: vwmulsu.vx v8, v12, a1615; CHECK-NEXT: ret616 %a = load <16 x i16>, ptr %x617 %b = insertelement <16 x i16> poison, i16 %y, i32 0618 %c = shufflevector <16 x i16> %b, <16 x i16> poison, <16 x i32> zeroinitializer619 %d = sext <16 x i16> %a to <16 x i32>620 %e = zext <16 x i16> %c to <16 x i32>621 %f = mul <16 x i32> %d, %e622 ret <16 x i32> %f623}624 625define <8 x i64> @vwmulsu_vx_v8i64(ptr %x, i32 %y) {626; CHECK-LABEL: vwmulsu_vx_v8i64:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma629; CHECK-NEXT: vle32.v v12, (a0)630; CHECK-NEXT: vwmulsu.vx v8, v12, a1631; CHECK-NEXT: ret632 %a = load <8 x i32>, ptr %x633 %b = insertelement <8 x i32> poison, i32 %y, i64 0634 %c = shufflevector <8 x i32> %b, <8 x i32> poison, <8 x i32> zeroinitializer635 %d = sext <8 x i32> %a to <8 x i64>636 %e = zext <8 x i32> %c to <8 x i64>637 %f = mul <8 x i64> %d, %e638 ret <8 x i64> %f639}640 641define <64 x i16> @vwmulsu_vx_v64i16(ptr %x, i8 %y) {642; CHECK-LABEL: vwmulsu_vx_v64i16:643; CHECK: # %bb.0:644; CHECK-NEXT: li a2, 64645; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma646; CHECK-NEXT: vle8.v v16, (a0)647; CHECK-NEXT: vwmulsu.vx v8, v16, a1648; CHECK-NEXT: ret649 %a = load <64 x i8>, ptr %x650 %b = insertelement <64 x i8> poison, i8 %y, i32 0651 %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer652 %d = sext <64 x i8> %a to <64 x i16>653 %e = zext <64 x i8> %c to <64 x i16>654 %f = mul <64 x i16> %d, %e655 ret <64 x i16> %f656}657 658define <32 x i32> @vwmulsu_vx_v32i32(ptr %x, i16 %y) {659; CHECK-LABEL: vwmulsu_vx_v32i32:660; CHECK: # %bb.0:661; CHECK-NEXT: li a2, 32662; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma663; CHECK-NEXT: vle16.v v16, (a0)664; CHECK-NEXT: vwmulsu.vx v8, v16, a1665; CHECK-NEXT: ret666 %a = load <32 x i16>, ptr %x667 %b = insertelement <32 x i16> poison, i16 %y, i32 0668 %c = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer669 %d = sext <32 x i16> %a to <32 x i32>670 %e = zext <32 x i16> %c to <32 x i32>671 %f = mul <32 x i32> %d, %e672 ret <32 x i32> %f673}674 675define <16 x i64> @vwmulsu_vx_v16i64(ptr %x, i32 %y) {676; CHECK-LABEL: vwmulsu_vx_v16i64:677; CHECK: # %bb.0:678; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma679; CHECK-NEXT: vle32.v v16, (a0)680; CHECK-NEXT: vwmulsu.vx v8, v16, a1681; CHECK-NEXT: ret682 %a = load <16 x i32>, ptr %x683 %b = insertelement <16 x i32> poison, i32 %y, i64 0684 %c = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer685 %d = sext <16 x i32> %a to <16 x i64>686 %e = zext <16 x i32> %c to <16 x i64>687 %f = mul <16 x i64> %d, %e688 ret <16 x i64> %f689}690 691define <8 x i16> @vwmulsu_vx_v8i16_i8(ptr %x, ptr %y) {692; CHECK-LABEL: vwmulsu_vx_v8i16_i8:693; CHECK: # %bb.0:694; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma695; CHECK-NEXT: vle8.v v9, (a0)696; CHECK-NEXT: lbu a0, 0(a1)697; CHECK-NEXT: vwmulsu.vx v8, v9, a0698; CHECK-NEXT: ret699 %a = load <8 x i8>, ptr %x700 %b = load i8, ptr %y701 %c = zext i8 %b to i16702 %d = insertelement <8 x i16> poison, i16 %c, i32 0703 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer704 %f = sext <8 x i8> %a to <8 x i16>705 %g = mul <8 x i16> %e, %f706 ret <8 x i16> %g707}708 709define <8 x i16> @vwmulsu_vx_v8i16_i8_swap(ptr %x, ptr %y) {710; CHECK-LABEL: vwmulsu_vx_v8i16_i8_swap:711; CHECK: # %bb.0:712; CHECK-NEXT: lb a1, 0(a1)713; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma714; CHECK-NEXT: vle8.v v9, (a0)715; CHECK-NEXT: vmv.v.x v10, a1716; CHECK-NEXT: vwmulsu.vv v8, v10, v9717; CHECK-NEXT: ret718 %a = load <8 x i8>, ptr %x719 %b = load i8, ptr %y720 %c = sext i8 %b to i16721 %d = insertelement <8 x i16> poison, i16 %c, i32 0722 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer723 %f = zext <8 x i8> %a to <8 x i16>724 %g = mul <8 x i16> %e, %f725 ret <8 x i16> %g726}727 728define <4 x i32> @vwmulsu_vx_v4i32_i8(ptr %x, ptr %y) {729; CHECK-LABEL: vwmulsu_vx_v4i32_i8:730; CHECK: # %bb.0:731; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma732; CHECK-NEXT: vle16.v v9, (a0)733; CHECK-NEXT: lbu a0, 0(a1)734; CHECK-NEXT: vwmul.vx v8, v9, a0735; CHECK-NEXT: ret736 %a = load <4 x i16>, ptr %x737 %b = load i8, ptr %y738 %c = zext i8 %b to i32739 %d = insertelement <4 x i32> poison, i32 %c, i32 0740 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer741 %f = sext <4 x i16> %a to <4 x i32>742 %g = mul <4 x i32> %e, %f743 ret <4 x i32> %g744}745 746define <4 x i32> @vwmulsu_vx_v4i32_i16(ptr %x, ptr %y) {747; CHECK-LABEL: vwmulsu_vx_v4i32_i16:748; CHECK: # %bb.0:749; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma750; CHECK-NEXT: vle16.v v9, (a0)751; CHECK-NEXT: lhu a0, 0(a1)752; CHECK-NEXT: vwmulsu.vx v8, v9, a0753; CHECK-NEXT: ret754 %a = load <4 x i16>, ptr %x755 %b = load i16, ptr %y756 %c = zext i16 %b to i32757 %d = insertelement <4 x i32> poison, i32 %c, i32 0758 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer759 %f = sext <4 x i16> %a to <4 x i32>760 %g = mul <4 x i32> %e, %f761 ret <4 x i32> %g762}763 764define <2 x i64> @vwmulsu_vx_v2i64_i8(ptr %x, ptr %y) {765; RV32-LABEL: vwmulsu_vx_v2i64_i8:766; RV32: # %bb.0:767; RV32-NEXT: addi sp, sp, -16768; RV32-NEXT: .cfi_def_cfa_offset 16769; RV32-NEXT: lbu a1, 0(a1)770; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma771; RV32-NEXT: vle32.v v8, (a0)772; RV32-NEXT: sw a1, 8(sp)773; RV32-NEXT: sw zero, 12(sp)774; RV32-NEXT: addi a0, sp, 8775; RV32-NEXT: vlse64.v v9, (a0), zero776; RV32-NEXT: vsext.vf2 v10, v8777; RV32-NEXT: vmul.vv v8, v9, v10778; RV32-NEXT: addi sp, sp, 16779; RV32-NEXT: .cfi_def_cfa_offset 0780; RV32-NEXT: ret781;782; RV64-LABEL: vwmulsu_vx_v2i64_i8:783; RV64: # %bb.0:784; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma785; RV64-NEXT: vle32.v v9, (a0)786; RV64-NEXT: lbu a0, 0(a1)787; RV64-NEXT: vwmul.vx v8, v9, a0788; RV64-NEXT: ret789 %a = load <2 x i32>, ptr %x790 %b = load i8, ptr %y791 %c = zext i8 %b to i64792 %d = insertelement <2 x i64> poison, i64 %c, i64 0793 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer794 %f = sext <2 x i32> %a to <2 x i64>795 %g = mul <2 x i64> %e, %f796 ret <2 x i64> %g797}798 799define <2 x i64> @vwmulsu_vx_v2i64_i16(ptr %x, ptr %y) {800; RV32-LABEL: vwmulsu_vx_v2i64_i16:801; RV32: # %bb.0:802; RV32-NEXT: addi sp, sp, -16803; RV32-NEXT: .cfi_def_cfa_offset 16804; RV32-NEXT: lhu a1, 0(a1)805; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma806; RV32-NEXT: vle32.v v8, (a0)807; RV32-NEXT: sw a1, 8(sp)808; RV32-NEXT: sw zero, 12(sp)809; RV32-NEXT: addi a0, sp, 8810; RV32-NEXT: vlse64.v v9, (a0), zero811; RV32-NEXT: vsext.vf2 v10, v8812; RV32-NEXT: vmul.vv v8, v9, v10813; RV32-NEXT: addi sp, sp, 16814; RV32-NEXT: .cfi_def_cfa_offset 0815; RV32-NEXT: ret816;817; RV64-LABEL: vwmulsu_vx_v2i64_i16:818; RV64: # %bb.0:819; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma820; RV64-NEXT: vle32.v v9, (a0)821; RV64-NEXT: lhu a0, 0(a1)822; RV64-NEXT: vwmul.vx v8, v9, a0823; RV64-NEXT: ret824 %a = load <2 x i32>, ptr %x825 %b = load i16, ptr %y826 %c = zext i16 %b to i64827 %d = insertelement <2 x i64> poison, i64 %c, i64 0828 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer829 %f = sext <2 x i32> %a to <2 x i64>830 %g = mul <2 x i64> %e, %f831 ret <2 x i64> %g832}833 834define <2 x i64> @vwmulsu_vx_v2i64_i32(ptr %x, ptr %y) {835; RV32-LABEL: vwmulsu_vx_v2i64_i32:836; RV32: # %bb.0:837; RV32-NEXT: addi sp, sp, -16838; RV32-NEXT: .cfi_def_cfa_offset 16839; RV32-NEXT: lw a1, 0(a1)840; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma841; RV32-NEXT: vle32.v v8, (a0)842; RV32-NEXT: sw a1, 8(sp)843; RV32-NEXT: sw zero, 12(sp)844; RV32-NEXT: addi a0, sp, 8845; RV32-NEXT: vlse64.v v9, (a0), zero846; RV32-NEXT: vsext.vf2 v10, v8847; RV32-NEXT: vmul.vv v8, v9, v10848; RV32-NEXT: addi sp, sp, 16849; RV32-NEXT: .cfi_def_cfa_offset 0850; RV32-NEXT: ret851;852; RV64-LABEL: vwmulsu_vx_v2i64_i32:853; RV64: # %bb.0:854; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma855; RV64-NEXT: vle32.v v9, (a0)856; RV64-NEXT: lw a0, 0(a1)857; RV64-NEXT: vwmulsu.vx v8, v9, a0858; RV64-NEXT: ret859 %a = load <2 x i32>, ptr %x860 %b = load i32, ptr %y861 %c = zext i32 %b to i64862 %d = insertelement <2 x i64> poison, i64 %c, i64 0863 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer864 %f = sext <2 x i32> %a to <2 x i64>865 %g = mul <2 x i64> %e, %f866 ret <2 x i64> %g867}868 869define <8 x i16> @vwmulsu_vx_v8i16_i8_and(ptr %x, i16 %y) {870; CHECK-LABEL: vwmulsu_vx_v8i16_i8_and:871; CHECK: # %bb.0:872; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma873; CHECK-NEXT: vle8.v v9, (a0)874; CHECK-NEXT: vwmulsu.vx v8, v9, a1875; CHECK-NEXT: ret876 %a = load <8 x i8>, ptr %x877 %b = and i16 %y, 255878 %c = insertelement <8 x i16> poison, i16 %b, i32 0879 %d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> zeroinitializer880 %e = sext <8 x i8> %a to <8 x i16>881 %f = mul <8 x i16> %d, %e882 ret <8 x i16> %f883}884 885define <8 x i16> @vwmulsu_vx_v8i16_i8_and1(ptr %x, i16 %y) {886; CHECK-LABEL: vwmulsu_vx_v8i16_i8_and1:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma889; CHECK-NEXT: vle8.v v9, (a0)890; CHECK-NEXT: andi a0, a1, 254891; CHECK-NEXT: vwmulsu.vx v8, v9, a0892; CHECK-NEXT: ret893 %a = load <8 x i8>, ptr %x894 %b = and i16 %y, 254895 %c = insertelement <8 x i16> poison, i16 %b, i32 0896 %d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> zeroinitializer897 %e = sext <8 x i8> %a to <8 x i16>898 %f = mul <8 x i16> %d, %e899 ret <8 x i16> %f900}901 902define <4 x i32> @vwmulsu_vx_v4i32_i16_and(ptr %x, i32 %y) {903; CHECK-LABEL: vwmulsu_vx_v4i32_i16_and:904; CHECK: # %bb.0:905; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma906; CHECK-NEXT: vle16.v v9, (a0)907; CHECK-NEXT: vwmulsu.vx v8, v9, a1908; CHECK-NEXT: ret909 %a = load <4 x i16>, ptr %x910 %b = and i32 %y, 65535911 %c = insertelement <4 x i32> poison, i32 %b, i32 0912 %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> zeroinitializer913 %e = sext <4 x i16> %a to <4 x i32>914 %f = mul <4 x i32> %d, %e915 ret <4 x i32> %f916}917 918define <4 x i32> @vwmulsu_vx_v4i32_i16_zext(ptr %x, i16 %y) {919; CHECK-LABEL: vwmulsu_vx_v4i32_i16_zext:920; CHECK: # %bb.0:921; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma922; CHECK-NEXT: vle16.v v9, (a0)923; CHECK-NEXT: vwmulsu.vx v8, v9, a1924; CHECK-NEXT: ret925 %a = load <4 x i16>, ptr %x926 %b = zext i16 %y to i32927 %c = insertelement <4 x i32> poison, i32 %b, i32 0928 %d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> zeroinitializer929 %e = sext <4 x i16> %a to <4 x i32>930 %f = mul <4 x i32> %d, %e931 ret <4 x i32> %f932}933