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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s4 5define <2 x i16> @vwmulu_v2i16(ptr %x, ptr %y) {6; CHECK-LABEL: vwmulu_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vle8.v v9, (a0)10; CHECK-NEXT: vle8.v v10, (a1)11; CHECK-NEXT: vwmulu.vv v8, v9, v1012; CHECK-NEXT: ret13 %a = load <2 x i8>, ptr %x14 %b = load <2 x i8>, ptr %y15 %c = zext <2 x i8> %a to <2 x i16>16 %d = zext <2 x i8> %b to <2 x i16>17 %e = mul <2 x i16> %c, %d18 ret <2 x i16> %e19}20 21define <4 x i16> @vwmulu_v4i16(ptr %x, ptr %y) {22; CHECK-LABEL: vwmulu_v4i16:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma25; CHECK-NEXT: vle8.v v9, (a0)26; CHECK-NEXT: vle8.v v10, (a1)27; CHECK-NEXT: vwmulu.vv v8, v9, v1028; CHECK-NEXT: ret29 %a = load <4 x i8>, ptr %x30 %b = load <4 x i8>, ptr %y31 %c = zext <4 x i8> %a to <4 x i16>32 %d = zext <4 x i8> %b to <4 x i16>33 %e = mul <4 x i16> %c, %d34 ret <4 x i16> %e35}36 37define <2 x i32> @vwmulu_v2i32(ptr %x, ptr %y) {38; CHECK-LABEL: vwmulu_v2i32:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma41; CHECK-NEXT: vle16.v v9, (a0)42; CHECK-NEXT: vle16.v v10, (a1)43; CHECK-NEXT: vwmulu.vv v8, v9, v1044; CHECK-NEXT: ret45 %a = load <2 x i16>, ptr %x46 %b = load <2 x i16>, ptr %y47 %c = zext <2 x i16> %a to <2 x i32>48 %d = zext <2 x i16> %b to <2 x i32>49 %e = mul <2 x i32> %c, %d50 ret <2 x i32> %e51}52 53define <8 x i16> @vwmulu_v8i16(ptr %x, ptr %y) {54; CHECK-LABEL: vwmulu_v8i16:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma57; CHECK-NEXT: vle8.v v9, (a0)58; CHECK-NEXT: vle8.v v10, (a1)59; CHECK-NEXT: vwmulu.vv v8, v9, v1060; CHECK-NEXT: ret61 %a = load <8 x i8>, ptr %x62 %b = load <8 x i8>, ptr %y63 %c = zext <8 x i8> %a to <8 x i16>64 %d = zext <8 x i8> %b to <8 x i16>65 %e = mul <8 x i16> %c, %d66 ret <8 x i16> %e67}68 69define <4 x i32> @vwmulu_v4i32(ptr %x, ptr %y) {70; CHECK-LABEL: vwmulu_v4i32:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma73; CHECK-NEXT: vle16.v v9, (a0)74; CHECK-NEXT: vle16.v v10, (a1)75; CHECK-NEXT: vwmulu.vv v8, v9, v1076; CHECK-NEXT: ret77 %a = load <4 x i16>, ptr %x78 %b = load <4 x i16>, ptr %y79 %c = zext <4 x i16> %a to <4 x i32>80 %d = zext <4 x i16> %b to <4 x i32>81 %e = mul <4 x i32> %c, %d82 ret <4 x i32> %e83}84 85define <2 x i64> @vwmulu_v2i64(ptr %x, ptr %y) {86; CHECK-LABEL: vwmulu_v2i64:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma89; CHECK-NEXT: vle32.v v9, (a0)90; CHECK-NEXT: vle32.v v10, (a1)91; CHECK-NEXT: vwmulu.vv v8, v9, v1092; CHECK-NEXT: ret93 %a = load <2 x i32>, ptr %x94 %b = load <2 x i32>, ptr %y95 %c = zext <2 x i32> %a to <2 x i64>96 %d = zext <2 x i32> %b to <2 x i64>97 %e = mul <2 x i64> %c, %d98 ret <2 x i64> %e99}100 101define <16 x i16> @vwmulu_v16i16(ptr %x, ptr %y) {102; CHECK-LABEL: vwmulu_v16i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma105; CHECK-NEXT: vle8.v v10, (a0)106; CHECK-NEXT: vle8.v v11, (a1)107; CHECK-NEXT: vwmulu.vv v8, v10, v11108; CHECK-NEXT: ret109 %a = load <16 x i8>, ptr %x110 %b = load <16 x i8>, ptr %y111 %c = zext <16 x i8> %a to <16 x i16>112 %d = zext <16 x i8> %b to <16 x i16>113 %e = mul <16 x i16> %c, %d114 ret <16 x i16> %e115}116 117define <8 x i32> @vwmulu_v8i32(ptr %x, ptr %y) {118; CHECK-LABEL: vwmulu_v8i32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma121; CHECK-NEXT: vle16.v v10, (a0)122; CHECK-NEXT: vle16.v v11, (a1)123; CHECK-NEXT: vwmulu.vv v8, v10, v11124; CHECK-NEXT: ret125 %a = load <8 x i16>, ptr %x126 %b = load <8 x i16>, ptr %y127 %c = zext <8 x i16> %a to <8 x i32>128 %d = zext <8 x i16> %b to <8 x i32>129 %e = mul <8 x i32> %c, %d130 ret <8 x i32> %e131}132 133define <4 x i64> @vwmulu_v4i64(ptr %x, ptr %y) {134; CHECK-LABEL: vwmulu_v4i64:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma137; CHECK-NEXT: vle32.v v10, (a0)138; CHECK-NEXT: vle32.v v11, (a1)139; CHECK-NEXT: vwmulu.vv v8, v10, v11140; CHECK-NEXT: ret141 %a = load <4 x i32>, ptr %x142 %b = load <4 x i32>, ptr %y143 %c = zext <4 x i32> %a to <4 x i64>144 %d = zext <4 x i32> %b to <4 x i64>145 %e = mul <4 x i64> %c, %d146 ret <4 x i64> %e147}148 149define <32 x i16> @vwmulu_v32i16(ptr %x, ptr %y) {150; CHECK-LABEL: vwmulu_v32i16:151; CHECK: # %bb.0:152; CHECK-NEXT: li a2, 32153; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma154; CHECK-NEXT: vle8.v v12, (a0)155; CHECK-NEXT: vle8.v v14, (a1)156; CHECK-NEXT: vwmulu.vv v8, v12, v14157; CHECK-NEXT: ret158 %a = load <32 x i8>, ptr %x159 %b = load <32 x i8>, ptr %y160 %c = zext <32 x i8> %a to <32 x i16>161 %d = zext <32 x i8> %b to <32 x i16>162 %e = mul <32 x i16> %c, %d163 ret <32 x i16> %e164}165 166define <16 x i32> @vwmulu_v16i32(ptr %x, ptr %y) {167; CHECK-LABEL: vwmulu_v16i32:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma170; CHECK-NEXT: vle16.v v12, (a0)171; CHECK-NEXT: vle16.v v14, (a1)172; CHECK-NEXT: vwmulu.vv v8, v12, v14173; CHECK-NEXT: ret174 %a = load <16 x i16>, ptr %x175 %b = load <16 x i16>, ptr %y176 %c = zext <16 x i16> %a to <16 x i32>177 %d = zext <16 x i16> %b to <16 x i32>178 %e = mul <16 x i32> %c, %d179 ret <16 x i32> %e180}181 182define <8 x i64> @vwmulu_v8i64(ptr %x, ptr %y) {183; CHECK-LABEL: vwmulu_v8i64:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma186; CHECK-NEXT: vle32.v v12, (a0)187; CHECK-NEXT: vle32.v v14, (a1)188; CHECK-NEXT: vwmulu.vv v8, v12, v14189; CHECK-NEXT: ret190 %a = load <8 x i32>, ptr %x191 %b = load <8 x i32>, ptr %y192 %c = zext <8 x i32> %a to <8 x i64>193 %d = zext <8 x i32> %b to <8 x i64>194 %e = mul <8 x i64> %c, %d195 ret <8 x i64> %e196}197 198define <64 x i16> @vwmulu_v64i16(ptr %x, ptr %y) {199; CHECK-LABEL: vwmulu_v64i16:200; CHECK: # %bb.0:201; CHECK-NEXT: li a2, 64202; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma203; CHECK-NEXT: vle8.v v16, (a0)204; CHECK-NEXT: vle8.v v20, (a1)205; CHECK-NEXT: vwmulu.vv v8, v16, v20206; CHECK-NEXT: ret207 %a = load <64 x i8>, ptr %x208 %b = load <64 x i8>, ptr %y209 %c = zext <64 x i8> %a to <64 x i16>210 %d = zext <64 x i8> %b to <64 x i16>211 %e = mul <64 x i16> %c, %d212 ret <64 x i16> %e213}214 215define <32 x i32> @vwmulu_v32i32(ptr %x, ptr %y) {216; CHECK-LABEL: vwmulu_v32i32:217; CHECK: # %bb.0:218; CHECK-NEXT: li a2, 32219; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma220; CHECK-NEXT: vle16.v v16, (a0)221; CHECK-NEXT: vle16.v v20, (a1)222; CHECK-NEXT: vwmulu.vv v8, v16, v20223; CHECK-NEXT: ret224 %a = load <32 x i16>, ptr %x225 %b = load <32 x i16>, ptr %y226 %c = zext <32 x i16> %a to <32 x i32>227 %d = zext <32 x i16> %b to <32 x i32>228 %e = mul <32 x i32> %c, %d229 ret <32 x i32> %e230}231 232define <16 x i64> @vwmulu_v16i64(ptr %x, ptr %y) {233; CHECK-LABEL: vwmulu_v16i64:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma236; CHECK-NEXT: vle32.v v16, (a0)237; CHECK-NEXT: vle32.v v20, (a1)238; CHECK-NEXT: vwmulu.vv v8, v16, v20239; CHECK-NEXT: ret240 %a = load <16 x i32>, ptr %x241 %b = load <16 x i32>, ptr %y242 %c = zext <16 x i32> %a to <16 x i64>243 %d = zext <16 x i32> %b to <16 x i64>244 %e = mul <16 x i64> %c, %d245 ret <16 x i64> %e246}247 248define <128 x i16> @vwmulu_v128i16(ptr %x, ptr %y) {249; CHECK-LABEL: vwmulu_v128i16:250; CHECK: # %bb.0:251; CHECK-NEXT: addi sp, sp, -16252; CHECK-NEXT: .cfi_def_cfa_offset 16253; CHECK-NEXT: csrr a2, vlenb254; CHECK-NEXT: slli a2, a2, 3255; CHECK-NEXT: sub sp, sp, a2256; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb257; CHECK-NEXT: li a2, 128258; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma259; CHECK-NEXT: vle8.v v16, (a0)260; CHECK-NEXT: vle8.v v24, (a1)261; CHECK-NEXT: li a0, 64262; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma263; CHECK-NEXT: vslidedown.vx v8, v16, a0264; CHECK-NEXT: addi a1, sp, 16265; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill266; CHECK-NEXT: vslidedown.vx v0, v24, a0267; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma268; CHECK-NEXT: vwmulu.vv v8, v16, v24269; CHECK-NEXT: addi a0, sp, 16270; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload271; CHECK-NEXT: vwmulu.vv v16, v24, v0272; CHECK-NEXT: csrr a0, vlenb273; CHECK-NEXT: slli a0, a0, 3274; CHECK-NEXT: add sp, sp, a0275; CHECK-NEXT: .cfi_def_cfa sp, 16276; CHECK-NEXT: addi sp, sp, 16277; CHECK-NEXT: .cfi_def_cfa_offset 0278; CHECK-NEXT: ret279 %a = load <128 x i8>, ptr %x280 %b = load <128 x i8>, ptr %y281 %c = zext <128 x i8> %a to <128 x i16>282 %d = zext <128 x i8> %b to <128 x i16>283 %e = mul <128 x i16> %c, %d284 ret <128 x i16> %e285}286 287define <64 x i32> @vwmulu_v64i32(ptr %x, ptr %y) {288; CHECK-LABEL: vwmulu_v64i32:289; CHECK: # %bb.0:290; CHECK-NEXT: addi sp, sp, -16291; CHECK-NEXT: .cfi_def_cfa_offset 16292; CHECK-NEXT: csrr a2, vlenb293; CHECK-NEXT: slli a2, a2, 3294; CHECK-NEXT: sub sp, sp, a2295; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb296; CHECK-NEXT: li a2, 64297; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma298; CHECK-NEXT: vle16.v v16, (a0)299; CHECK-NEXT: vle16.v v24, (a1)300; CHECK-NEXT: li a0, 32301; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma302; CHECK-NEXT: vslidedown.vx v8, v16, a0303; CHECK-NEXT: addi a1, sp, 16304; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill305; CHECK-NEXT: vslidedown.vx v0, v24, a0306; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma307; CHECK-NEXT: vwmulu.vv v8, v16, v24308; CHECK-NEXT: addi a0, sp, 16309; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload310; CHECK-NEXT: vwmulu.vv v16, v24, v0311; CHECK-NEXT: csrr a0, vlenb312; CHECK-NEXT: slli a0, a0, 3313; CHECK-NEXT: add sp, sp, a0314; CHECK-NEXT: .cfi_def_cfa sp, 16315; CHECK-NEXT: addi sp, sp, 16316; CHECK-NEXT: .cfi_def_cfa_offset 0317; CHECK-NEXT: ret318 %a = load <64 x i16>, ptr %x319 %b = load <64 x i16>, ptr %y320 %c = zext <64 x i16> %a to <64 x i32>321 %d = zext <64 x i16> %b to <64 x i32>322 %e = mul <64 x i32> %c, %d323 ret <64 x i32> %e324}325 326define <32 x i64> @vwmulu_v32i64(ptr %x, ptr %y) {327; CHECK-LABEL: vwmulu_v32i64:328; CHECK: # %bb.0:329; CHECK-NEXT: addi sp, sp, -16330; CHECK-NEXT: .cfi_def_cfa_offset 16331; CHECK-NEXT: csrr a2, vlenb332; CHECK-NEXT: slli a2, a2, 3333; CHECK-NEXT: sub sp, sp, a2334; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb335; CHECK-NEXT: li a2, 32336; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma337; CHECK-NEXT: vle32.v v16, (a0)338; CHECK-NEXT: vle32.v v24, (a1)339; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma340; CHECK-NEXT: vslidedown.vi v8, v16, 16341; CHECK-NEXT: addi a0, sp, 16342; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill343; CHECK-NEXT: vslidedown.vi v0, v24, 16344; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma345; CHECK-NEXT: vwmulu.vv v8, v16, v24346; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload347; CHECK-NEXT: vwmulu.vv v16, v24, v0348; CHECK-NEXT: csrr a0, vlenb349; CHECK-NEXT: slli a0, a0, 3350; CHECK-NEXT: add sp, sp, a0351; CHECK-NEXT: .cfi_def_cfa sp, 16352; CHECK-NEXT: addi sp, sp, 16353; CHECK-NEXT: .cfi_def_cfa_offset 0354; CHECK-NEXT: ret355 %a = load <32 x i32>, ptr %x356 %b = load <32 x i32>, ptr %y357 %c = zext <32 x i32> %a to <32 x i64>358 %d = zext <32 x i32> %b to <32 x i64>359 %e = mul <32 x i64> %c, %d360 ret <32 x i64> %e361}362 363define <2 x i32> @vwmulu_v2i32_v2i8(ptr %x, ptr %y) {364; CHECK-LABEL: vwmulu_v2i32_v2i8:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma367; CHECK-NEXT: vle8.v v8, (a0)368; CHECK-NEXT: vle8.v v9, (a1)369; CHECK-NEXT: vwmulu.vv v10, v8, v9370; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma371; CHECK-NEXT: vzext.vf2 v8, v10372; CHECK-NEXT: ret373 %a = load <2 x i8>, ptr %x374 %b = load <2 x i8>, ptr %y375 %c = zext <2 x i8> %a to <2 x i32>376 %d = zext <2 x i8> %b to <2 x i32>377 %e = mul <2 x i32> %c, %d378 ret <2 x i32> %e379}380 381define <4 x i32> @vwmulu_v4i32_v4i8_v4i16(ptr %x, ptr %y) {382; CHECK-LABEL: vwmulu_v4i32_v4i8_v4i16:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma385; CHECK-NEXT: vle8.v v8, (a0)386; CHECK-NEXT: vle16.v v9, (a1)387; CHECK-NEXT: vzext.vf2 v10, v8388; CHECK-NEXT: vwmulu.vv v8, v10, v9389; CHECK-NEXT: ret390 %a = load <4 x i8>, ptr %x391 %b = load <4 x i16>, ptr %y392 %c = zext <4 x i8> %a to <4 x i32>393 %d = zext <4 x i16> %b to <4 x i32>394 %e = mul <4 x i32> %c, %d395 ret <4 x i32> %e396}397 398define <4 x i64> @vwmulu_v4i64_v4i32_v4i8(ptr %x, ptr %y) {399; CHECK-LABEL: vwmulu_v4i64_v4i32_v4i8:400; CHECK: # %bb.0:401; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma402; CHECK-NEXT: vle8.v v8, (a1)403; CHECK-NEXT: vle32.v v10, (a0)404; CHECK-NEXT: vzext.vf4 v11, v8405; CHECK-NEXT: vwmulu.vv v8, v10, v11406; CHECK-NEXT: ret407 %a = load <4 x i32>, ptr %x408 %b = load <4 x i8>, ptr %y409 %c = zext <4 x i32> %a to <4 x i64>410 %d = zext <4 x i8> %b to <4 x i64>411 %e = mul <4 x i64> %c, %d412 ret <4 x i64> %e413}414 415define <2 x i16> @vwmulu_vx_v2i16(ptr %x, i8 %y) {416; CHECK-LABEL: vwmulu_vx_v2i16:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma419; CHECK-NEXT: vle8.v v9, (a0)420; CHECK-NEXT: vwmulu.vx v8, v9, a1421; CHECK-NEXT: ret422 %a = load <2 x i8>, ptr %x423 %b = insertelement <2 x i8> poison, i8 %y, i32 0424 %c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer425 %d = zext <2 x i8> %a to <2 x i16>426 %e = zext <2 x i8> %c to <2 x i16>427 %f = mul <2 x i16> %d, %e428 ret <2 x i16> %f429}430 431define <4 x i16> @vwmulu_vx_v4i16(ptr %x, i8 %y) {432; CHECK-LABEL: vwmulu_vx_v4i16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma435; CHECK-NEXT: vle8.v v9, (a0)436; CHECK-NEXT: vwmulu.vx v8, v9, a1437; CHECK-NEXT: ret438 %a = load <4 x i8>, ptr %x439 %b = insertelement <4 x i8> poison, i8 %y, i32 0440 %c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer441 %d = zext <4 x i8> %a to <4 x i16>442 %e = zext <4 x i8> %c to <4 x i16>443 %f = mul <4 x i16> %d, %e444 ret <4 x i16> %f445}446 447define <2 x i32> @vwmulu_vx_v2i32(ptr %x, i16 %y) {448; CHECK-LABEL: vwmulu_vx_v2i32:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma451; CHECK-NEXT: vle16.v v9, (a0)452; CHECK-NEXT: vwmulu.vx v8, v9, a1453; CHECK-NEXT: ret454 %a = load <2 x i16>, ptr %x455 %b = insertelement <2 x i16> poison, i16 %y, i32 0456 %c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer457 %d = zext <2 x i16> %a to <2 x i32>458 %e = zext <2 x i16> %c to <2 x i32>459 %f = mul <2 x i32> %d, %e460 ret <2 x i32> %f461}462 463define <8 x i16> @vwmulu_vx_v8i16(ptr %x, i8 %y) {464; CHECK-LABEL: vwmulu_vx_v8i16:465; CHECK: # %bb.0:466; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma467; CHECK-NEXT: vle8.v v9, (a0)468; CHECK-NEXT: vwmulu.vx v8, v9, a1469; CHECK-NEXT: ret470 %a = load <8 x i8>, ptr %x471 %b = insertelement <8 x i8> poison, i8 %y, i32 0472 %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer473 %d = zext <8 x i8> %a to <8 x i16>474 %e = zext <8 x i8> %c to <8 x i16>475 %f = mul <8 x i16> %d, %e476 ret <8 x i16> %f477}478 479define <4 x i32> @vwmulu_vx_v4i32(ptr %x, i16 %y) {480; CHECK-LABEL: vwmulu_vx_v4i32:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma483; CHECK-NEXT: vle16.v v9, (a0)484; CHECK-NEXT: vwmulu.vx v8, v9, a1485; CHECK-NEXT: ret486 %a = load <4 x i16>, ptr %x487 %b = insertelement <4 x i16> poison, i16 %y, i32 0488 %c = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer489 %d = zext <4 x i16> %a to <4 x i32>490 %e = zext <4 x i16> %c to <4 x i32>491 %f = mul <4 x i32> %d, %e492 ret <4 x i32> %f493}494 495define <2 x i64> @vwmulu_vx_v2i64(ptr %x, i32 %y) {496; CHECK-LABEL: vwmulu_vx_v2i64:497; CHECK: # %bb.0:498; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma499; CHECK-NEXT: vle32.v v9, (a0)500; CHECK-NEXT: vwmulu.vx v8, v9, a1501; CHECK-NEXT: ret502 %a = load <2 x i32>, ptr %x503 %b = insertelement <2 x i32> poison, i32 %y, i64 0504 %c = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer505 %d = zext <2 x i32> %a to <2 x i64>506 %e = zext <2 x i32> %c to <2 x i64>507 %f = mul <2 x i64> %d, %e508 ret <2 x i64> %f509}510 511define <16 x i16> @vwmulu_vx_v16i16(ptr %x, i8 %y) {512; CHECK-LABEL: vwmulu_vx_v16i16:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma515; CHECK-NEXT: vle8.v v10, (a0)516; CHECK-NEXT: vwmulu.vx v8, v10, a1517; CHECK-NEXT: ret518 %a = load <16 x i8>, ptr %x519 %b = insertelement <16 x i8> poison, i8 %y, i32 0520 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer521 %d = zext <16 x i8> %a to <16 x i16>522 %e = zext <16 x i8> %c to <16 x i16>523 %f = mul <16 x i16> %d, %e524 ret <16 x i16> %f525}526 527define <8 x i32> @vwmulu_vx_v8i32(ptr %x, i16 %y) {528; CHECK-LABEL: vwmulu_vx_v8i32:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma531; CHECK-NEXT: vle16.v v10, (a0)532; CHECK-NEXT: vwmulu.vx v8, v10, a1533; CHECK-NEXT: ret534 %a = load <8 x i16>, ptr %x535 %b = insertelement <8 x i16> poison, i16 %y, i32 0536 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer537 %d = zext <8 x i16> %a to <8 x i32>538 %e = zext <8 x i16> %c to <8 x i32>539 %f = mul <8 x i32> %d, %e540 ret <8 x i32> %f541}542 543define <4 x i64> @vwmulu_vx_v4i64(ptr %x, i32 %y) {544; CHECK-LABEL: vwmulu_vx_v4i64:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma547; CHECK-NEXT: vle32.v v10, (a0)548; CHECK-NEXT: vwmulu.vx v8, v10, a1549; CHECK-NEXT: ret550 %a = load <4 x i32>, ptr %x551 %b = insertelement <4 x i32> poison, i32 %y, i64 0552 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer553 %d = zext <4 x i32> %a to <4 x i64>554 %e = zext <4 x i32> %c to <4 x i64>555 %f = mul <4 x i64> %d, %e556 ret <4 x i64> %f557}558 559define <32 x i16> @vwmulu_vx_v32i16(ptr %x, i8 %y) {560; CHECK-LABEL: vwmulu_vx_v32i16:561; CHECK: # %bb.0:562; CHECK-NEXT: li a2, 32563; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma564; CHECK-NEXT: vle8.v v12, (a0)565; CHECK-NEXT: vwmulu.vx v8, v12, a1566; CHECK-NEXT: ret567 %a = load <32 x i8>, ptr %x568 %b = insertelement <32 x i8> poison, i8 %y, i32 0569 %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer570 %d = zext <32 x i8> %a to <32 x i16>571 %e = zext <32 x i8> %c to <32 x i16>572 %f = mul <32 x i16> %d, %e573 ret <32 x i16> %f574}575 576define <16 x i32> @vwmulu_vx_v16i32(ptr %x, i16 %y) {577; CHECK-LABEL: vwmulu_vx_v16i32:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma580; CHECK-NEXT: vle16.v v12, (a0)581; CHECK-NEXT: vwmulu.vx v8, v12, a1582; CHECK-NEXT: ret583 %a = load <16 x i16>, ptr %x584 %b = insertelement <16 x i16> poison, i16 %y, i32 0585 %c = shufflevector <16 x i16> %b, <16 x i16> poison, <16 x i32> zeroinitializer586 %d = zext <16 x i16> %a to <16 x i32>587 %e = zext <16 x i16> %c to <16 x i32>588 %f = mul <16 x i32> %d, %e589 ret <16 x i32> %f590}591 592define <8 x i64> @vwmulu_vx_v8i64(ptr %x, i32 %y) {593; CHECK-LABEL: vwmulu_vx_v8i64:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma596; CHECK-NEXT: vle32.v v12, (a0)597; CHECK-NEXT: vwmulu.vx v8, v12, a1598; CHECK-NEXT: ret599 %a = load <8 x i32>, ptr %x600 %b = insertelement <8 x i32> poison, i32 %y, i64 0601 %c = shufflevector <8 x i32> %b, <8 x i32> poison, <8 x i32> zeroinitializer602 %d = zext <8 x i32> %a to <8 x i64>603 %e = zext <8 x i32> %c to <8 x i64>604 %f = mul <8 x i64> %d, %e605 ret <8 x i64> %f606}607 608define <64 x i16> @vwmulu_vx_v64i16(ptr %x, i8 %y) {609; CHECK-LABEL: vwmulu_vx_v64i16:610; CHECK: # %bb.0:611; CHECK-NEXT: li a2, 64612; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma613; CHECK-NEXT: vle8.v v16, (a0)614; CHECK-NEXT: vwmulu.vx v8, v16, a1615; CHECK-NEXT: ret616 %a = load <64 x i8>, ptr %x617 %b = insertelement <64 x i8> poison, i8 %y, i32 0618 %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer619 %d = zext <64 x i8> %a to <64 x i16>620 %e = zext <64 x i8> %c to <64 x i16>621 %f = mul <64 x i16> %d, %e622 ret <64 x i16> %f623}624 625define <32 x i32> @vwmulu_vx_v32i32(ptr %x, i16 %y) {626; CHECK-LABEL: vwmulu_vx_v32i32:627; CHECK: # %bb.0:628; CHECK-NEXT: li a2, 32629; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma630; CHECK-NEXT: vle16.v v16, (a0)631; CHECK-NEXT: vwmulu.vx v8, v16, a1632; CHECK-NEXT: ret633 %a = load <32 x i16>, ptr %x634 %b = insertelement <32 x i16> poison, i16 %y, i32 0635 %c = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer636 %d = zext <32 x i16> %a to <32 x i32>637 %e = zext <32 x i16> %c to <32 x i32>638 %f = mul <32 x i32> %d, %e639 ret <32 x i32> %f640}641 642define <16 x i64> @vwmulu_vx_v16i64(ptr %x, i32 %y) {643; CHECK-LABEL: vwmulu_vx_v16i64:644; CHECK: # %bb.0:645; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma646; CHECK-NEXT: vle32.v v16, (a0)647; CHECK-NEXT: vwmulu.vx v8, v16, a1648; CHECK-NEXT: ret649 %a = load <16 x i32>, ptr %x650 %b = insertelement <16 x i32> poison, i32 %y, i64 0651 %c = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer652 %d = zext <16 x i32> %a to <16 x i64>653 %e = zext <16 x i32> %c to <16 x i64>654 %f = mul <16 x i64> %d, %e655 ret <16 x i64> %f656}657 658define <8 x i16> @vwmulu_vx_v8i16_i8(ptr %x, ptr %y) {659; CHECK-LABEL: vwmulu_vx_v8i16_i8:660; CHECK: # %bb.0:661; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma662; CHECK-NEXT: vle8.v v9, (a0)663; CHECK-NEXT: lbu a0, 0(a1)664; CHECK-NEXT: vwmulu.vx v8, v9, a0665; CHECK-NEXT: ret666 %a = load <8 x i8>, ptr %x667 %b = load i8, ptr %y668 %c = zext i8 %b to i16669 %d = insertelement <8 x i16> poison, i16 %c, i32 0670 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer671 %f = zext <8 x i8> %a to <8 x i16>672 %g = mul <8 x i16> %e, %f673 ret <8 x i16> %g674}675 676define <8 x i16> @vwmulu_vx_v8i16_i16(ptr %x, ptr %y) {677; CHECK-LABEL: vwmulu_vx_v8i16_i16:678; CHECK: # %bb.0:679; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma680; CHECK-NEXT: vle8.v v8, (a0)681; CHECK-NEXT: lh a0, 0(a1)682; CHECK-NEXT: vzext.vf2 v9, v8683; CHECK-NEXT: vmul.vx v8, v9, a0684; CHECK-NEXT: ret685 %a = load <8 x i8>, ptr %x686 %b = load i16, ptr %y687 %d = insertelement <8 x i16> poison, i16 %b, i32 0688 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer689 %f = zext <8 x i8> %a to <8 x i16>690 %g = mul <8 x i16> %e, %f691 ret <8 x i16> %g692}693 694define <4 x i32> @vwmulu_vx_v4i32_i8(ptr %x, ptr %y) {695; CHECK-LABEL: vwmulu_vx_v4i32_i8:696; CHECK: # %bb.0:697; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma698; CHECK-NEXT: vle16.v v9, (a0)699; CHECK-NEXT: lbu a0, 0(a1)700; CHECK-NEXT: vwmulu.vx v8, v9, a0701; CHECK-NEXT: ret702 %a = load <4 x i16>, ptr %x703 %b = load i8, ptr %y704 %c = zext i8 %b to i32705 %d = insertelement <4 x i32> poison, i32 %c, i32 0706 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer707 %f = zext <4 x i16> %a to <4 x i32>708 %g = mul <4 x i32> %e, %f709 ret <4 x i32> %g710}711 712define <4 x i32> @vwmulu_vx_v4i32_i16(ptr %x, ptr %y) {713; CHECK-LABEL: vwmulu_vx_v4i32_i16:714; CHECK: # %bb.0:715; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma716; CHECK-NEXT: vle16.v v9, (a0)717; CHECK-NEXT: lhu a0, 0(a1)718; CHECK-NEXT: vwmulu.vx v8, v9, a0719; CHECK-NEXT: ret720 %a = load <4 x i16>, ptr %x721 %b = load i16, ptr %y722 %c = zext i16 %b to i32723 %d = insertelement <4 x i32> poison, i32 %c, i32 0724 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer725 %f = zext <4 x i16> %a to <4 x i32>726 %g = mul <4 x i32> %e, %f727 ret <4 x i32> %g728}729 730define <4 x i32> @vwmulu_vx_v4i32_i32(ptr %x, ptr %y) {731; CHECK-LABEL: vwmulu_vx_v4i32_i32:732; CHECK: # %bb.0:733; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma734; CHECK-NEXT: vle16.v v8, (a0)735; CHECK-NEXT: lw a0, 0(a1)736; CHECK-NEXT: vzext.vf2 v9, v8737; CHECK-NEXT: vmul.vx v8, v9, a0738; CHECK-NEXT: ret739 %a = load <4 x i16>, ptr %x740 %b = load i32, ptr %y741 %d = insertelement <4 x i32> poison, i32 %b, i32 0742 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer743 %f = zext <4 x i16> %a to <4 x i32>744 %g = mul <4 x i32> %e, %f745 ret <4 x i32> %g746}747 748define <2 x i64> @vwmulu_vx_v2i64_i8(ptr %x, ptr %y) {749; RV32-LABEL: vwmulu_vx_v2i64_i8:750; RV32: # %bb.0:751; RV32-NEXT: addi sp, sp, -16752; RV32-NEXT: .cfi_def_cfa_offset 16753; RV32-NEXT: lbu a1, 0(a1)754; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma755; RV32-NEXT: vle32.v v8, (a0)756; RV32-NEXT: sw a1, 8(sp)757; RV32-NEXT: sw zero, 12(sp)758; RV32-NEXT: addi a0, sp, 8759; RV32-NEXT: vlse64.v v9, (a0), zero760; RV32-NEXT: vzext.vf2 v10, v8761; RV32-NEXT: vmul.vv v8, v9, v10762; RV32-NEXT: addi sp, sp, 16763; RV32-NEXT: .cfi_def_cfa_offset 0764; RV32-NEXT: ret765;766; RV64-LABEL: vwmulu_vx_v2i64_i8:767; RV64: # %bb.0:768; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma769; RV64-NEXT: vle32.v v9, (a0)770; RV64-NEXT: lbu a0, 0(a1)771; RV64-NEXT: vwmulu.vx v8, v9, a0772; RV64-NEXT: ret773 %a = load <2 x i32>, ptr %x774 %b = load i8, ptr %y775 %c = zext i8 %b to i64776 %d = insertelement <2 x i64> poison, i64 %c, i64 0777 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer778 %f = zext <2 x i32> %a to <2 x i64>779 %g = mul <2 x i64> %e, %f780 ret <2 x i64> %g781}782 783define <2 x i64> @vwmulu_vx_v2i64_i16(ptr %x, ptr %y) {784; RV32-LABEL: vwmulu_vx_v2i64_i16:785; RV32: # %bb.0:786; RV32-NEXT: addi sp, sp, -16787; RV32-NEXT: .cfi_def_cfa_offset 16788; RV32-NEXT: lhu a1, 0(a1)789; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma790; RV32-NEXT: vle32.v v8, (a0)791; RV32-NEXT: sw a1, 8(sp)792; RV32-NEXT: sw zero, 12(sp)793; RV32-NEXT: addi a0, sp, 8794; RV32-NEXT: vlse64.v v9, (a0), zero795; RV32-NEXT: vzext.vf2 v10, v8796; RV32-NEXT: vmul.vv v8, v9, v10797; RV32-NEXT: addi sp, sp, 16798; RV32-NEXT: .cfi_def_cfa_offset 0799; RV32-NEXT: ret800;801; RV64-LABEL: vwmulu_vx_v2i64_i16:802; RV64: # %bb.0:803; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma804; RV64-NEXT: vle32.v v9, (a0)805; RV64-NEXT: lhu a0, 0(a1)806; RV64-NEXT: vwmulu.vx v8, v9, a0807; RV64-NEXT: ret808 %a = load <2 x i32>, ptr %x809 %b = load i16, ptr %y810 %c = zext i16 %b to i64811 %d = insertelement <2 x i64> poison, i64 %c, i64 0812 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer813 %f = zext <2 x i32> %a to <2 x i64>814 %g = mul <2 x i64> %e, %f815 ret <2 x i64> %g816}817 818define <2 x i64> @vwmulu_vx_v2i64_i32(ptr %x, ptr %y) {819; RV32-LABEL: vwmulu_vx_v2i64_i32:820; RV32: # %bb.0:821; RV32-NEXT: addi sp, sp, -16822; RV32-NEXT: .cfi_def_cfa_offset 16823; RV32-NEXT: lw a1, 0(a1)824; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma825; RV32-NEXT: vle32.v v8, (a0)826; RV32-NEXT: sw a1, 8(sp)827; RV32-NEXT: sw zero, 12(sp)828; RV32-NEXT: addi a0, sp, 8829; RV32-NEXT: vlse64.v v9, (a0), zero830; RV32-NEXT: vzext.vf2 v10, v8831; RV32-NEXT: vmul.vv v8, v9, v10832; RV32-NEXT: addi sp, sp, 16833; RV32-NEXT: .cfi_def_cfa_offset 0834; RV32-NEXT: ret835;836; RV64-LABEL: vwmulu_vx_v2i64_i32:837; RV64: # %bb.0:838; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma839; RV64-NEXT: vle32.v v9, (a0)840; RV64-NEXT: lw a0, 0(a1)841; RV64-NEXT: vwmulu.vx v8, v9, a0842; RV64-NEXT: ret843 %a = load <2 x i32>, ptr %x844 %b = load i32, ptr %y845 %c = zext i32 %b to i64846 %d = insertelement <2 x i64> poison, i64 %c, i64 0847 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer848 %f = zext <2 x i32> %a to <2 x i64>849 %g = mul <2 x i64> %e, %f850 ret <2 x i64> %g851}852 853define <2 x i64> @vwmulu_vx_v2i64_i64(ptr %x, ptr %y) {854; RV32-LABEL: vwmulu_vx_v2i64_i64:855; RV32: # %bb.0:856; RV32-NEXT: addi sp, sp, -16857; RV32-NEXT: .cfi_def_cfa_offset 16858; RV32-NEXT: lw a2, 0(a1)859; RV32-NEXT: lw a1, 4(a1)860; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma861; RV32-NEXT: vle32.v v8, (a0)862; RV32-NEXT: sw a2, 8(sp)863; RV32-NEXT: sw a1, 12(sp)864; RV32-NEXT: addi a0, sp, 8865; RV32-NEXT: vlse64.v v9, (a0), zero866; RV32-NEXT: vzext.vf2 v10, v8867; RV32-NEXT: vmul.vv v8, v9, v10868; RV32-NEXT: addi sp, sp, 16869; RV32-NEXT: .cfi_def_cfa_offset 0870; RV32-NEXT: ret871;872; RV64-LABEL: vwmulu_vx_v2i64_i64:873; RV64: # %bb.0:874; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma875; RV64-NEXT: vle32.v v8, (a0)876; RV64-NEXT: ld a0, 0(a1)877; RV64-NEXT: vzext.vf2 v9, v8878; RV64-NEXT: vmul.vx v8, v9, a0879; RV64-NEXT: ret880 %a = load <2 x i32>, ptr %x881 %b = load i64, ptr %y882 %d = insertelement <2 x i64> poison, i64 %b, i64 0883 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer884 %f = zext <2 x i32> %a to <2 x i64>885 %g = mul <2 x i64> %e, %f886 ret <2 x i64> %g887}888