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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV325; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV646 7; ==============================================================================8; i32 -> i649; ==============================================================================10 11define <4 x i64> @vwsll_vv_v4i64_sext(<4 x i32> %a, <4 x i32> %b) {12; CHECK-LABEL: vwsll_vv_v4i64_sext:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma15; CHECK-NEXT: vzext.vf2 v10, v816; CHECK-NEXT: vsext.vf2 v12, v917; CHECK-NEXT: vsll.vv v8, v10, v1218; CHECK-NEXT: ret19;20; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_sext:21; CHECK-ZVBB: # %bb.0:22; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma23; CHECK-ZVBB-NEXT: vmv1r.v v10, v924; CHECK-ZVBB-NEXT: vmv1r.v v11, v825; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v1026; CHECK-ZVBB-NEXT: ret27 %x = zext <4 x i32> %a to <4 x i64>28 %y = sext <4 x i32> %b to <4 x i64>29 %z = shl <4 x i64> %x, %y30 ret <4 x i64> %z31}32 33define <4 x i64> @vwsll_vv_v4i64_zext(<4 x i32> %a, <4 x i32> %b) {34; CHECK-LABEL: vwsll_vv_v4i64_zext:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma37; CHECK-NEXT: vzext.vf2 v10, v838; CHECK-NEXT: vzext.vf2 v12, v939; CHECK-NEXT: vsll.vv v8, v10, v1240; CHECK-NEXT: ret41;42; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_zext:43; CHECK-ZVBB: # %bb.0:44; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma45; CHECK-ZVBB-NEXT: vmv1r.v v10, v946; CHECK-ZVBB-NEXT: vmv1r.v v11, v847; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v1048; CHECK-ZVBB-NEXT: ret49 %x = zext <4 x i32> %a to <4 x i64>50 %y = zext <4 x i32> %b to <4 x i64>51 %z = shl <4 x i64> %x, %y52 ret <4 x i64> %z53}54 55define <4 x i64> @vwsll_vx_i64_v4i64(<4 x i32> %a, i64 %b) {56; CHECK-LABEL: vwsll_vx_i64_v4i64:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma59; CHECK-NEXT: vzext.vf2 v10, v860; CHECK-NEXT: vsll.vx v8, v10, a061; CHECK-NEXT: ret62;63; CHECK-ZVBB-LABEL: vwsll_vx_i64_v4i64:64; CHECK-ZVBB: # %bb.0:65; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma66; CHECK-ZVBB-NEXT: vmv1r.v v10, v867; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a068; CHECK-ZVBB-NEXT: ret69 %head = insertelement <4 x i64> poison, i64 %b, i32 070 %splat = shufflevector <4 x i64> %head, <4 x i64> poison, <4 x i32> zeroinitializer71 %x = zext <4 x i32> %a to <4 x i64>72 %z = shl <4 x i64> %x, %splat73 ret <4 x i64> %z74}75 76define <4 x i64> @vwsll_vx_i32_v4i64_sext(<4 x i32> %a, i32 %b) {77; CHECK-LABEL: vwsll_vx_i32_v4i64_sext:78; CHECK: # %bb.0:79; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma80; CHECK-NEXT: vmv.v.x v12, a081; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma82; CHECK-NEXT: vzext.vf2 v10, v883; CHECK-NEXT: vsext.vf2 v8, v1284; CHECK-NEXT: vsll.vv v8, v10, v885; CHECK-NEXT: ret86;87; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_sext:88; CHECK-ZVBB: # %bb.0:89; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma90; CHECK-ZVBB-NEXT: vmv1r.v v10, v891; CHECK-ZVBB-NEXT: vmv.v.x v11, a092; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v1193; CHECK-ZVBB-NEXT: ret94 %head = insertelement <4 x i32> poison, i32 %b, i32 095 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer96 %x = zext <4 x i32> %a to <4 x i64>97 %y = sext <4 x i32> %splat to <4 x i64>98 %z = shl <4 x i64> %x, %y99 ret <4 x i64> %z100}101 102define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) {103; CHECK-LABEL: vwsll_vx_i32_v4i64_zext:104; CHECK: # %bb.0:105; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma106; CHECK-NEXT: vmv.v.x v12, a0107; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma108; CHECK-NEXT: vzext.vf2 v10, v8109; CHECK-NEXT: vzext.vf2 v8, v12110; CHECK-NEXT: vsll.vv v8, v10, v8111; CHECK-NEXT: ret112;113; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_zext:114; CHECK-ZVBB: # %bb.0:115; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma116; CHECK-ZVBB-NEXT: vmv1r.v v10, v8117; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0118; CHECK-ZVBB-NEXT: ret119 %head = insertelement <4 x i32> poison, i32 %b, i32 0120 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer121 %x = zext <4 x i32> %a to <4 x i64>122 %y = zext <4 x i32> %splat to <4 x i64>123 %z = shl <4 x i64> %x, %y124 ret <4 x i64> %z125}126 127define <4 x i64> @vwsll_vx_i16_v4i64_sext(<4 x i32> %a, i16 %b) {128; CHECK-LABEL: vwsll_vx_i16_v4i64_sext:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma131; CHECK-NEXT: vmv.v.x v12, a0132; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma133; CHECK-NEXT: vzext.vf2 v10, v8134; CHECK-NEXT: vsext.vf4 v8, v12135; CHECK-NEXT: vsll.vv v8, v10, v8136; CHECK-NEXT: ret137;138; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_sext:139; CHECK-ZVBB: # %bb.0:140; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma141; CHECK-ZVBB-NEXT: vmv1r.v v10, v8142; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0143; CHECK-ZVBB-NEXT: ret144 %head = insertelement <4 x i16> poison, i16 %b, i32 0145 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer146 %x = zext <4 x i32> %a to <4 x i64>147 %y = sext <4 x i16> %splat to <4 x i64>148 %z = shl <4 x i64> %x, %y149 ret <4 x i64> %z150}151 152define <4 x i64> @vwsll_vx_i16_v4i64_zext(<4 x i32> %a, i16 %b) {153; CHECK-LABEL: vwsll_vx_i16_v4i64_zext:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma156; CHECK-NEXT: vmv.v.x v12, a0157; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma158; CHECK-NEXT: vzext.vf2 v10, v8159; CHECK-NEXT: vzext.vf4 v8, v12160; CHECK-NEXT: vsll.vv v8, v10, v8161; CHECK-NEXT: ret162;163; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_zext:164; CHECK-ZVBB: # %bb.0:165; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma166; CHECK-ZVBB-NEXT: vmv1r.v v10, v8167; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0168; CHECK-ZVBB-NEXT: ret169 %head = insertelement <4 x i16> poison, i16 %b, i32 0170 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer171 %x = zext <4 x i32> %a to <4 x i64>172 %y = zext <4 x i16> %splat to <4 x i64>173 %z = shl <4 x i64> %x, %y174 ret <4 x i64> %z175}176 177define <4 x i64> @vwsll_vx_i8_v4i64_sext(<4 x i32> %a, i8 %b) {178; CHECK-LABEL: vwsll_vx_i8_v4i64_sext:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma181; CHECK-NEXT: vmv.v.x v12, a0182; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma183; CHECK-NEXT: vzext.vf2 v10, v8184; CHECK-NEXT: vsext.vf8 v8, v12185; CHECK-NEXT: vsll.vv v8, v10, v8186; CHECK-NEXT: ret187;188; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_sext:189; CHECK-ZVBB: # %bb.0:190; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma191; CHECK-ZVBB-NEXT: vmv1r.v v10, v8192; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0193; CHECK-ZVBB-NEXT: ret194 %head = insertelement <4 x i8> poison, i8 %b, i32 0195 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer196 %x = zext <4 x i32> %a to <4 x i64>197 %y = sext <4 x i8> %splat to <4 x i64>198 %z = shl <4 x i64> %x, %y199 ret <4 x i64> %z200}201 202define <4 x i64> @vwsll_vx_i8_v4i64_zext(<4 x i32> %a, i8 %b) {203; CHECK-LABEL: vwsll_vx_i8_v4i64_zext:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma206; CHECK-NEXT: vmv.v.x v12, a0207; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma208; CHECK-NEXT: vzext.vf2 v10, v8209; CHECK-NEXT: vzext.vf8 v8, v12210; CHECK-NEXT: vsll.vv v8, v10, v8211; CHECK-NEXT: ret212;213; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_zext:214; CHECK-ZVBB: # %bb.0:215; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma216; CHECK-ZVBB-NEXT: vmv1r.v v10, v8217; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0218; CHECK-ZVBB-NEXT: ret219 %head = insertelement <4 x i8> poison, i8 %b, i32 0220 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer221 %x = zext <4 x i32> %a to <4 x i64>222 %y = zext <4 x i8> %splat to <4 x i64>223 %z = shl <4 x i64> %x, %y224 ret <4 x i64> %z225}226 227define <4 x i64> @vwsll_vi_v4i64(<4 x i32> %a) {228; CHECK-LABEL: vwsll_vi_v4i64:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma231; CHECK-NEXT: vmv1r.v v10, v8232; CHECK-NEXT: li a0, 4233; CHECK-NEXT: vwmulu.vx v8, v10, a0234; CHECK-NEXT: ret235;236; CHECK-ZVBB-LABEL: vwsll_vi_v4i64:237; CHECK-ZVBB: # %bb.0:238; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma239; CHECK-ZVBB-NEXT: vmv1r.v v10, v8240; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2241; CHECK-ZVBB-NEXT: ret242 %x = zext <4 x i32> %a to <4 x i64>243 %z = shl <4 x i64> %x, splat (i64 2)244 ret <4 x i64> %z245}246 247; ==============================================================================248; i16 -> i32249; ==============================================================================250 251define <8 x i32> @vwsll_vv_v8i32_sext(<8 x i16> %a, <8 x i16> %b) {252; CHECK-LABEL: vwsll_vv_v8i32_sext:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma255; CHECK-NEXT: vzext.vf2 v10, v8256; CHECK-NEXT: vsext.vf2 v12, v9257; CHECK-NEXT: vsll.vv v8, v10, v12258; CHECK-NEXT: ret259;260; CHECK-ZVBB-LABEL: vwsll_vv_v8i32_sext:261; CHECK-ZVBB: # %bb.0:262; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma263; CHECK-ZVBB-NEXT: vmv1r.v v10, v9264; CHECK-ZVBB-NEXT: vmv1r.v v11, v8265; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10266; CHECK-ZVBB-NEXT: ret267 %x = zext <8 x i16> %a to <8 x i32>268 %y = sext <8 x i16> %b to <8 x i32>269 %z = shl <8 x i32> %x, %y270 ret <8 x i32> %z271}272 273define <8 x i32> @vwsll_vv_v8i32_zext(<8 x i16> %a, <8 x i16> %b) {274; CHECK-LABEL: vwsll_vv_v8i32_zext:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma277; CHECK-NEXT: vzext.vf2 v10, v8278; CHECK-NEXT: vzext.vf2 v12, v9279; CHECK-NEXT: vsll.vv v8, v10, v12280; CHECK-NEXT: ret281;282; CHECK-ZVBB-LABEL: vwsll_vv_v8i32_zext:283; CHECK-ZVBB: # %bb.0:284; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma285; CHECK-ZVBB-NEXT: vmv1r.v v10, v9286; CHECK-ZVBB-NEXT: vmv1r.v v11, v8287; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10288; CHECK-ZVBB-NEXT: ret289 %x = zext <8 x i16> %a to <8 x i32>290 %y = zext <8 x i16> %b to <8 x i32>291 %z = shl <8 x i32> %x, %y292 ret <8 x i32> %z293}294 295define <8 x i32> @vwsll_vx_i64_v8i32(<8 x i16> %a, i64 %b) {296; CHECK-LABEL: vwsll_vx_i64_v8i32:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma299; CHECK-NEXT: vzext.vf2 v10, v8300; CHECK-NEXT: vsll.vx v8, v10, a0301; CHECK-NEXT: ret302;303; CHECK-ZVBB-LABEL: vwsll_vx_i64_v8i32:304; CHECK-ZVBB: # %bb.0:305; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma306; CHECK-ZVBB-NEXT: vmv1r.v v10, v8307; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0308; CHECK-ZVBB-NEXT: ret309 %head = insertelement <8 x i64> poison, i64 %b, i32 0310 %splat = shufflevector <8 x i64> %head, <8 x i64> poison, <8 x i32> zeroinitializer311 %x = zext <8 x i16> %a to <8 x i32>312 %y = trunc <8 x i64> %splat to <8 x i32>313 %z = shl <8 x i32> %x, %y314 ret <8 x i32> %z315}316 317define <8 x i32> @vwsll_vx_i32_v8i32(<8 x i16> %a, i32 %b) {318; CHECK-LABEL: vwsll_vx_i32_v8i32:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma321; CHECK-NEXT: vzext.vf2 v10, v8322; CHECK-NEXT: vsll.vx v8, v10, a0323; CHECK-NEXT: ret324;325; CHECK-ZVBB-LABEL: vwsll_vx_i32_v8i32:326; CHECK-ZVBB: # %bb.0:327; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma328; CHECK-ZVBB-NEXT: vmv1r.v v10, v8329; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0330; CHECK-ZVBB-NEXT: ret331 %head = insertelement <8 x i32> poison, i32 %b, i32 0332 %splat = shufflevector <8 x i32> %head, <8 x i32> poison, <8 x i32> zeroinitializer333 %x = zext <8 x i16> %a to <8 x i32>334 %z = shl <8 x i32> %x, %splat335 ret <8 x i32> %z336}337 338define <8 x i32> @vwsll_vx_i16_v8i32_sext(<8 x i16> %a, i16 %b) {339; CHECK-LABEL: vwsll_vx_i16_v8i32_sext:340; CHECK: # %bb.0:341; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma342; CHECK-NEXT: vmv.v.x v12, a0343; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma344; CHECK-NEXT: vzext.vf2 v10, v8345; CHECK-NEXT: vsext.vf2 v8, v12346; CHECK-NEXT: vsll.vv v8, v10, v8347; CHECK-NEXT: ret348;349; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_sext:350; CHECK-ZVBB: # %bb.0:351; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma352; CHECK-ZVBB-NEXT: vmv1r.v v10, v8353; CHECK-ZVBB-NEXT: vmv.v.x v11, a0354; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11355; CHECK-ZVBB-NEXT: ret356 %head = insertelement <8 x i16> poison, i16 %b, i32 0357 %splat = shufflevector <8 x i16> %head, <8 x i16> poison, <8 x i32> zeroinitializer358 %x = zext <8 x i16> %a to <8 x i32>359 %y = sext <8 x i16> %splat to <8 x i32>360 %z = shl <8 x i32> %x, %y361 ret <8 x i32> %z362}363 364define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) {365; CHECK-LABEL: vwsll_vx_i16_v8i32_zext:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma368; CHECK-NEXT: vmv.v.x v12, a0369; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma370; CHECK-NEXT: vzext.vf2 v10, v8371; CHECK-NEXT: vzext.vf2 v8, v12372; CHECK-NEXT: vsll.vv v8, v10, v8373; CHECK-NEXT: ret374;375; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_zext:376; CHECK-ZVBB: # %bb.0:377; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma378; CHECK-ZVBB-NEXT: vmv1r.v v10, v8379; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0380; CHECK-ZVBB-NEXT: ret381 %head = insertelement <8 x i16> poison, i16 %b, i32 0382 %splat = shufflevector <8 x i16> %head, <8 x i16> poison, <8 x i32> zeroinitializer383 %x = zext <8 x i16> %a to <8 x i32>384 %y = zext <8 x i16> %splat to <8 x i32>385 %z = shl <8 x i32> %x, %y386 ret <8 x i32> %z387}388 389define <8 x i32> @vwsll_vx_i8_v8i32_sext(<8 x i16> %a, i8 %b) {390; CHECK-LABEL: vwsll_vx_i8_v8i32_sext:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma393; CHECK-NEXT: vmv.v.x v12, a0394; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma395; CHECK-NEXT: vzext.vf2 v10, v8396; CHECK-NEXT: vsext.vf4 v8, v12397; CHECK-NEXT: vsll.vv v8, v10, v8398; CHECK-NEXT: ret399;400; CHECK-ZVBB-LABEL: vwsll_vx_i8_v8i32_sext:401; CHECK-ZVBB: # %bb.0:402; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma403; CHECK-ZVBB-NEXT: vmv1r.v v10, v8404; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0405; CHECK-ZVBB-NEXT: ret406 %head = insertelement <8 x i8> poison, i8 %b, i32 0407 %splat = shufflevector <8 x i8> %head, <8 x i8> poison, <8 x i32> zeroinitializer408 %x = zext <8 x i16> %a to <8 x i32>409 %y = sext <8 x i8> %splat to <8 x i32>410 %z = shl <8 x i32> %x, %y411 ret <8 x i32> %z412}413 414define <8 x i32> @vwsll_vx_i8_v8i32_zext(<8 x i16> %a, i8 %b) {415; CHECK-LABEL: vwsll_vx_i8_v8i32_zext:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma418; CHECK-NEXT: vmv.v.x v12, a0419; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma420; CHECK-NEXT: vzext.vf2 v10, v8421; CHECK-NEXT: vzext.vf4 v8, v12422; CHECK-NEXT: vsll.vv v8, v10, v8423; CHECK-NEXT: ret424;425; CHECK-ZVBB-LABEL: vwsll_vx_i8_v8i32_zext:426; CHECK-ZVBB: # %bb.0:427; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma428; CHECK-ZVBB-NEXT: vmv1r.v v10, v8429; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0430; CHECK-ZVBB-NEXT: ret431 %head = insertelement <8 x i8> poison, i8 %b, i32 0432 %splat = shufflevector <8 x i8> %head, <8 x i8> poison, <8 x i32> zeroinitializer433 %x = zext <8 x i16> %a to <8 x i32>434 %y = zext <8 x i8> %splat to <8 x i32>435 %z = shl <8 x i32> %x, %y436 ret <8 x i32> %z437}438 439define <8 x i32> @vwsll_vi_v8i32(<8 x i16> %a) {440; CHECK-LABEL: vwsll_vi_v8i32:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma443; CHECK-NEXT: vmv1r.v v10, v8444; CHECK-NEXT: li a0, 4445; CHECK-NEXT: vwmulu.vx v8, v10, a0446; CHECK-NEXT: ret447;448; CHECK-ZVBB-LABEL: vwsll_vi_v8i32:449; CHECK-ZVBB: # %bb.0:450; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma451; CHECK-ZVBB-NEXT: vmv1r.v v10, v8452; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2453; CHECK-ZVBB-NEXT: ret454 %x = zext <8 x i16> %a to <8 x i32>455 %z = shl <8 x i32> %x, splat (i32 2)456 ret <8 x i32> %z457}458 459; ==============================================================================460; i8 -> i16461; ==============================================================================462 463define <16 x i16> @vwsll_vv_v16i16_sext(<16 x i8> %a, <16 x i8> %b) {464; CHECK-LABEL: vwsll_vv_v16i16_sext:465; CHECK: # %bb.0:466; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma467; CHECK-NEXT: vzext.vf2 v10, v8468; CHECK-NEXT: vsext.vf2 v12, v9469; CHECK-NEXT: vsll.vv v8, v10, v12470; CHECK-NEXT: ret471;472; CHECK-ZVBB-LABEL: vwsll_vv_v16i16_sext:473; CHECK-ZVBB: # %bb.0:474; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma475; CHECK-ZVBB-NEXT: vmv1r.v v10, v9476; CHECK-ZVBB-NEXT: vmv1r.v v11, v8477; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10478; CHECK-ZVBB-NEXT: ret479 %x = zext <16 x i8> %a to <16 x i16>480 %y = sext <16 x i8> %b to <16 x i16>481 %z = shl <16 x i16> %x, %y482 ret <16 x i16> %z483}484 485define <16 x i16> @vwsll_vv_v16i16_zext(<16 x i8> %a, <16 x i8> %b) {486; CHECK-LABEL: vwsll_vv_v16i16_zext:487; CHECK: # %bb.0:488; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma489; CHECK-NEXT: vzext.vf2 v10, v8490; CHECK-NEXT: vzext.vf2 v12, v9491; CHECK-NEXT: vsll.vv v8, v10, v12492; CHECK-NEXT: ret493;494; CHECK-ZVBB-LABEL: vwsll_vv_v16i16_zext:495; CHECK-ZVBB: # %bb.0:496; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma497; CHECK-ZVBB-NEXT: vmv1r.v v10, v9498; CHECK-ZVBB-NEXT: vmv1r.v v11, v8499; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10500; CHECK-ZVBB-NEXT: ret501 %x = zext <16 x i8> %a to <16 x i16>502 %y = zext <16 x i8> %b to <16 x i16>503 %z = shl <16 x i16> %x, %y504 ret <16 x i16> %z505}506 507define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) {508; RV32-LABEL: vwsll_vx_i64_v16i16:509; RV32: # %bb.0:510; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma511; RV32-NEXT: vmv.v.x v16, a0512; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma513; RV32-NEXT: vrgather.vi v24, v16, 0514; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma515; RV32-NEXT: vzext.vf2 v12, v8516; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma517; RV32-NEXT: vnsrl.wi v8, v24, 0518; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma519; RV32-NEXT: vnsrl.wi v14, v8, 0520; RV32-NEXT: vsll.vv v8, v12, v14521; RV32-NEXT: ret522;523; RV64-LABEL: vwsll_vx_i64_v16i16:524; RV64: # %bb.0:525; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma526; RV64-NEXT: vmv.v.x v16, a0527; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma528; RV64-NEXT: vzext.vf2 v12, v8529; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma530; RV64-NEXT: vnsrl.wi v8, v16, 0531; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma532; RV64-NEXT: vnsrl.wi v14, v8, 0533; RV64-NEXT: vsll.vv v8, v12, v14534; RV64-NEXT: ret535;536; CHECK-ZVBB-RV32-LABEL: vwsll_vx_i64_v16i16:537; CHECK-ZVBB-RV32: # %bb.0:538; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma539; CHECK-ZVBB-RV32-NEXT: vmv.v.x v16, a0540; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma541; CHECK-ZVBB-RV32-NEXT: vrgather.vi v24, v16, 0542; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma543; CHECK-ZVBB-RV32-NEXT: vzext.vf2 v12, v8544; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma545; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v8, v24, 0546; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma547; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v14, v8, 0548; CHECK-ZVBB-RV32-NEXT: vsll.vv v8, v12, v14549; CHECK-ZVBB-RV32-NEXT: ret550;551; CHECK-ZVBB-RV64-LABEL: vwsll_vx_i64_v16i16:552; CHECK-ZVBB-RV64: # %bb.0:553; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma554; CHECK-ZVBB-RV64-NEXT: vmv1r.v v10, v8555; CHECK-ZVBB-RV64-NEXT: vwsll.vx v8, v10, a0556; CHECK-ZVBB-RV64-NEXT: ret557 %head = insertelement <8 x i64> poison, i64 %b, i32 0558 %splat = shufflevector <8 x i64> %head, <8 x i64> poison, <16 x i32> zeroinitializer559 %x = zext <16 x i8> %a to <16 x i16>560 %y = trunc <16 x i64> %splat to <16 x i16>561 %z = shl <16 x i16> %x, %y562 ret <16 x i16> %z563}564 565define <16 x i16> @vwsll_vx_i32_v16i16(<16 x i8> %a, i32 %b) {566; CHECK-LABEL: vwsll_vx_i32_v16i16:567; CHECK: # %bb.0:568; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma569; CHECK-NEXT: vmv.v.x v12, a0570; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma571; CHECK-NEXT: vzext.vf2 v10, v8572; CHECK-NEXT: vnsrl.wi v8, v12, 0573; CHECK-NEXT: vsll.vv v8, v10, v8574; CHECK-NEXT: ret575;576; CHECK-ZVBB-LABEL: vwsll_vx_i32_v16i16:577; CHECK-ZVBB: # %bb.0:578; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma579; CHECK-ZVBB-NEXT: vmv1r.v v10, v8580; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0581; CHECK-ZVBB-NEXT: ret582 %head = insertelement <16 x i32> poison, i32 %b, i32 0583 %splat = shufflevector <16 x i32> %head, <16 x i32> poison, <16 x i32> zeroinitializer584 %x = zext <16 x i8> %a to <16 x i16>585 %y = trunc <16 x i32> %splat to <16 x i16>586 %z = shl <16 x i16> %x, %y587 ret <16 x i16> %z588}589 590define <16 x i16> @vwsll_vx_i16_v16i16(<16 x i8> %a, i16 %b) {591; CHECK-LABEL: vwsll_vx_i16_v16i16:592; CHECK: # %bb.0:593; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma594; CHECK-NEXT: vzext.vf2 v10, v8595; CHECK-NEXT: vsll.vx v8, v10, a0596; CHECK-NEXT: ret597;598; CHECK-ZVBB-LABEL: vwsll_vx_i16_v16i16:599; CHECK-ZVBB: # %bb.0:600; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma601; CHECK-ZVBB-NEXT: vmv1r.v v10, v8602; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0603; CHECK-ZVBB-NEXT: ret604 %head = insertelement <16 x i16> poison, i16 %b, i32 0605 %splat = shufflevector <16 x i16> %head, <16 x i16> poison, <16 x i32> zeroinitializer606 %x = zext <16 x i8> %a to <16 x i16>607 %z = shl <16 x i16> %x, %splat608 ret <16 x i16> %z609}610 611define <16 x i16> @vwsll_vx_i8_v16i16_sext(<16 x i8> %a, i8 %b) {612; CHECK-LABEL: vwsll_vx_i8_v16i16_sext:613; CHECK: # %bb.0:614; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma615; CHECK-NEXT: vmv.v.x v12, a0616; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma617; CHECK-NEXT: vzext.vf2 v10, v8618; CHECK-NEXT: vsext.vf2 v8, v12619; CHECK-NEXT: vsll.vv v8, v10, v8620; CHECK-NEXT: ret621;622; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_sext:623; CHECK-ZVBB: # %bb.0:624; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma625; CHECK-ZVBB-NEXT: vmv1r.v v10, v8626; CHECK-ZVBB-NEXT: vmv.v.x v11, a0627; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11628; CHECK-ZVBB-NEXT: ret629 %head = insertelement <16 x i8> poison, i8 %b, i32 0630 %splat = shufflevector <16 x i8> %head, <16 x i8> poison, <16 x i32> zeroinitializer631 %x = zext <16 x i8> %a to <16 x i16>632 %y = sext <16 x i8> %splat to <16 x i16>633 %z = shl <16 x i16> %x, %y634 ret <16 x i16> %z635}636 637define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) {638; CHECK-LABEL: vwsll_vx_i8_v16i16_zext:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma641; CHECK-NEXT: vmv.v.x v12, a0642; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma643; CHECK-NEXT: vzext.vf2 v10, v8644; CHECK-NEXT: vzext.vf2 v8, v12645; CHECK-NEXT: vsll.vv v8, v10, v8646; CHECK-NEXT: ret647;648; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_zext:649; CHECK-ZVBB: # %bb.0:650; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma651; CHECK-ZVBB-NEXT: vmv1r.v v10, v8652; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0653; CHECK-ZVBB-NEXT: ret654 %head = insertelement <16 x i8> poison, i8 %b, i32 0655 %splat = shufflevector <16 x i8> %head, <16 x i8> poison, <16 x i32> zeroinitializer656 %x = zext <16 x i8> %a to <16 x i16>657 %y = zext <16 x i8> %splat to <16 x i16>658 %z = shl <16 x i16> %x, %y659 ret <16 x i16> %z660}661 662define <16 x i16> @vwsll_vi_v16i16(<16 x i8> %a) {663; CHECK-LABEL: vwsll_vi_v16i16:664; CHECK: # %bb.0:665; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma666; CHECK-NEXT: vmv1r.v v10, v8667; CHECK-NEXT: li a0, 4668; CHECK-NEXT: vwmulu.vx v8, v10, a0669; CHECK-NEXT: ret670;671; CHECK-ZVBB-LABEL: vwsll_vi_v16i16:672; CHECK-ZVBB: # %bb.0:673; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma674; CHECK-ZVBB-NEXT: vmv1r.v v10, v8675; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2676; CHECK-ZVBB-NEXT: ret677 %x = zext <16 x i8> %a to <16 x i16>678 %z = shl <16 x i16> %x, splat (i16 2)679 ret <16 x i16> %z680}681 682; ==============================================================================683; i8 -> i64684; ==============================================================================685 686define <4 x i64> @vwsll_vv_v4i64_v4i8_sext(<4 x i8> %a, <4 x i8> %b) {687; CHECK-LABEL: vwsll_vv_v4i64_v4i8_sext:688; CHECK: # %bb.0:689; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma690; CHECK-NEXT: vzext.vf8 v10, v8691; CHECK-NEXT: vsext.vf8 v12, v9692; CHECK-NEXT: vsll.vv v8, v10, v12693; CHECK-NEXT: ret694;695; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_sext:696; CHECK-ZVBB: # %bb.0:697; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma698; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8699; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9700; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12701; CHECK-ZVBB-NEXT: ret702 %x = zext <4 x i8> %a to <4 x i64>703 %y = sext <4 x i8> %b to <4 x i64>704 %z = shl <4 x i64> %x, %y705 ret <4 x i64> %z706}707 708define <4 x i64> @vwsll_vv_v4i64_v4i8_zext(<4 x i8> %a, <4 x i8> %b) {709; CHECK-LABEL: vwsll_vv_v4i64_v4i8_zext:710; CHECK: # %bb.0:711; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma712; CHECK-NEXT: vzext.vf8 v10, v8713; CHECK-NEXT: vzext.vf8 v12, v9714; CHECK-NEXT: vsll.vv v8, v10, v12715; CHECK-NEXT: ret716;717; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_zext:718; CHECK-ZVBB: # %bb.0:719; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma720; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8721; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9722; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11723; CHECK-ZVBB-NEXT: ret724 %x = zext <4 x i8> %a to <4 x i64>725 %y = zext <4 x i8> %b to <4 x i64>726 %z = shl <4 x i64> %x, %y727 ret <4 x i64> %z728}729 730define <4 x i64> @vwsll_vx_i64_v4i64_v4i8(<4 x i8> %a, i64 %b) {731; CHECK-LABEL: vwsll_vx_i64_v4i64_v4i8:732; CHECK: # %bb.0:733; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma734; CHECK-NEXT: vzext.vf8 v10, v8735; CHECK-NEXT: vsll.vx v8, v10, a0736; CHECK-NEXT: ret737;738; CHECK-ZVBB-LABEL: vwsll_vx_i64_v4i64_v4i8:739; CHECK-ZVBB: # %bb.0:740; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma741; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8742; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0743; CHECK-ZVBB-NEXT: ret744 %head = insertelement <4 x i64> poison, i64 %b, i32 0745 %splat = shufflevector <4 x i64> %head, <4 x i64> poison, <4 x i32> zeroinitializer746 %x = zext <4 x i8> %a to <4 x i64>747 %z = shl <4 x i64> %x, %splat748 ret <4 x i64> %z749}750 751define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_sext(<4 x i8> %a, i32 %b) {752; CHECK-LABEL: vwsll_vx_i32_v4i64_v4i8_sext:753; CHECK: # %bb.0:754; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma755; CHECK-NEXT: vmv.v.x v12, a0756; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma757; CHECK-NEXT: vzext.vf8 v10, v8758; CHECK-NEXT: vsext.vf2 v8, v12759; CHECK-NEXT: vsll.vv v8, v10, v8760; CHECK-NEXT: ret761;762; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_sext:763; CHECK-ZVBB: # %bb.0:764; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma765; CHECK-ZVBB-NEXT: vmv.v.x v12, a0766; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma767; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8768; CHECK-ZVBB-NEXT: vsext.vf2 v8, v12769; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8770; CHECK-ZVBB-NEXT: ret771 %head = insertelement <4 x i32> poison, i32 %b, i32 0772 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer773 %x = zext <4 x i8> %a to <4 x i64>774 %y = sext <4 x i32> %splat to <4 x i64>775 %z = shl <4 x i64> %x, %y776 ret <4 x i64> %z777}778 779define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_zext(<4 x i8> %a, i32 %b) {780; CHECK-LABEL: vwsll_vx_i32_v4i64_v4i8_zext:781; CHECK: # %bb.0:782; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma783; CHECK-NEXT: vmv.v.x v12, a0784; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma785; CHECK-NEXT: vzext.vf8 v10, v8786; CHECK-NEXT: vzext.vf2 v8, v12787; CHECK-NEXT: vsll.vv v8, v10, v8788; CHECK-NEXT: ret789;790; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_zext:791; CHECK-ZVBB: # %bb.0:792; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma793; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8794; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0795; CHECK-ZVBB-NEXT: ret796 %head = insertelement <4 x i32> poison, i32 %b, i32 0797 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer798 %x = zext <4 x i8> %a to <4 x i64>799 %y = zext <4 x i32> %splat to <4 x i64>800 %z = shl <4 x i64> %x, %y801 ret <4 x i64> %z802}803 804define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_sext(<4 x i8> %a, i16 %b) {805; CHECK-LABEL: vwsll_vx_i16_v4i64_v4i8_sext:806; CHECK: # %bb.0:807; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma808; CHECK-NEXT: vmv.v.x v12, a0809; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma810; CHECK-NEXT: vzext.vf8 v10, v8811; CHECK-NEXT: vsext.vf4 v8, v12812; CHECK-NEXT: vsll.vv v8, v10, v8813; CHECK-NEXT: ret814;815; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_sext:816; CHECK-ZVBB: # %bb.0:817; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma818; CHECK-ZVBB-NEXT: vmv.v.x v12, a0819; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma820; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8821; CHECK-ZVBB-NEXT: vsext.vf4 v8, v12822; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8823; CHECK-ZVBB-NEXT: ret824 %head = insertelement <4 x i16> poison, i16 %b, i32 0825 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer826 %x = zext <4 x i8> %a to <4 x i64>827 %y = sext <4 x i16> %splat to <4 x i64>828 %z = shl <4 x i64> %x, %y829 ret <4 x i64> %z830}831 832define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_zext(<4 x i8> %a, i16 %b) {833; CHECK-LABEL: vwsll_vx_i16_v4i64_v4i8_zext:834; CHECK: # %bb.0:835; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma836; CHECK-NEXT: vmv.v.x v12, a0837; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma838; CHECK-NEXT: vzext.vf8 v10, v8839; CHECK-NEXT: vzext.vf4 v8, v12840; CHECK-NEXT: vsll.vv v8, v10, v8841; CHECK-NEXT: ret842;843; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_zext:844; CHECK-ZVBB: # %bb.0:845; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma846; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8847; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0848; CHECK-ZVBB-NEXT: ret849 %head = insertelement <4 x i16> poison, i16 %b, i32 0850 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer851 %x = zext <4 x i8> %a to <4 x i64>852 %y = zext <4 x i16> %splat to <4 x i64>853 %z = shl <4 x i64> %x, %y854 ret <4 x i64> %z855}856 857define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_sext(<4 x i8> %a, i8 %b) {858; CHECK-LABEL: vwsll_vx_i8_v4i64_v4i8_sext:859; CHECK: # %bb.0:860; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma861; CHECK-NEXT: vmv.v.x v12, a0862; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma863; CHECK-NEXT: vzext.vf8 v10, v8864; CHECK-NEXT: vsext.vf8 v8, v12865; CHECK-NEXT: vsll.vv v8, v10, v8866; CHECK-NEXT: ret867;868; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_sext:869; CHECK-ZVBB: # %bb.0:870; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma871; CHECK-ZVBB-NEXT: vmv.v.x v12, a0872; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma873; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8874; CHECK-ZVBB-NEXT: vsext.vf8 v8, v12875; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8876; CHECK-ZVBB-NEXT: ret877 %head = insertelement <4 x i8> poison, i8 %b, i32 0878 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer879 %x = zext <4 x i8> %a to <4 x i64>880 %y = sext <4 x i8> %splat to <4 x i64>881 %z = shl <4 x i64> %x, %y882 ret <4 x i64> %z883}884 885define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_zext(<4 x i8> %a, i8 %b) {886; CHECK-LABEL: vwsll_vx_i8_v4i64_v4i8_zext:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma889; CHECK-NEXT: vmv.v.x v12, a0890; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma891; CHECK-NEXT: vzext.vf8 v10, v8892; CHECK-NEXT: vzext.vf8 v8, v12893; CHECK-NEXT: vsll.vv v8, v10, v8894; CHECK-NEXT: ret895;896; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_zext:897; CHECK-ZVBB: # %bb.0:898; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma899; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8900; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0901; CHECK-ZVBB-NEXT: ret902 %head = insertelement <4 x i8> poison, i8 %b, i32 0903 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer904 %x = zext <4 x i8> %a to <4 x i64>905 %y = zext <4 x i8> %splat to <4 x i64>906 %z = shl <4 x i64> %x, %y907 ret <4 x i64> %z908}909 910define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) {911; CHECK-LABEL: vwsll_vi_v4i64_v4i8:912; CHECK: # %bb.0:913; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma914; CHECK-NEXT: vzext.vf8 v10, v8915; CHECK-NEXT: vsll.vi v8, v10, 2916; CHECK-NEXT: ret917;918; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8:919; CHECK-ZVBB: # %bb.0:920; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma921; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8922; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2923; CHECK-ZVBB-NEXT: ret924 %x = zext <4 x i8> %a to <4 x i64>925 %z = shl <4 x i64> %x, splat (i64 2)926 ret <4 x i64> %z927}928