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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <2 x i16> @vwsubu_v2i16(ptr %x, ptr %y) {6; CHECK-LABEL: vwsubu_v2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma9; CHECK-NEXT: vle8.v v9, (a0)10; CHECK-NEXT: vle8.v v10, (a1)11; CHECK-NEXT: vwsubu.vv v8, v9, v1012; CHECK-NEXT: ret13 %a = load <2 x i8>, ptr %x14 %b = load <2 x i8>, ptr %y15 %c = zext <2 x i8> %a to <2 x i16>16 %d = zext <2 x i8> %b to <2 x i16>17 %e = sub <2 x i16> %c, %d18 ret <2 x i16> %e19}20 21define <4 x i16> @vwsubu_v4i16(ptr %x, ptr %y) {22; CHECK-LABEL: vwsubu_v4i16:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma25; CHECK-NEXT: vle8.v v9, (a0)26; CHECK-NEXT: vle8.v v10, (a1)27; CHECK-NEXT: vwsubu.vv v8, v9, v1028; CHECK-NEXT: ret29 %a = load <4 x i8>, ptr %x30 %b = load <4 x i8>, ptr %y31 %c = zext <4 x i8> %a to <4 x i16>32 %d = zext <4 x i8> %b to <4 x i16>33 %e = sub <4 x i16> %c, %d34 ret <4 x i16> %e35}36 37define <2 x i32> @vwsubu_v2i32(ptr %x, ptr %y) {38; CHECK-LABEL: vwsubu_v2i32:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma41; CHECK-NEXT: vle16.v v9, (a0)42; CHECK-NEXT: vle16.v v10, (a1)43; CHECK-NEXT: vwsubu.vv v8, v9, v1044; CHECK-NEXT: ret45 %a = load <2 x i16>, ptr %x46 %b = load <2 x i16>, ptr %y47 %c = zext <2 x i16> %a to <2 x i32>48 %d = zext <2 x i16> %b to <2 x i32>49 %e = sub <2 x i32> %c, %d50 ret <2 x i32> %e51}52 53define <8 x i16> @vwsubu_v8i16(ptr %x, ptr %y) {54; CHECK-LABEL: vwsubu_v8i16:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma57; CHECK-NEXT: vle8.v v9, (a0)58; CHECK-NEXT: vle8.v v10, (a1)59; CHECK-NEXT: vwsubu.vv v8, v9, v1060; CHECK-NEXT: ret61 %a = load <8 x i8>, ptr %x62 %b = load <8 x i8>, ptr %y63 %c = zext <8 x i8> %a to <8 x i16>64 %d = zext <8 x i8> %b to <8 x i16>65 %e = sub <8 x i16> %c, %d66 ret <8 x i16> %e67}68 69define <4 x i32> @vwsubu_v4i32(ptr %x, ptr %y) {70; CHECK-LABEL: vwsubu_v4i32:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma73; CHECK-NEXT: vle16.v v9, (a0)74; CHECK-NEXT: vle16.v v10, (a1)75; CHECK-NEXT: vwsubu.vv v8, v9, v1076; CHECK-NEXT: ret77 %a = load <4 x i16>, ptr %x78 %b = load <4 x i16>, ptr %y79 %c = zext <4 x i16> %a to <4 x i32>80 %d = zext <4 x i16> %b to <4 x i32>81 %e = sub <4 x i32> %c, %d82 ret <4 x i32> %e83}84 85define <2 x i64> @vwsubu_v2i64(ptr %x, ptr %y) {86; CHECK-LABEL: vwsubu_v2i64:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma89; CHECK-NEXT: vle32.v v9, (a0)90; CHECK-NEXT: vle32.v v10, (a1)91; CHECK-NEXT: vwsubu.vv v8, v9, v1092; CHECK-NEXT: ret93 %a = load <2 x i32>, ptr %x94 %b = load <2 x i32>, ptr %y95 %c = zext <2 x i32> %a to <2 x i64>96 %d = zext <2 x i32> %b to <2 x i64>97 %e = sub <2 x i64> %c, %d98 ret <2 x i64> %e99}100 101define <16 x i16> @vwsubu_v16i16(ptr %x, ptr %y) {102; CHECK-LABEL: vwsubu_v16i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma105; CHECK-NEXT: vle8.v v10, (a0)106; CHECK-NEXT: vle8.v v11, (a1)107; CHECK-NEXT: vwsubu.vv v8, v10, v11108; CHECK-NEXT: ret109 %a = load <16 x i8>, ptr %x110 %b = load <16 x i8>, ptr %y111 %c = zext <16 x i8> %a to <16 x i16>112 %d = zext <16 x i8> %b to <16 x i16>113 %e = sub <16 x i16> %c, %d114 ret <16 x i16> %e115}116 117define <8 x i32> @vwsubu_v8i32(ptr %x, ptr %y) {118; CHECK-LABEL: vwsubu_v8i32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma121; CHECK-NEXT: vle16.v v10, (a0)122; CHECK-NEXT: vle16.v v11, (a1)123; CHECK-NEXT: vwsubu.vv v8, v10, v11124; CHECK-NEXT: ret125 %a = load <8 x i16>, ptr %x126 %b = load <8 x i16>, ptr %y127 %c = zext <8 x i16> %a to <8 x i32>128 %d = zext <8 x i16> %b to <8 x i32>129 %e = sub <8 x i32> %c, %d130 ret <8 x i32> %e131}132 133define <4 x i64> @vwsubu_v4i64(ptr %x, ptr %y) {134; CHECK-LABEL: vwsubu_v4i64:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma137; CHECK-NEXT: vle32.v v10, (a0)138; CHECK-NEXT: vle32.v v11, (a1)139; CHECK-NEXT: vwsubu.vv v8, v10, v11140; CHECK-NEXT: ret141 %a = load <4 x i32>, ptr %x142 %b = load <4 x i32>, ptr %y143 %c = zext <4 x i32> %a to <4 x i64>144 %d = zext <4 x i32> %b to <4 x i64>145 %e = sub <4 x i64> %c, %d146 ret <4 x i64> %e147}148 149define <32 x i16> @vwsubu_v32i16(ptr %x, ptr %y) {150; CHECK-LABEL: vwsubu_v32i16:151; CHECK: # %bb.0:152; CHECK-NEXT: li a2, 32153; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma154; CHECK-NEXT: vle8.v v12, (a0)155; CHECK-NEXT: vle8.v v14, (a1)156; CHECK-NEXT: vwsubu.vv v8, v12, v14157; CHECK-NEXT: ret158 %a = load <32 x i8>, ptr %x159 %b = load <32 x i8>, ptr %y160 %c = zext <32 x i8> %a to <32 x i16>161 %d = zext <32 x i8> %b to <32 x i16>162 %e = sub <32 x i16> %c, %d163 ret <32 x i16> %e164}165 166define <16 x i32> @vwsubu_v16i32(ptr %x, ptr %y) {167; CHECK-LABEL: vwsubu_v16i32:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma170; CHECK-NEXT: vle16.v v12, (a0)171; CHECK-NEXT: vle16.v v14, (a1)172; CHECK-NEXT: vwsubu.vv v8, v12, v14173; CHECK-NEXT: ret174 %a = load <16 x i16>, ptr %x175 %b = load <16 x i16>, ptr %y176 %c = zext <16 x i16> %a to <16 x i32>177 %d = zext <16 x i16> %b to <16 x i32>178 %e = sub <16 x i32> %c, %d179 ret <16 x i32> %e180}181 182define <8 x i64> @vwsubu_v8i64(ptr %x, ptr %y) {183; CHECK-LABEL: vwsubu_v8i64:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma186; CHECK-NEXT: vle32.v v12, (a0)187; CHECK-NEXT: vle32.v v14, (a1)188; CHECK-NEXT: vwsubu.vv v8, v12, v14189; CHECK-NEXT: ret190 %a = load <8 x i32>, ptr %x191 %b = load <8 x i32>, ptr %y192 %c = zext <8 x i32> %a to <8 x i64>193 %d = zext <8 x i32> %b to <8 x i64>194 %e = sub <8 x i64> %c, %d195 ret <8 x i64> %e196}197 198define <64 x i16> @vwsubu_v64i16(ptr %x, ptr %y) {199; CHECK-LABEL: vwsubu_v64i16:200; CHECK: # %bb.0:201; CHECK-NEXT: li a2, 64202; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma203; CHECK-NEXT: vle8.v v16, (a0)204; CHECK-NEXT: vle8.v v20, (a1)205; CHECK-NEXT: vwsubu.vv v8, v16, v20206; CHECK-NEXT: ret207 %a = load <64 x i8>, ptr %x208 %b = load <64 x i8>, ptr %y209 %c = zext <64 x i8> %a to <64 x i16>210 %d = zext <64 x i8> %b to <64 x i16>211 %e = sub <64 x i16> %c, %d212 ret <64 x i16> %e213}214 215define <32 x i32> @vwsubu_v32i32(ptr %x, ptr %y) {216; CHECK-LABEL: vwsubu_v32i32:217; CHECK: # %bb.0:218; CHECK-NEXT: li a2, 32219; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma220; CHECK-NEXT: vle16.v v16, (a0)221; CHECK-NEXT: vle16.v v20, (a1)222; CHECK-NEXT: vwsubu.vv v8, v16, v20223; CHECK-NEXT: ret224 %a = load <32 x i16>, ptr %x225 %b = load <32 x i16>, ptr %y226 %c = zext <32 x i16> %a to <32 x i32>227 %d = zext <32 x i16> %b to <32 x i32>228 %e = sub <32 x i32> %c, %d229 ret <32 x i32> %e230}231 232define <16 x i64> @vwsubu_v16i64(ptr %x, ptr %y) {233; CHECK-LABEL: vwsubu_v16i64:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma236; CHECK-NEXT: vle32.v v16, (a0)237; CHECK-NEXT: vle32.v v20, (a1)238; CHECK-NEXT: vwsubu.vv v8, v16, v20239; CHECK-NEXT: ret240 %a = load <16 x i32>, ptr %x241 %b = load <16 x i32>, ptr %y242 %c = zext <16 x i32> %a to <16 x i64>243 %d = zext <16 x i32> %b to <16 x i64>244 %e = sub <16 x i64> %c, %d245 ret <16 x i64> %e246}247 248define <128 x i16> @vwsubu_v128i16(ptr %x, ptr %y) nounwind {249; CHECK-LABEL: vwsubu_v128i16:250; CHECK: # %bb.0:251; CHECK-NEXT: addi sp, sp, -16252; CHECK-NEXT: csrr a2, vlenb253; CHECK-NEXT: slli a2, a2, 3254; CHECK-NEXT: sub sp, sp, a2255; CHECK-NEXT: li a2, 128256; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma257; CHECK-NEXT: vle8.v v16, (a0)258; CHECK-NEXT: vle8.v v24, (a1)259; CHECK-NEXT: li a0, 64260; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma261; CHECK-NEXT: vslidedown.vx v8, v16, a0262; CHECK-NEXT: addi a1, sp, 16263; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill264; CHECK-NEXT: vslidedown.vx v0, v24, a0265; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma266; CHECK-NEXT: vwsubu.vv v8, v16, v24267; CHECK-NEXT: addi a0, sp, 16268; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload269; CHECK-NEXT: vwsubu.vv v16, v24, v0270; CHECK-NEXT: csrr a0, vlenb271; CHECK-NEXT: slli a0, a0, 3272; CHECK-NEXT: add sp, sp, a0273; CHECK-NEXT: addi sp, sp, 16274; CHECK-NEXT: ret275 %a = load <128 x i8>, ptr %x276 %b = load <128 x i8>, ptr %y277 %c = zext <128 x i8> %a to <128 x i16>278 %d = zext <128 x i8> %b to <128 x i16>279 %e = sub <128 x i16> %c, %d280 ret <128 x i16> %e281}282 283define <64 x i32> @vwsubu_v64i32(ptr %x, ptr %y) nounwind {284; CHECK-LABEL: vwsubu_v64i32:285; CHECK: # %bb.0:286; CHECK-NEXT: addi sp, sp, -16287; CHECK-NEXT: csrr a2, vlenb288; CHECK-NEXT: slli a2, a2, 3289; CHECK-NEXT: sub sp, sp, a2290; CHECK-NEXT: li a2, 64291; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma292; CHECK-NEXT: vle16.v v16, (a0)293; CHECK-NEXT: vle16.v v24, (a1)294; CHECK-NEXT: li a0, 32295; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma296; CHECK-NEXT: vslidedown.vx v8, v16, a0297; CHECK-NEXT: addi a1, sp, 16298; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill299; CHECK-NEXT: vslidedown.vx v0, v24, a0300; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma301; CHECK-NEXT: vwsubu.vv v8, v16, v24302; CHECK-NEXT: addi a0, sp, 16303; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload304; CHECK-NEXT: vwsubu.vv v16, v24, v0305; CHECK-NEXT: csrr a0, vlenb306; CHECK-NEXT: slli a0, a0, 3307; CHECK-NEXT: add sp, sp, a0308; CHECK-NEXT: addi sp, sp, 16309; CHECK-NEXT: ret310 %a = load <64 x i16>, ptr %x311 %b = load <64 x i16>, ptr %y312 %c = zext <64 x i16> %a to <64 x i32>313 %d = zext <64 x i16> %b to <64 x i32>314 %e = sub <64 x i32> %c, %d315 ret <64 x i32> %e316}317 318define <32 x i64> @vwsubu_v32i64(ptr %x, ptr %y) nounwind {319; CHECK-LABEL: vwsubu_v32i64:320; CHECK: # %bb.0:321; CHECK-NEXT: addi sp, sp, -16322; CHECK-NEXT: csrr a2, vlenb323; CHECK-NEXT: slli a2, a2, 3324; CHECK-NEXT: sub sp, sp, a2325; CHECK-NEXT: li a2, 32326; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma327; CHECK-NEXT: vle32.v v16, (a0)328; CHECK-NEXT: vle32.v v24, (a1)329; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma330; CHECK-NEXT: vslidedown.vi v8, v16, 16331; CHECK-NEXT: addi a0, sp, 16332; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill333; CHECK-NEXT: vslidedown.vi v0, v24, 16334; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma335; CHECK-NEXT: vwsubu.vv v8, v16, v24336; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload337; CHECK-NEXT: vwsubu.vv v16, v24, v0338; CHECK-NEXT: csrr a0, vlenb339; CHECK-NEXT: slli a0, a0, 3340; CHECK-NEXT: add sp, sp, a0341; CHECK-NEXT: addi sp, sp, 16342; CHECK-NEXT: ret343 %a = load <32 x i32>, ptr %x344 %b = load <32 x i32>, ptr %y345 %c = zext <32 x i32> %a to <32 x i64>346 %d = zext <32 x i32> %b to <32 x i64>347 %e = sub <32 x i64> %c, %d348 ret <32 x i64> %e349}350 351define <2 x i32> @vwsubu_v2i32_v2i8(ptr %x, ptr %y) {352; CHECK-LABEL: vwsubu_v2i32_v2i8:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma355; CHECK-NEXT: vle8.v v8, (a0)356; CHECK-NEXT: vle8.v v9, (a1)357; CHECK-NEXT: vwsubu.vv v10, v8, v9358; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma359; CHECK-NEXT: vsext.vf2 v8, v10360; CHECK-NEXT: ret361 %a = load <2 x i8>, ptr %x362 %b = load <2 x i8>, ptr %y363 %c = zext <2 x i8> %a to <2 x i32>364 %d = zext <2 x i8> %b to <2 x i32>365 %e = sub <2 x i32> %c, %d366 ret <2 x i32> %e367}368 369define <4 x i32> @vwsubu_v4i32_v4i8_v4i16(ptr %x, ptr %y) {370; CHECK-LABEL: vwsubu_v4i32_v4i8_v4i16:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma373; CHECK-NEXT: vle8.v v8, (a0)374; CHECK-NEXT: vle16.v v9, (a1)375; CHECK-NEXT: vzext.vf2 v10, v8376; CHECK-NEXT: vwsubu.vv v8, v10, v9377; CHECK-NEXT: ret378 %a = load <4 x i8>, ptr %x379 %b = load <4 x i16>, ptr %y380 %c = zext <4 x i8> %a to <4 x i32>381 %d = zext <4 x i16> %b to <4 x i32>382 %e = sub <4 x i32> %c, %d383 ret <4 x i32> %e384}385 386define <4 x i64> @vwsubu_v4i64_v4i32_v4i8(ptr %x, ptr %y) {387; CHECK-LABEL: vwsubu_v4i64_v4i32_v4i8:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma390; CHECK-NEXT: vle8.v v8, (a1)391; CHECK-NEXT: vle32.v v10, (a0)392; CHECK-NEXT: vzext.vf4 v11, v8393; CHECK-NEXT: vwsubu.vv v8, v10, v11394; CHECK-NEXT: ret395 %a = load <4 x i32>, ptr %x396 %b = load <4 x i8>, ptr %y397 %c = zext <4 x i32> %a to <4 x i64>398 %d = zext <4 x i8> %b to <4 x i64>399 %e = sub <4 x i64> %c, %d400 ret <4 x i64> %e401}402 403define <2 x i16> @vwsubu_vx_v2i16(ptr %x, i8 %y) {404; CHECK-LABEL: vwsubu_vx_v2i16:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma407; CHECK-NEXT: vle8.v v9, (a0)408; CHECK-NEXT: vwsubu.vx v8, v9, a1409; CHECK-NEXT: ret410 %a = load <2 x i8>, ptr %x411 %b = insertelement <2 x i8> poison, i8 %y, i32 0412 %c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer413 %d = zext <2 x i8> %a to <2 x i16>414 %e = zext <2 x i8> %c to <2 x i16>415 %f = sub <2 x i16> %d, %e416 ret <2 x i16> %f417}418 419define <4 x i16> @vwsubu_vx_v4i16(ptr %x, i8 %y) {420; CHECK-LABEL: vwsubu_vx_v4i16:421; CHECK: # %bb.0:422; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma423; CHECK-NEXT: vle8.v v9, (a0)424; CHECK-NEXT: vwsubu.vx v8, v9, a1425; CHECK-NEXT: ret426 %a = load <4 x i8>, ptr %x427 %b = insertelement <4 x i8> poison, i8 %y, i32 0428 %c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer429 %d = zext <4 x i8> %a to <4 x i16>430 %e = zext <4 x i8> %c to <4 x i16>431 %f = sub <4 x i16> %d, %e432 ret <4 x i16> %f433}434 435define <2 x i32> @vwsubu_vx_v2i32(ptr %x, i16 %y) {436; CHECK-LABEL: vwsubu_vx_v2i32:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma439; CHECK-NEXT: vle16.v v9, (a0)440; CHECK-NEXT: vwsubu.vx v8, v9, a1441; CHECK-NEXT: ret442 %a = load <2 x i16>, ptr %x443 %b = insertelement <2 x i16> poison, i16 %y, i32 0444 %c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer445 %d = zext <2 x i16> %a to <2 x i32>446 %e = zext <2 x i16> %c to <2 x i32>447 %f = sub <2 x i32> %d, %e448 ret <2 x i32> %f449}450 451define <8 x i16> @vwsubu_vx_v8i16(ptr %x, i8 %y) {452; CHECK-LABEL: vwsubu_vx_v8i16:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma455; CHECK-NEXT: vle8.v v9, (a0)456; CHECK-NEXT: vwsubu.vx v8, v9, a1457; CHECK-NEXT: ret458 %a = load <8 x i8>, ptr %x459 %b = insertelement <8 x i8> poison, i8 %y, i32 0460 %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer461 %d = zext <8 x i8> %a to <8 x i16>462 %e = zext <8 x i8> %c to <8 x i16>463 %f = sub <8 x i16> %d, %e464 ret <8 x i16> %f465}466 467define <4 x i32> @vwsubu_vx_v4i32(ptr %x, i16 %y) {468; CHECK-LABEL: vwsubu_vx_v4i32:469; CHECK: # %bb.0:470; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma471; CHECK-NEXT: vle16.v v9, (a0)472; CHECK-NEXT: vwsubu.vx v8, v9, a1473; CHECK-NEXT: ret474 %a = load <4 x i16>, ptr %x475 %b = insertelement <4 x i16> poison, i16 %y, i32 0476 %c = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer477 %d = zext <4 x i16> %a to <4 x i32>478 %e = zext <4 x i16> %c to <4 x i32>479 %f = sub <4 x i32> %d, %e480 ret <4 x i32> %f481}482 483define <2 x i64> @vwsubu_vx_v2i64(ptr %x, i32 %y) {484; CHECK-LABEL: vwsubu_vx_v2i64:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma487; CHECK-NEXT: vle32.v v9, (a0)488; CHECK-NEXT: vwsubu.vx v8, v9, a1489; CHECK-NEXT: ret490 %a = load <2 x i32>, ptr %x491 %b = insertelement <2 x i32> poison, i32 %y, i64 0492 %c = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer493 %d = zext <2 x i32> %a to <2 x i64>494 %e = zext <2 x i32> %c to <2 x i64>495 %f = sub <2 x i64> %d, %e496 ret <2 x i64> %f497}498 499define <16 x i16> @vwsubu_vx_v16i16(ptr %x, i8 %y) {500; CHECK-LABEL: vwsubu_vx_v16i16:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma503; CHECK-NEXT: vle8.v v10, (a0)504; CHECK-NEXT: vwsubu.vx v8, v10, a1505; CHECK-NEXT: ret506 %a = load <16 x i8>, ptr %x507 %b = insertelement <16 x i8> poison, i8 %y, i32 0508 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer509 %d = zext <16 x i8> %a to <16 x i16>510 %e = zext <16 x i8> %c to <16 x i16>511 %f = sub <16 x i16> %d, %e512 ret <16 x i16> %f513}514 515define <8 x i32> @vwsubu_vx_v8i32(ptr %x, i16 %y) {516; CHECK-LABEL: vwsubu_vx_v8i32:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma519; CHECK-NEXT: vle16.v v10, (a0)520; CHECK-NEXT: vwsubu.vx v8, v10, a1521; CHECK-NEXT: ret522 %a = load <8 x i16>, ptr %x523 %b = insertelement <8 x i16> poison, i16 %y, i32 0524 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer525 %d = zext <8 x i16> %a to <8 x i32>526 %e = zext <8 x i16> %c to <8 x i32>527 %f = sub <8 x i32> %d, %e528 ret <8 x i32> %f529}530 531define <4 x i64> @vwsubu_vx_v4i64(ptr %x, i32 %y) {532; CHECK-LABEL: vwsubu_vx_v4i64:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma535; CHECK-NEXT: vle32.v v10, (a0)536; CHECK-NEXT: vwsubu.vx v8, v10, a1537; CHECK-NEXT: ret538 %a = load <4 x i32>, ptr %x539 %b = insertelement <4 x i32> poison, i32 %y, i64 0540 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer541 %d = zext <4 x i32> %a to <4 x i64>542 %e = zext <4 x i32> %c to <4 x i64>543 %f = sub <4 x i64> %d, %e544 ret <4 x i64> %f545}546 547define <32 x i16> @vwsubu_vx_v32i16(ptr %x, i8 %y) {548; CHECK-LABEL: vwsubu_vx_v32i16:549; CHECK: # %bb.0:550; CHECK-NEXT: li a2, 32551; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma552; CHECK-NEXT: vle8.v v12, (a0)553; CHECK-NEXT: vwsubu.vx v8, v12, a1554; CHECK-NEXT: ret555 %a = load <32 x i8>, ptr %x556 %b = insertelement <32 x i8> poison, i8 %y, i32 0557 %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer558 %d = zext <32 x i8> %a to <32 x i16>559 %e = zext <32 x i8> %c to <32 x i16>560 %f = sub <32 x i16> %d, %e561 ret <32 x i16> %f562}563 564define <16 x i32> @vwsubu_vx_v16i32(ptr %x, i16 %y) {565; CHECK-LABEL: vwsubu_vx_v16i32:566; CHECK: # %bb.0:567; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma568; CHECK-NEXT: vle16.v v12, (a0)569; CHECK-NEXT: vwsubu.vx v8, v12, a1570; CHECK-NEXT: ret571 %a = load <16 x i16>, ptr %x572 %b = insertelement <16 x i16> poison, i16 %y, i32 0573 %c = shufflevector <16 x i16> %b, <16 x i16> poison, <16 x i32> zeroinitializer574 %d = zext <16 x i16> %a to <16 x i32>575 %e = zext <16 x i16> %c to <16 x i32>576 %f = sub <16 x i32> %d, %e577 ret <16 x i32> %f578}579 580define <8 x i64> @vwsubu_vx_v8i64(ptr %x, i32 %y) {581; CHECK-LABEL: vwsubu_vx_v8i64:582; CHECK: # %bb.0:583; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma584; CHECK-NEXT: vle32.v v12, (a0)585; CHECK-NEXT: vwsubu.vx v8, v12, a1586; CHECK-NEXT: ret587 %a = load <8 x i32>, ptr %x588 %b = insertelement <8 x i32> poison, i32 %y, i64 0589 %c = shufflevector <8 x i32> %b, <8 x i32> poison, <8 x i32> zeroinitializer590 %d = zext <8 x i32> %a to <8 x i64>591 %e = zext <8 x i32> %c to <8 x i64>592 %f = sub <8 x i64> %d, %e593 ret <8 x i64> %f594}595 596define <64 x i16> @vwsubu_vx_v64i16(ptr %x, i8 %y) {597; CHECK-LABEL: vwsubu_vx_v64i16:598; CHECK: # %bb.0:599; CHECK-NEXT: li a2, 64600; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma601; CHECK-NEXT: vle8.v v16, (a0)602; CHECK-NEXT: vwsubu.vx v8, v16, a1603; CHECK-NEXT: ret604 %a = load <64 x i8>, ptr %x605 %b = insertelement <64 x i8> poison, i8 %y, i32 0606 %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer607 %d = zext <64 x i8> %a to <64 x i16>608 %e = zext <64 x i8> %c to <64 x i16>609 %f = sub <64 x i16> %d, %e610 ret <64 x i16> %f611}612 613define <32 x i32> @vwsubu_vx_v32i32(ptr %x, i16 %y) {614; CHECK-LABEL: vwsubu_vx_v32i32:615; CHECK: # %bb.0:616; CHECK-NEXT: li a2, 32617; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma618; CHECK-NEXT: vle16.v v16, (a0)619; CHECK-NEXT: vwsubu.vx v8, v16, a1620; CHECK-NEXT: ret621 %a = load <32 x i16>, ptr %x622 %b = insertelement <32 x i16> poison, i16 %y, i32 0623 %c = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer624 %d = zext <32 x i16> %a to <32 x i32>625 %e = zext <32 x i16> %c to <32 x i32>626 %f = sub <32 x i32> %d, %e627 ret <32 x i32> %f628}629 630define <16 x i64> @vwsubu_vx_v16i64(ptr %x, i32 %y) {631; CHECK-LABEL: vwsubu_vx_v16i64:632; CHECK: # %bb.0:633; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma634; CHECK-NEXT: vle32.v v16, (a0)635; CHECK-NEXT: vwsubu.vx v8, v16, a1636; CHECK-NEXT: ret637 %a = load <16 x i32>, ptr %x638 %b = insertelement <16 x i32> poison, i32 %y, i64 0639 %c = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer640 %d = zext <16 x i32> %a to <16 x i64>641 %e = zext <16 x i32> %c to <16 x i64>642 %f = sub <16 x i64> %d, %e643 ret <16 x i64> %f644}645 646define <8 x i16> @vwsubu_vx_v8i16_i8(ptr %x, ptr %y) {647; CHECK-LABEL: vwsubu_vx_v8i16_i8:648; CHECK: # %bb.0:649; CHECK-NEXT: lbu a1, 0(a1)650; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma651; CHECK-NEXT: vle8.v v9, (a0)652; CHECK-NEXT: vmv.v.x v10, a1653; CHECK-NEXT: vwsubu.vv v8, v10, v9654; CHECK-NEXT: ret655 %a = load <8 x i8>, ptr %x656 %b = load i8, ptr %y657 %c = zext i8 %b to i16658 %d = insertelement <8 x i16> poison, i16 %c, i32 0659 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer660 %f = zext <8 x i8> %a to <8 x i16>661 %g = sub <8 x i16> %e, %f662 ret <8 x i16> %g663}664 665define <8 x i16> @vwsubu_vx_v8i16_i16(ptr %x, ptr %y) {666; CHECK-LABEL: vwsubu_vx_v8i16_i16:667; CHECK: # %bb.0:668; CHECK-NEXT: lh a1, 0(a1)669; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma670; CHECK-NEXT: vle8.v v9, (a0)671; CHECK-NEXT: vmv.v.x v8, a1672; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma673; CHECK-NEXT: vwsubu.wv v8, v8, v9674; CHECK-NEXT: ret675 %a = load <8 x i8>, ptr %x676 %b = load i16, ptr %y677 %d = insertelement <8 x i16> poison, i16 %b, i32 0678 %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer679 %f = zext <8 x i8> %a to <8 x i16>680 %g = sub <8 x i16> %e, %f681 ret <8 x i16> %g682}683 684define <4 x i32> @vwsubu_vx_v4i32_i8(ptr %x, ptr %y) {685; CHECK-LABEL: vwsubu_vx_v4i32_i8:686; CHECK: # %bb.0:687; CHECK-NEXT: lbu a1, 0(a1)688; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma689; CHECK-NEXT: vle16.v v9, (a0)690; CHECK-NEXT: vmv.v.x v10, a1691; CHECK-NEXT: vwsubu.vv v8, v10, v9692; CHECK-NEXT: ret693 %a = load <4 x i16>, ptr %x694 %b = load i8, ptr %y695 %c = zext i8 %b to i32696 %d = insertelement <4 x i32> poison, i32 %c, i32 0697 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer698 %f = zext <4 x i16> %a to <4 x i32>699 %g = sub <4 x i32> %e, %f700 ret <4 x i32> %g701}702 703define <4 x i32> @vwsubu_vx_v4i32_i16(ptr %x, ptr %y) {704; CHECK-LABEL: vwsubu_vx_v4i32_i16:705; CHECK: # %bb.0:706; CHECK-NEXT: lhu a1, 0(a1)707; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma708; CHECK-NEXT: vle16.v v9, (a0)709; CHECK-NEXT: vmv.v.x v10, a1710; CHECK-NEXT: vwsubu.vv v8, v10, v9711; CHECK-NEXT: ret712 %a = load <4 x i16>, ptr %x713 %b = load i16, ptr %y714 %c = zext i16 %b to i32715 %d = insertelement <4 x i32> poison, i32 %c, i32 0716 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer717 %f = zext <4 x i16> %a to <4 x i32>718 %g = sub <4 x i32> %e, %f719 ret <4 x i32> %g720}721 722define <4 x i32> @vwsubu_vx_v4i32_i32(ptr %x, ptr %y) {723; CHECK-LABEL: vwsubu_vx_v4i32_i32:724; CHECK: # %bb.0:725; CHECK-NEXT: lw a1, 0(a1)726; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma727; CHECK-NEXT: vle16.v v9, (a0)728; CHECK-NEXT: vmv.v.x v8, a1729; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma730; CHECK-NEXT: vwsubu.wv v8, v8, v9731; CHECK-NEXT: ret732 %a = load <4 x i16>, ptr %x733 %b = load i32, ptr %y734 %d = insertelement <4 x i32> poison, i32 %b, i32 0735 %e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer736 %f = zext <4 x i16> %a to <4 x i32>737 %g = sub <4 x i32> %e, %f738 ret <4 x i32> %g739}740 741define <2 x i64> @vwsubu_vx_v2i64_i8(ptr %x, ptr %y) nounwind {742; RV32-LABEL: vwsubu_vx_v2i64_i8:743; RV32: # %bb.0:744; RV32-NEXT: addi sp, sp, -16745; RV32-NEXT: lbu a1, 0(a1)746; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma747; RV32-NEXT: vle32.v v9, (a0)748; RV32-NEXT: sw a1, 8(sp)749; RV32-NEXT: sw zero, 12(sp)750; RV32-NEXT: addi a0, sp, 8751; RV32-NEXT: vlse64.v v8, (a0), zero752; RV32-NEXT: vwsubu.wv v8, v8, v9753; RV32-NEXT: addi sp, sp, 16754; RV32-NEXT: ret755;756; RV64-LABEL: vwsubu_vx_v2i64_i8:757; RV64: # %bb.0:758; RV64-NEXT: lbu a1, 0(a1)759; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma760; RV64-NEXT: vle32.v v9, (a0)761; RV64-NEXT: vmv.v.x v10, a1762; RV64-NEXT: vwsubu.vv v8, v10, v9763; RV64-NEXT: ret764 %a = load <2 x i32>, ptr %x765 %b = load i8, ptr %y766 %c = zext i8 %b to i64767 %d = insertelement <2 x i64> poison, i64 %c, i64 0768 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer769 %f = zext <2 x i32> %a to <2 x i64>770 %g = sub <2 x i64> %e, %f771 ret <2 x i64> %g772}773 774define <2 x i64> @vwsubu_vx_v2i64_i16(ptr %x, ptr %y) nounwind {775; RV32-LABEL: vwsubu_vx_v2i64_i16:776; RV32: # %bb.0:777; RV32-NEXT: addi sp, sp, -16778; RV32-NEXT: lhu a1, 0(a1)779; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma780; RV32-NEXT: vle32.v v9, (a0)781; RV32-NEXT: sw a1, 8(sp)782; RV32-NEXT: sw zero, 12(sp)783; RV32-NEXT: addi a0, sp, 8784; RV32-NEXT: vlse64.v v8, (a0), zero785; RV32-NEXT: vwsubu.wv v8, v8, v9786; RV32-NEXT: addi sp, sp, 16787; RV32-NEXT: ret788;789; RV64-LABEL: vwsubu_vx_v2i64_i16:790; RV64: # %bb.0:791; RV64-NEXT: lhu a1, 0(a1)792; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma793; RV64-NEXT: vle32.v v9, (a0)794; RV64-NEXT: vmv.v.x v10, a1795; RV64-NEXT: vwsubu.vv v8, v10, v9796; RV64-NEXT: ret797 %a = load <2 x i32>, ptr %x798 %b = load i16, ptr %y799 %c = zext i16 %b to i64800 %d = insertelement <2 x i64> poison, i64 %c, i64 0801 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer802 %f = zext <2 x i32> %a to <2 x i64>803 %g = sub <2 x i64> %e, %f804 ret <2 x i64> %g805}806 807define <2 x i64> @vwsubu_vx_v2i64_i32(ptr %x, ptr %y) nounwind {808; RV32-LABEL: vwsubu_vx_v2i64_i32:809; RV32: # %bb.0:810; RV32-NEXT: addi sp, sp, -16811; RV32-NEXT: lw a1, 0(a1)812; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma813; RV32-NEXT: vle32.v v9, (a0)814; RV32-NEXT: sw a1, 8(sp)815; RV32-NEXT: sw zero, 12(sp)816; RV32-NEXT: addi a0, sp, 8817; RV32-NEXT: vlse64.v v8, (a0), zero818; RV32-NEXT: vwsubu.wv v8, v8, v9819; RV32-NEXT: addi sp, sp, 16820; RV32-NEXT: ret821;822; RV64-LABEL: vwsubu_vx_v2i64_i32:823; RV64: # %bb.0:824; RV64-NEXT: lw a1, 0(a1)825; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma826; RV64-NEXT: vle32.v v9, (a0)827; RV64-NEXT: vmv.v.x v10, a1828; RV64-NEXT: vwsubu.vv v8, v10, v9829; RV64-NEXT: ret830 %a = load <2 x i32>, ptr %x831 %b = load i32, ptr %y832 %c = zext i32 %b to i64833 %d = insertelement <2 x i64> poison, i64 %c, i64 0834 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer835 %f = zext <2 x i32> %a to <2 x i64>836 %g = sub <2 x i64> %e, %f837 ret <2 x i64> %g838}839 840define <2 x i64> @vwsubu_vx_v2i64_i64(ptr %x, ptr %y) nounwind {841; RV32-LABEL: vwsubu_vx_v2i64_i64:842; RV32: # %bb.0:843; RV32-NEXT: addi sp, sp, -16844; RV32-NEXT: lw a2, 0(a1)845; RV32-NEXT: lw a1, 4(a1)846; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma847; RV32-NEXT: vle32.v v9, (a0)848; RV32-NEXT: sw a2, 8(sp)849; RV32-NEXT: sw a1, 12(sp)850; RV32-NEXT: addi a0, sp, 8851; RV32-NEXT: vlse64.v v8, (a0), zero852; RV32-NEXT: vwsubu.wv v8, v8, v9853; RV32-NEXT: addi sp, sp, 16854; RV32-NEXT: ret855;856; RV64-LABEL: vwsubu_vx_v2i64_i64:857; RV64: # %bb.0:858; RV64-NEXT: ld a1, 0(a1)859; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma860; RV64-NEXT: vle32.v v9, (a0)861; RV64-NEXT: vmv.v.x v8, a1862; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma863; RV64-NEXT: vwsubu.wv v8, v8, v9864; RV64-NEXT: ret865 %a = load <2 x i32>, ptr %x866 %b = load i64, ptr %y867 %d = insertelement <2 x i64> poison, i64 %b, i64 0868 %e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer869 %f = zext <2 x i32> %a to <2 x i64>870 %g = sub <2 x i64> %e, %f871 ret <2 x i64> %g872}873 874define <2 x i32> @vwsubu_v2i32_of_v2i8(ptr %x, ptr %y) {875; CHECK-LABEL: vwsubu_v2i32_of_v2i8:876; CHECK: # %bb.0:877; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma878; CHECK-NEXT: vle8.v v8, (a0)879; CHECK-NEXT: vle8.v v9, (a1)880; CHECK-NEXT: vwsubu.vv v10, v8, v9881; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma882; CHECK-NEXT: vsext.vf2 v8, v10883; CHECK-NEXT: ret884 %a = load <2 x i8>, ptr %x885 %b = load <2 x i8>, ptr %y886 %c = zext <2 x i8> %a to <2 x i32>887 %d = zext <2 x i8> %b to <2 x i32>888 %e = sub <2 x i32> %c, %d889 ret <2 x i32> %e890}891 892define <2 x i64> @vwsubu_v2i64_of_v2i8(ptr %x, ptr %y) {893; CHECK-LABEL: vwsubu_v2i64_of_v2i8:894; CHECK: # %bb.0:895; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma896; CHECK-NEXT: vle8.v v8, (a0)897; CHECK-NEXT: vle8.v v9, (a1)898; CHECK-NEXT: vwsubu.vv v10, v8, v9899; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma900; CHECK-NEXT: vsext.vf4 v8, v10901; CHECK-NEXT: ret902 %a = load <2 x i8>, ptr %x903 %b = load <2 x i8>, ptr %y904 %c = zext <2 x i8> %a to <2 x i64>905 %d = zext <2 x i8> %b to <2 x i64>906 %e = sub <2 x i64> %c, %d907 ret <2 x i64> %e908}909 910define <2 x i64> @vwsubu_v2i64_of_v2i16(ptr %x, ptr %y) {911; CHECK-LABEL: vwsubu_v2i64_of_v2i16:912; CHECK: # %bb.0:913; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma914; CHECK-NEXT: vle16.v v8, (a0)915; CHECK-NEXT: vle16.v v9, (a1)916; CHECK-NEXT: vwsubu.vv v10, v8, v9917; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma918; CHECK-NEXT: vsext.vf2 v8, v10919; CHECK-NEXT: ret920 %a = load <2 x i16>, ptr %x921 %b = load <2 x i16>, ptr %y922 %c = zext <2 x i16> %a to <2 x i64>923 %d = zext <2 x i16> %b to <2 x i64>924 %e = sub <2 x i64> %c, %d925 ret <2 x i64> %e926}927