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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s4 5define <4 x i16> @vzext_v4i16_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {6; CHECK-LABEL: vzext_v4i16_v4i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma9; CHECK-NEXT: vzext.vf2 v9, v8, v0.t10; CHECK-NEXT: vmv1r.v v8, v911; CHECK-NEXT: ret12 %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)13 ret <4 x i16> %v14}15 16define <4 x i16> @vzext_v4i16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {17; CHECK-LABEL: vzext_v4i16_v4i8_unmasked:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma20; CHECK-NEXT: vzext.vf2 v9, v821; CHECK-NEXT: vmv1r.v v8, v922; CHECK-NEXT: ret23 %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)24 ret <4 x i16> %v25}26 27define <4 x i32> @vzext_v4i32_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {28; CHECK-LABEL: vzext_v4i32_v4i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma31; CHECK-NEXT: vzext.vf4 v9, v8, v0.t32; CHECK-NEXT: vmv.v.v v8, v933; CHECK-NEXT: ret34 %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)35 ret <4 x i32> %v36}37 38define <4 x i32> @vzext_v4i32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {39; CHECK-LABEL: vzext_v4i32_v4i8_unmasked:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma42; CHECK-NEXT: vzext.vf4 v9, v843; CHECK-NEXT: vmv.v.v v8, v944; CHECK-NEXT: ret45 %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)46 ret <4 x i32> %v47}48 49define <4 x i64> @vzext_v4i64_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {50; CHECK-LABEL: vzext_v4i64_v4i8:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma53; CHECK-NEXT: vmv1r.v v10, v854; CHECK-NEXT: vzext.vf8 v8, v10, v0.t55; CHECK-NEXT: ret56 %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)57 ret <4 x i64> %v58}59 60define <4 x i64> @vzext_v4i64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {61; CHECK-LABEL: vzext_v4i64_v4i8_unmasked:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma64; CHECK-NEXT: vmv1r.v v10, v865; CHECK-NEXT: vzext.vf8 v8, v1066; CHECK-NEXT: ret67 %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)68 ret <4 x i64> %v69}70 71define <4 x i32> @vzext_v4i32_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: vzext_v4i32_v4i16:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma75; CHECK-NEXT: vzext.vf2 v9, v8, v0.t76; CHECK-NEXT: vmv.v.v v8, v977; CHECK-NEXT: ret78 %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)79 ret <4 x i32> %v80}81 82define <4 x i32> @vzext_v4i32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {83; CHECK-LABEL: vzext_v4i32_v4i16_unmasked:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma86; CHECK-NEXT: vzext.vf2 v9, v887; CHECK-NEXT: vmv.v.v v8, v988; CHECK-NEXT: ret89 %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)90 ret <4 x i32> %v91}92 93define <4 x i64> @vzext_v4i64_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {94; CHECK-LABEL: vzext_v4i64_v4i16:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma97; CHECK-NEXT: vmv1r.v v10, v898; CHECK-NEXT: vzext.vf4 v8, v10, v0.t99; CHECK-NEXT: ret100 %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)101 ret <4 x i64> %v102}103 104define <4 x i64> @vzext_v4i64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {105; CHECK-LABEL: vzext_v4i64_v4i16_unmasked:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma108; CHECK-NEXT: vmv1r.v v10, v8109; CHECK-NEXT: vzext.vf4 v8, v10110; CHECK-NEXT: ret111 %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)112 ret <4 x i64> %v113}114 115define <4 x i64> @vzext_v4i64_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {116; CHECK-LABEL: vzext_v4i64_v4i32:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma119; CHECK-NEXT: vmv1r.v v10, v8120; CHECK-NEXT: vzext.vf2 v8, v10, v0.t121; CHECK-NEXT: ret122 %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)123 ret <4 x i64> %v124}125 126define <4 x i64> @vzext_v4i64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {127; CHECK-LABEL: vzext_v4i64_v4i32_unmasked:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma130; CHECK-NEXT: vmv1r.v v10, v8131; CHECK-NEXT: vzext.vf2 v8, v10132; CHECK-NEXT: ret133 %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)134 ret <4 x i64> %v135}136 137define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext %evl) {138; CHECK-LABEL: vzext_v32i64_v32i32:139; CHECK: # %bb.0:140; CHECK-NEXT: li a2, 16141; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma142; CHECK-NEXT: vslidedown.vi v24, v0, 2143; CHECK-NEXT: mv a1, a0144; CHECK-NEXT: bltu a0, a2, .LBB12_2145; CHECK-NEXT: # %bb.1:146; CHECK-NEXT: li a1, 16147; CHECK-NEXT: .LBB12_2:148; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma149; CHECK-NEXT: vzext.vf2 v16, v8, v0.t150; CHECK-NEXT: addi a1, a0, -16151; CHECK-NEXT: sltu a0, a0, a1152; CHECK-NEXT: addi a0, a0, -1153; CHECK-NEXT: and a0, a0, a1154; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma155; CHECK-NEXT: vslidedown.vi v8, v8, 16156; CHECK-NEXT: vmv1r.v v0, v24157; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma158; CHECK-NEXT: vzext.vf2 v24, v8, v0.t159; CHECK-NEXT: vmv8r.v v8, v16160; CHECK-NEXT: vmv.v.v v16, v24161; CHECK-NEXT: ret162 %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl)163 ret <32 x i64> %v164}165 166define <32 x i64> @vzext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl) {167; CHECK-LABEL: vzext_v32i64_v32i32_unmasked:168; CHECK: # %bb.0:169; CHECK-NEXT: li a2, 16170; CHECK-NEXT: mv a1, a0171; CHECK-NEXT: bltu a0, a2, .LBB13_2172; CHECK-NEXT: # %bb.1:173; CHECK-NEXT: li a1, 16174; CHECK-NEXT: .LBB13_2:175; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma176; CHECK-NEXT: vzext.vf2 v24, v8177; CHECK-NEXT: addi a1, a0, -16178; CHECK-NEXT: sltu a0, a0, a1179; CHECK-NEXT: addi a0, a0, -1180; CHECK-NEXT: and a0, a0, a1181; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma182; CHECK-NEXT: vslidedown.vi v8, v8, 16183; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma184; CHECK-NEXT: vzext.vf2 v16, v8185; CHECK-NEXT: vmv8r.v v8, v24186; CHECK-NEXT: ret187 %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> splat (i1 true), i32 %evl)188 ret <32 x i64> %v189}190 191define <4 x i16> @vzext_v4i16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {192; CHECK-LABEL: vzext_v4i16_v4i7:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma195; CHECK-NEXT: vzext.vf2 v9, v8, v0.t196; CHECK-NEXT: li a0, 127197; CHECK-NEXT: vand.vx v8, v9, a0, v0.t198; CHECK-NEXT: ret199 %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl)200 ret <4 x i16> %v201}202 203define <4 x i8> @vzext_v4i8_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {204; CHECK-LABEL: vzext_v4i8_v4i7:205; CHECK: # %bb.0:206; CHECK-NEXT: li a1, 127207; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma208; CHECK-NEXT: vand.vx v8, v8, a1, v0.t209; CHECK-NEXT: ret210 %v = call <4 x i8> @llvm.vp.zext.v4i8.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl)211 ret <4 x i8> %v212}213 214define <4 x i15> @vzext_v4i15_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {215; CHECK-LABEL: vzext_v4i15_v4i8:216; CHECK: # %bb.0:217; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma218; CHECK-NEXT: vzext.vf2 v9, v8, v0.t219; CHECK-NEXT: vmv1r.v v8, v9220; CHECK-NEXT: ret221 %v = call <4 x i15> @llvm.vp.zext.v4i15.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)222 ret <4 x i15> %v223}224 225define <4 x i15> @vzext_v4i15_v4i9(<4 x i9> %va, <4 x i1> %m, i32 zeroext %evl) {226; CHECK-LABEL: vzext_v4i15_v4i9:227; CHECK: # %bb.0:228; CHECK-NEXT: li a1, 511229; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma230; CHECK-NEXT: vand.vx v8, v8, a1, v0.t231; CHECK-NEXT: ret232 %v = call <4 x i15> @llvm.vp.zext.v4i15.v4i9(<4 x i9> %va, <4 x i1> %m, i32 %evl)233 ret <4 x i15> %v234}235