1685 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NODOT3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NODOT4; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT325; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvqdotq -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DOT,DOT646 7define i32 @vqdot_vv(<16 x i8> %a, <16 x i8> %b) {8; NODOT-LABEL: vqdot_vv:9; NODOT: # %bb.0: # %entry10; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma11; NODOT-NEXT: vsext.vf2 v12, v812; NODOT-NEXT: vsext.vf2 v14, v913; NODOT-NEXT: vwmul.vv v8, v12, v1414; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma15; NODOT-NEXT: vmv.s.x v12, zero16; NODOT-NEXT: vredsum.vs v8, v8, v1217; NODOT-NEXT: vmv.x.s a0, v818; NODOT-NEXT: ret19;20; DOT-LABEL: vqdot_vv:21; DOT: # %bb.0: # %entry22; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma23; DOT-NEXT: vmv.v.i v10, 024; DOT-NEXT: vqdot.vv v10, v8, v925; DOT-NEXT: vmv.s.x v8, zero26; DOT-NEXT: vredsum.vs v8, v10, v827; DOT-NEXT: vmv.x.s a0, v828; DOT-NEXT: ret29entry:30 %a.sext = sext <16 x i8> %a to <16 x i32>31 %b.sext = sext <16 x i8> %b to <16 x i32>32 %mul = mul <16 x i32> %a.sext, %b.sext33 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)34 ret i32 %res35}36 37define i32 @vqdot_vx_constant(<16 x i8> %a) {38; CHECK-LABEL: vqdot_vx_constant:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma41; CHECK-NEXT: vsext.vf2 v12, v842; CHECK-NEXT: li a0, 2343; CHECK-NEXT: vwmul.vx v8, v12, a044; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma45; CHECK-NEXT: vmv.s.x v12, zero46; CHECK-NEXT: vredsum.vs v8, v8, v1247; CHECK-NEXT: vmv.x.s a0, v848; CHECK-NEXT: ret49entry:50 %a.sext = sext <16 x i8> %a to <16 x i32>51 %mul = mul <16 x i32> %a.sext, splat (i32 23)52 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)53 ret i32 %res54}55 56define i32 @vqdot_vx_constant_swapped(<16 x i8> %a) {57; CHECK-LABEL: vqdot_vx_constant_swapped:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma60; CHECK-NEXT: vsext.vf2 v12, v861; CHECK-NEXT: li a0, 2362; CHECK-NEXT: vwmul.vx v8, v12, a063; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma64; CHECK-NEXT: vmv.s.x v12, zero65; CHECK-NEXT: vredsum.vs v8, v8, v1266; CHECK-NEXT: vmv.x.s a0, v867; CHECK-NEXT: ret68entry:69 %a.sext = sext <16 x i8> %a to <16 x i32>70 %mul = mul <16 x i32> splat (i32 23), %a.sext71 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)72 ret i32 %res73}74 75define i32 @vqdotu_vv(<16 x i8> %a, <16 x i8> %b) {76; NODOT-LABEL: vqdotu_vv:77; NODOT: # %bb.0: # %entry78; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma79; NODOT-NEXT: vwmulu.vv v10, v8, v980; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma81; NODOT-NEXT: vmv.s.x v8, zero82; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma83; NODOT-NEXT: vwredsumu.vs v8, v10, v884; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma85; NODOT-NEXT: vmv.x.s a0, v886; NODOT-NEXT: ret87;88; DOT-LABEL: vqdotu_vv:89; DOT: # %bb.0: # %entry90; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma91; DOT-NEXT: vmv.v.i v10, 092; DOT-NEXT: vqdotu.vv v10, v8, v993; DOT-NEXT: vmv.s.x v8, zero94; DOT-NEXT: vredsum.vs v8, v10, v895; DOT-NEXT: vmv.x.s a0, v896; DOT-NEXT: ret97entry:98 %a.zext = zext <16 x i8> %a to <16 x i32>99 %b.zext = zext <16 x i8> %b to <16 x i32>100 %mul = mul <16 x i32> %a.zext, %b.zext101 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)102 ret i32 %res103}104 105define i32 @vqdotu_vx_constant(<16 x i8> %a) {106; CHECK-LABEL: vqdotu_vx_constant:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma109; CHECK-NEXT: vzext.vf2 v12, v8110; CHECK-NEXT: li a0, 123111; CHECK-NEXT: vwmulu.vx v8, v12, a0112; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma113; CHECK-NEXT: vmv.s.x v12, zero114; CHECK-NEXT: vredsum.vs v8, v8, v12115; CHECK-NEXT: vmv.x.s a0, v8116; CHECK-NEXT: ret117entry:118 %a.zext = zext <16 x i8> %a to <16 x i32>119 %mul = mul <16 x i32> %a.zext, splat (i32 123)120 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)121 ret i32 %res122}123 124define i32 @vqdotsu_vv(<16 x i8> %a, <16 x i8> %b) {125; NODOT-LABEL: vqdotsu_vv:126; NODOT: # %bb.0: # %entry127; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma128; NODOT-NEXT: vsext.vf2 v12, v8129; NODOT-NEXT: vzext.vf2 v14, v9130; NODOT-NEXT: vwmulsu.vv v8, v12, v14131; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma132; NODOT-NEXT: vmv.s.x v12, zero133; NODOT-NEXT: vredsum.vs v8, v8, v12134; NODOT-NEXT: vmv.x.s a0, v8135; NODOT-NEXT: ret136;137; DOT-LABEL: vqdotsu_vv:138; DOT: # %bb.0: # %entry139; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma140; DOT-NEXT: vmv.v.i v10, 0141; DOT-NEXT: vqdotsu.vv v10, v8, v9142; DOT-NEXT: vmv.s.x v8, zero143; DOT-NEXT: vredsum.vs v8, v10, v8144; DOT-NEXT: vmv.x.s a0, v8145; DOT-NEXT: ret146entry:147 %a.sext = sext <16 x i8> %a to <16 x i32>148 %b.zext = zext <16 x i8> %b to <16 x i32>149 %mul = mul <16 x i32> %a.sext, %b.zext150 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)151 ret i32 %res152}153 154define i32 @vqdotsu_vv_swapped(<16 x i8> %a, <16 x i8> %b) {155; NODOT-LABEL: vqdotsu_vv_swapped:156; NODOT: # %bb.0: # %entry157; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma158; NODOT-NEXT: vsext.vf2 v12, v8159; NODOT-NEXT: vzext.vf2 v14, v9160; NODOT-NEXT: vwmulsu.vv v8, v12, v14161; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma162; NODOT-NEXT: vmv.s.x v12, zero163; NODOT-NEXT: vredsum.vs v8, v8, v12164; NODOT-NEXT: vmv.x.s a0, v8165; NODOT-NEXT: ret166;167; DOT-LABEL: vqdotsu_vv_swapped:168; DOT: # %bb.0: # %entry169; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma170; DOT-NEXT: vmv.v.i v10, 0171; DOT-NEXT: vqdotsu.vv v10, v8, v9172; DOT-NEXT: vmv.s.x v8, zero173; DOT-NEXT: vredsum.vs v8, v10, v8174; DOT-NEXT: vmv.x.s a0, v8175; DOT-NEXT: ret176entry:177 %a.sext = sext <16 x i8> %a to <16 x i32>178 %b.zext = zext <16 x i8> %b to <16 x i32>179 %mul = mul <16 x i32> %b.zext, %a.sext180 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)181 ret i32 %res182}183 184define i32 @vdotqsu_vx_constant(<16 x i8> %a) {185; CHECK-LABEL: vdotqsu_vx_constant:186; CHECK: # %bb.0: # %entry187; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma188; CHECK-NEXT: vsext.vf2 v12, v8189; CHECK-NEXT: li a0, 123190; CHECK-NEXT: vwmul.vx v8, v12, a0191; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma192; CHECK-NEXT: vmv.s.x v12, zero193; CHECK-NEXT: vredsum.vs v8, v8, v12194; CHECK-NEXT: vmv.x.s a0, v8195; CHECK-NEXT: ret196entry:197 %a.sext = sext <16 x i8> %a to <16 x i32>198 %mul = mul <16 x i32> %a.sext, splat (i32 123)199 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)200 ret i32 %res201}202 203define i32 @vdotqus_vx_constant(<16 x i8> %a) {204; CHECK-LABEL: vdotqus_vx_constant:205; CHECK: # %bb.0: # %entry206; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma207; CHECK-NEXT: vzext.vf2 v12, v8208; CHECK-NEXT: li a0, -23209; CHECK-NEXT: vmv.v.x v14, a0210; CHECK-NEXT: vwmulsu.vv v8, v14, v12211; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma212; CHECK-NEXT: vmv.s.x v12, zero213; CHECK-NEXT: vredsum.vs v8, v8, v12214; CHECK-NEXT: vmv.x.s a0, v8215; CHECK-NEXT: ret216entry:217 %a.zext = zext <16 x i8> %a to <16 x i32>218 %mul = mul <16 x i32> %a.zext, splat (i32 -23)219 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)220 ret i32 %res221}222 223define i32 @reduce_of_sext(<16 x i8> %a) {224; NODOT-LABEL: reduce_of_sext:225; NODOT: # %bb.0: # %entry226; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma227; NODOT-NEXT: vsext.vf4 v12, v8228; NODOT-NEXT: vmv.s.x v8, zero229; NODOT-NEXT: vredsum.vs v8, v12, v8230; NODOT-NEXT: vmv.x.s a0, v8231; NODOT-NEXT: ret232;233; DOT-LABEL: reduce_of_sext:234; DOT: # %bb.0: # %entry235; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma236; DOT-NEXT: vmv.v.i v9, 1237; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma238; DOT-NEXT: vmv.v.i v10, 0239; DOT-NEXT: vqdot.vv v10, v8, v9240; DOT-NEXT: vmv.s.x v8, zero241; DOT-NEXT: vredsum.vs v8, v10, v8242; DOT-NEXT: vmv.x.s a0, v8243; DOT-NEXT: ret244entry:245 %a.ext = sext <16 x i8> %a to <16 x i32>246 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a.ext)247 ret i32 %res248}249 250define i32 @reduce_of_zext(<16 x i8> %a) {251; NODOT-LABEL: reduce_of_zext:252; NODOT: # %bb.0: # %entry253; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma254; NODOT-NEXT: vzext.vf4 v12, v8255; NODOT-NEXT: vmv.s.x v8, zero256; NODOT-NEXT: vredsum.vs v8, v12, v8257; NODOT-NEXT: vmv.x.s a0, v8258; NODOT-NEXT: ret259;260; DOT-LABEL: reduce_of_zext:261; DOT: # %bb.0: # %entry262; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma263; DOT-NEXT: vmv.v.i v9, 1264; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma265; DOT-NEXT: vmv.v.i v10, 0266; DOT-NEXT: vqdotu.vv v10, v8, v9267; DOT-NEXT: vmv.s.x v8, zero268; DOT-NEXT: vredsum.vs v8, v10, v8269; DOT-NEXT: vmv.x.s a0, v8270; DOT-NEXT: ret271entry:272 %a.ext = zext <16 x i8> %a to <16 x i32>273 %res = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a.ext)274 ret i32 %res275}276 277define i32 @vqdot_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {278; NODOT-LABEL: vqdot_vv_accum:279; NODOT: # %bb.0: # %entry280; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma281; NODOT-NEXT: vsext.vf2 v10, v8282; NODOT-NEXT: vsext.vf2 v16, v9283; NODOT-NEXT: vwmacc.vv v12, v10, v16284; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma285; NODOT-NEXT: vmv.s.x v8, zero286; NODOT-NEXT: vredsum.vs v8, v12, v8287; NODOT-NEXT: vmv.x.s a0, v8288; NODOT-NEXT: ret289;290; DOT-LABEL: vqdot_vv_accum:291; DOT: # %bb.0: # %entry292; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma293; DOT-NEXT: vmv1r.v v16, v12294; DOT-NEXT: vqdot.vv v16, v8, v9295; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma296; DOT-NEXT: vmv.v.v v12, v16297; DOT-NEXT: vmv.s.x v8, zero298; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma299; DOT-NEXT: vredsum.vs v8, v12, v8300; DOT-NEXT: vmv.x.s a0, v8301; DOT-NEXT: ret302entry:303 %a.sext = sext <16 x i8> %a to <16 x i32>304 %b.sext = sext <16 x i8> %b to <16 x i32>305 %mul = mul <16 x i32> %a.sext, %b.sext306 %add = add <16 x i32> %mul, %x307 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)308 ret i32 %sum309}310 311define i32 @vqdotu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {312; NODOT-LABEL: vqdotu_vv_accum:313; NODOT: # %bb.0: # %entry314; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma315; NODOT-NEXT: vwmulu.vv v10, v8, v9316; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma317; NODOT-NEXT: vwaddu.wv v12, v12, v10318; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma319; NODOT-NEXT: vmv.s.x v8, zero320; NODOT-NEXT: vredsum.vs v8, v12, v8321; NODOT-NEXT: vmv.x.s a0, v8322; NODOT-NEXT: ret323;324; DOT-LABEL: vqdotu_vv_accum:325; DOT: # %bb.0: # %entry326; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma327; DOT-NEXT: vmv1r.v v16, v12328; DOT-NEXT: vqdotu.vv v16, v8, v9329; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma330; DOT-NEXT: vmv.v.v v12, v16331; DOT-NEXT: vmv.s.x v8, zero332; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma333; DOT-NEXT: vredsum.vs v8, v12, v8334; DOT-NEXT: vmv.x.s a0, v8335; DOT-NEXT: ret336entry:337 %a.zext = zext <16 x i8> %a to <16 x i32>338 %b.zext = zext <16 x i8> %b to <16 x i32>339 %mul = mul <16 x i32> %a.zext, %b.zext340 %add = add <16 x i32> %mul, %x341 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)342 ret i32 %sum343}344 345define i32 @vqdotsu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {346; NODOT-LABEL: vqdotsu_vv_accum:347; NODOT: # %bb.0: # %entry348; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma349; NODOT-NEXT: vsext.vf2 v10, v8350; NODOT-NEXT: vzext.vf2 v16, v9351; NODOT-NEXT: vwmaccsu.vv v12, v10, v16352; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma353; NODOT-NEXT: vmv.s.x v8, zero354; NODOT-NEXT: vredsum.vs v8, v12, v8355; NODOT-NEXT: vmv.x.s a0, v8356; NODOT-NEXT: ret357;358; DOT-LABEL: vqdotsu_vv_accum:359; DOT: # %bb.0: # %entry360; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma361; DOT-NEXT: vmv1r.v v16, v12362; DOT-NEXT: vqdotsu.vv v16, v8, v9363; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma364; DOT-NEXT: vmv.v.v v12, v16365; DOT-NEXT: vmv.s.x v8, zero366; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma367; DOT-NEXT: vredsum.vs v8, v12, v8368; DOT-NEXT: vmv.x.s a0, v8369; DOT-NEXT: ret370entry:371 %a.sext = sext <16 x i8> %a to <16 x i32>372 %b.zext = zext <16 x i8> %b to <16 x i32>373 %mul = mul <16 x i32> %a.sext, %b.zext374 %add = add <16 x i32> %mul, %x375 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)376 ret i32 %sum377}378 379define i32 @vqdot_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {380; NODOT-LABEL: vqdot_vv_scalar_add:381; NODOT: # %bb.0: # %entry382; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma383; NODOT-NEXT: vsext.vf2 v12, v8384; NODOT-NEXT: vsext.vf2 v14, v9385; NODOT-NEXT: vwmul.vv v8, v12, v14386; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma387; NODOT-NEXT: vmv.s.x v12, a0388; NODOT-NEXT: vredsum.vs v8, v8, v12389; NODOT-NEXT: vmv.x.s a0, v8390; NODOT-NEXT: ret391;392; DOT-LABEL: vqdot_vv_scalar_add:393; DOT: # %bb.0: # %entry394; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma395; DOT-NEXT: vmv.v.i v10, 0396; DOT-NEXT: vqdot.vv v10, v8, v9397; DOT-NEXT: vmv.s.x v8, a0398; DOT-NEXT: vredsum.vs v8, v10, v8399; DOT-NEXT: vmv.x.s a0, v8400; DOT-NEXT: ret401entry:402 %a.sext = sext <16 x i8> %a to <16 x i32>403 %b.sext = sext <16 x i8> %b to <16 x i32>404 %mul = mul <16 x i32> %a.sext, %b.sext405 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)406 %add = add i32 %sum, %x407 ret i32 %add408}409 410define i32 @vqdotu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {411; NODOT-LABEL: vqdotu_vv_scalar_add:412; NODOT: # %bb.0: # %entry413; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma414; NODOT-NEXT: vwmulu.vv v10, v8, v9415; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma416; NODOT-NEXT: vmv.s.x v8, a0417; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma418; NODOT-NEXT: vwredsumu.vs v8, v10, v8419; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma420; NODOT-NEXT: vmv.x.s a0, v8421; NODOT-NEXT: ret422;423; DOT-LABEL: vqdotu_vv_scalar_add:424; DOT: # %bb.0: # %entry425; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma426; DOT-NEXT: vmv.v.i v10, 0427; DOT-NEXT: vqdotu.vv v10, v8, v9428; DOT-NEXT: vmv.s.x v8, a0429; DOT-NEXT: vredsum.vs v8, v10, v8430; DOT-NEXT: vmv.x.s a0, v8431; DOT-NEXT: ret432entry:433 %a.zext = zext <16 x i8> %a to <16 x i32>434 %b.zext = zext <16 x i8> %b to <16 x i32>435 %mul = mul <16 x i32> %a.zext, %b.zext436 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)437 %add = add i32 %sum, %x438 ret i32 %add439}440 441define i32 @vqdotsu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {442; NODOT-LABEL: vqdotsu_vv_scalar_add:443; NODOT: # %bb.0: # %entry444; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma445; NODOT-NEXT: vsext.vf2 v12, v8446; NODOT-NEXT: vzext.vf2 v14, v9447; NODOT-NEXT: vwmulsu.vv v8, v12, v14448; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma449; NODOT-NEXT: vmv.s.x v12, a0450; NODOT-NEXT: vredsum.vs v8, v8, v12451; NODOT-NEXT: vmv.x.s a0, v8452; NODOT-NEXT: ret453;454; DOT-LABEL: vqdotsu_vv_scalar_add:455; DOT: # %bb.0: # %entry456; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma457; DOT-NEXT: vmv.v.i v10, 0458; DOT-NEXT: vqdotsu.vv v10, v8, v9459; DOT-NEXT: vmv.s.x v8, a0460; DOT-NEXT: vredsum.vs v8, v10, v8461; DOT-NEXT: vmv.x.s a0, v8462; DOT-NEXT: ret463entry:464 %a.sext = sext <16 x i8> %a to <16 x i32>465 %b.zext = zext <16 x i8> %b to <16 x i32>466 %mul = mul <16 x i32> %a.sext, %b.zext467 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %mul)468 %add = add i32 %sum, %x469 ret i32 %add470}471 472define i32 @vqdot_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {473; NODOT-LABEL: vqdot_vv_split:474; NODOT: # %bb.0: # %entry475; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma476; NODOT-NEXT: vsext.vf2 v12, v8477; NODOT-NEXT: vsext.vf2 v14, v9478; NODOT-NEXT: vsext.vf2 v16, v10479; NODOT-NEXT: vsext.vf2 v18, v11480; NODOT-NEXT: vwmul.vv v8, v12, v14481; NODOT-NEXT: vwmacc.vv v8, v16, v18482; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma483; NODOT-NEXT: vmv.s.x v12, zero484; NODOT-NEXT: vredsum.vs v8, v8, v12485; NODOT-NEXT: vmv.x.s a0, v8486; NODOT-NEXT: ret487;488; DOT-LABEL: vqdot_vv_split:489; DOT: # %bb.0: # %entry490; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma491; DOT-NEXT: vmv.v.i v12, 0492; DOT-NEXT: vqdot.vv v12, v8, v9493; DOT-NEXT: vqdot.vv v12, v10, v11494; DOT-NEXT: vmv.s.x v8, zero495; DOT-NEXT: vredsum.vs v8, v12, v8496; DOT-NEXT: vmv.x.s a0, v8497; DOT-NEXT: ret498entry:499 %a.sext = sext <16 x i8> %a to <16 x i32>500 %b.sext = sext <16 x i8> %b to <16 x i32>501 %mul = mul <16 x i32> %a.sext, %b.sext502 %c.sext = sext <16 x i8> %c to <16 x i32>503 %d.sext = sext <16 x i8> %d to <16 x i32>504 %mul2 = mul <16 x i32> %c.sext, %d.sext505 %add = add <16 x i32> %mul, %mul2506 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)507 ret i32 %sum508}509 510define <1 x i32> @vqdot_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {511; NODOT-LABEL: vqdot_vv_partial_reduce_v1i32_v4i8:512; NODOT: # %bb.0: # %entry513; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma514; NODOT-NEXT: vsext.vf2 v10, v8515; NODOT-NEXT: vsext.vf2 v8, v9516; NODOT-NEXT: vwmul.vv v9, v10, v8517; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma518; NODOT-NEXT: vslidedown.vi v8, v9, 3519; NODOT-NEXT: vslidedown.vi v10, v9, 2520; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma521; NODOT-NEXT: vadd.vv v8, v8, v9522; NODOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma523; NODOT-NEXT: vslidedown.vi v9, v9, 1524; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma525; NODOT-NEXT: vadd.vv v9, v9, v10526; NODOT-NEXT: vadd.vv v8, v9, v8527; NODOT-NEXT: ret528;529; DOT-LABEL: vqdot_vv_partial_reduce_v1i32_v4i8:530; DOT: # %bb.0: # %entry531; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma532; DOT-NEXT: vmv.s.x v10, zero533; DOT-NEXT: vqdot.vv v10, v8, v9534; DOT-NEXT: vmv1r.v v8, v10535; DOT-NEXT: ret536entry:537 %a.sext = sext <4 x i8> %a to <4 x i32>538 %b.sext = sext <4 x i8> %b to <4 x i32>539 %mul = mul <4 x i32> %a.sext, %b.sext540 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)541 ret <1 x i32> %res542}543 544define <1 x i32> @vqdotu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {545; NODOT-LABEL: vqdotu_vv_partial_reduce_v1i32_v4i8:546; NODOT: # %bb.0: # %entry547; NODOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma548; NODOT-NEXT: vwmulu.vv v10, v8, v9549; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma550; NODOT-NEXT: vzext.vf2 v8, v10551; NODOT-NEXT: vslidedown.vi v9, v8, 3552; NODOT-NEXT: vslidedown.vi v10, v8, 2553; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma554; NODOT-NEXT: vadd.vv v9, v9, v8555; NODOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma556; NODOT-NEXT: vslidedown.vi v8, v8, 1557; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma558; NODOT-NEXT: vadd.vv v8, v8, v10559; NODOT-NEXT: vadd.vv v8, v8, v9560; NODOT-NEXT: ret561;562; DOT-LABEL: vqdotu_vv_partial_reduce_v1i32_v4i8:563; DOT: # %bb.0: # %entry564; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma565; DOT-NEXT: vmv.s.x v10, zero566; DOT-NEXT: vqdotu.vv v10, v8, v9567; DOT-NEXT: vmv1r.v v8, v10568; DOT-NEXT: ret569entry:570 %a.sext = zext <4 x i8> %a to <4 x i32>571 %b.sext = zext <4 x i8> %b to <4 x i32>572 %mul = mul <4 x i32> %a.sext, %b.sext573 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)574 ret <1 x i32> %res575}576 577define <1 x i32> @vqdotu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {578; NODOT-LABEL: vqdotu_vx_partial_reduce:579; NODOT: # %bb.0: # %entry580; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma581; NODOT-NEXT: vzext.vf4 v9, v8582; NODOT-NEXT: vsll.vi v8, v9, 7583; NODOT-NEXT: vslidedown.vi v9, v8, 3584; NODOT-NEXT: vslidedown.vi v10, v8, 2585; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma586; NODOT-NEXT: vadd.vv v9, v9, v8587; NODOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma588; NODOT-NEXT: vslidedown.vi v8, v8, 1589; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma590; NODOT-NEXT: vadd.vv v8, v8, v10591; NODOT-NEXT: vadd.vv v8, v8, v9592; NODOT-NEXT: ret593;594; DOT-LABEL: vqdotu_vx_partial_reduce:595; DOT: # %bb.0: # %entry596; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma597; DOT-NEXT: vmv.s.x v9, zero598; DOT-NEXT: li a0, 128599; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma600; DOT-NEXT: vmv.v.x v10, a0601; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma602; DOT-NEXT: vqdotu.vv v9, v8, v10603; DOT-NEXT: vmv1r.v v8, v9604; DOT-NEXT: ret605entry:606 %a.ext = zext <4 x i8> %a to <4 x i32>607 %mul = mul <4 x i32> %a.ext, splat (i32 128)608 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)609 ret <1 x i32> %res610}611 612define <1 x i32> @vqdot_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {613; NODOT-LABEL: vqdot_vx_partial_reduce:614; NODOT: # %bb.0: # %entry615; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma616; NODOT-NEXT: vsext.vf4 v9, v8617; NODOT-NEXT: vsll.vi v8, v9, 7618; NODOT-NEXT: vrsub.vi v8, v8, 0619; NODOT-NEXT: vslidedown.vi v9, v8, 3620; NODOT-NEXT: vslidedown.vi v10, v8, 2621; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma622; NODOT-NEXT: vadd.vv v9, v9, v8623; NODOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma624; NODOT-NEXT: vslidedown.vi v8, v8, 1625; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma626; NODOT-NEXT: vadd.vv v8, v8, v10627; NODOT-NEXT: vadd.vv v8, v8, v9628; NODOT-NEXT: ret629;630; DOT-LABEL: vqdot_vx_partial_reduce:631; DOT: # %bb.0: # %entry632; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma633; DOT-NEXT: vmv.s.x v9, zero634; DOT-NEXT: li a0, 128635; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma636; DOT-NEXT: vmv.v.x v10, a0637; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma638; DOT-NEXT: vqdot.vv v9, v8, v10639; DOT-NEXT: vmv1r.v v8, v9640; DOT-NEXT: ret641entry:642 %a.ext = sext <4 x i8> %a to <4 x i32>643 %mul = mul <4 x i32> %a.ext, splat (i32 -128)644 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)645 ret <1 x i32> %res646}647 648define <1 x i32> @vqdotsu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {649; NODOT-LABEL: vqdotsu_vv_partial_reduce_v1i32_v4i8:650; NODOT: # %bb.0: # %entry651; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma652; NODOT-NEXT: vsext.vf2 v10, v8653; NODOT-NEXT: vzext.vf2 v8, v9654; NODOT-NEXT: vwmulsu.vv v9, v10, v8655; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma656; NODOT-NEXT: vslidedown.vi v8, v9, 3657; NODOT-NEXT: vslidedown.vi v10, v9, 2658; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma659; NODOT-NEXT: vadd.vv v8, v8, v9660; NODOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma661; NODOT-NEXT: vslidedown.vi v9, v9, 1662; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma663; NODOT-NEXT: vadd.vv v9, v9, v10664; NODOT-NEXT: vadd.vv v8, v9, v8665; NODOT-NEXT: ret666;667; DOT-LABEL: vqdotsu_vv_partial_reduce_v1i32_v4i8:668; DOT: # %bb.0: # %entry669; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma670; DOT-NEXT: vmv.s.x v10, zero671; DOT-NEXT: vqdotsu.vv v10, v8, v9672; DOT-NEXT: vmv1r.v v8, v10673; DOT-NEXT: ret674entry:675 %a.sext = sext <4 x i8> %a to <4 x i32>676 %b.sext = zext <4 x i8> %b to <4 x i32>677 %mul = mul <4 x i32> %a.sext, %b.sext678 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)679 ret <1 x i32> %res680}681 682define <1 x i32> @vqdotsu_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {683; NODOT-LABEL: vqdotsu_vv_partial_reduce_swapped:684; NODOT: # %bb.0: # %entry685; NODOT-NEXT: vsetivli zero, 4, e16, mf2, ta, ma686; NODOT-NEXT: vsext.vf2 v10, v8687; NODOT-NEXT: vzext.vf2 v8, v9688; NODOT-NEXT: vwmulsu.vv v9, v10, v8689; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma690; NODOT-NEXT: vslidedown.vi v8, v9, 3691; NODOT-NEXT: vslidedown.vi v10, v9, 2692; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma693; NODOT-NEXT: vadd.vv v8, v8, v9694; NODOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma695; NODOT-NEXT: vslidedown.vi v9, v9, 1696; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma697; NODOT-NEXT: vadd.vv v9, v9, v10698; NODOT-NEXT: vadd.vv v8, v9, v8699; NODOT-NEXT: ret700;701; DOT-LABEL: vqdotsu_vv_partial_reduce_swapped:702; DOT: # %bb.0: # %entry703; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma704; DOT-NEXT: vmv.s.x v10, zero705; DOT-NEXT: vqdotsu.vv v10, v8, v9706; DOT-NEXT: vmv1r.v v8, v10707; DOT-NEXT: ret708entry:709 %a.ext = sext <4 x i8> %a to <4 x i32>710 %b.ext = zext <4 x i8> %b to <4 x i32>711 %mul = mul <4 x i32> %b.ext, %a.ext712 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)713 ret <1 x i32> %res714}715 716define <1 x i32> @vqdotsu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {717; CHECK-LABEL: vqdotsu_vx_partial_reduce:718; CHECK: # %bb.0: # %entry719; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma720; CHECK-NEXT: vsext.vf4 v9, v8721; CHECK-NEXT: vsll.vi v8, v9, 7722; CHECK-NEXT: vslidedown.vi v9, v8, 3723; CHECK-NEXT: vslidedown.vi v10, v8, 2724; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma725; CHECK-NEXT: vadd.vv v9, v9, v8726; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma727; CHECK-NEXT: vslidedown.vi v8, v8, 1728; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma729; CHECK-NEXT: vadd.vv v8, v8, v10730; CHECK-NEXT: vadd.vv v8, v8, v9731; CHECK-NEXT: ret732entry:733 %a.ext = sext <4 x i8> %a to <4 x i32>734 %mul = mul <4 x i32> %a.ext, splat (i32 128)735 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <4 x i32> %mul)736 ret <1 x i32> %res737}738 739 740define <2 x i32> @vqdot_vv_partial_reduce_v2i32_v8i8(<8 x i8> %a, <8 x i8> %b) {741; NODOT-LABEL: vqdot_vv_partial_reduce_v2i32_v8i8:742; NODOT: # %bb.0: # %entry743; NODOT-NEXT: vsetivli zero, 8, e16, m1, ta, ma744; NODOT-NEXT: vsext.vf2 v10, v8745; NODOT-NEXT: vsext.vf2 v11, v9746; NODOT-NEXT: vwmul.vv v8, v10, v11747; NODOT-NEXT: vsetivli zero, 2, e32, m2, ta, ma748; NODOT-NEXT: vslidedown.vi v10, v8, 6749; NODOT-NEXT: vsetivli zero, 2, e32, mf2, ta, ma750; NODOT-NEXT: vadd.vv v12, v10, v8751; NODOT-NEXT: vsetivli zero, 2, e32, m2, ta, ma752; NODOT-NEXT: vslidedown.vi v10, v8, 4753; NODOT-NEXT: vsetivli zero, 2, e32, m1, ta, ma754; NODOT-NEXT: vslidedown.vi v8, v8, 2755; NODOT-NEXT: vsetivli zero, 2, e32, mf2, ta, ma756; NODOT-NEXT: vadd.vv v8, v8, v10757; NODOT-NEXT: vadd.vv v8, v8, v12758; NODOT-NEXT: ret759;760; DOT-LABEL: vqdot_vv_partial_reduce_v2i32_v8i8:761; DOT: # %bb.0: # %entry762; DOT-NEXT: vsetivli zero, 2, e32, mf2, ta, ma763; DOT-NEXT: vmv.v.i v10, 0764; DOT-NEXT: vqdot.vv v10, v8, v9765; DOT-NEXT: vmv1r.v v8, v10766; DOT-NEXT: ret767entry:768 %a.sext = sext <8 x i8> %a to <8 x i32>769 %b.sext = sext <8 x i8> %b to <8 x i32>770 %mul = mul <8 x i32> %a.sext, %b.sext771 %res = call <2 x i32> @llvm.vector.partial.reduce.add(<2 x i32> zeroinitializer, <8 x i32> %mul)772 ret <2 x i32> %res773}774 775define <2 x i32> @vqdot_vv_partial_reduce_v2i32_v64i8(<64 x i8> %a, <64 x i8> %b) {776; CHECK-LABEL: vqdot_vv_partial_reduce_v2i32_v64i8:777; CHECK: # %bb.0: # %entry778; CHECK-NEXT: addi sp, sp, -16779; CHECK-NEXT: .cfi_def_cfa_offset 16780; CHECK-NEXT: csrr a0, vlenb781; CHECK-NEXT: slli a1, a0, 2782; CHECK-NEXT: add a0, a1, a0783; CHECK-NEXT: sub sp, sp, a0784; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x05, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 5 * vlenb785; CHECK-NEXT: li a0, 32786; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma787; CHECK-NEXT: vsext.vf2 v24, v8788; CHECK-NEXT: vsext.vf2 v28, v12789; CHECK-NEXT: vwmul.vv v16, v24, v28790; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma791; CHECK-NEXT: vslidedown.vi v24, v16, 28792; CHECK-NEXT: vslidedown.vi v0, v16, 26793; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma794; CHECK-NEXT: vadd.vv v24, v0, v24795; CHECK-NEXT: csrr a1, vlenb796; CHECK-NEXT: slli a1, a1, 2797; CHECK-NEXT: add a1, sp, a1798; CHECK-NEXT: addi a1, a1, 16799; CHECK-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill800; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma801; CHECK-NEXT: vslidedown.vi v0, v16, 24802; CHECK-NEXT: vslidedown.vi v24, v16, 22803; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma804; CHECK-NEXT: vadd.vv v24, v24, v0805; CHECK-NEXT: csrr a1, vlenb806; CHECK-NEXT: slli a2, a1, 1807; CHECK-NEXT: add a1, a2, a1808; CHECK-NEXT: add a1, sp, a1809; CHECK-NEXT: addi a1, a1, 16810; CHECK-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill811; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma812; CHECK-NEXT: vslidedown.vi v0, v16, 20813; CHECK-NEXT: vslidedown.vi v24, v16, 18814; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma815; CHECK-NEXT: vadd.vv v24, v24, v0816; CHECK-NEXT: csrr a1, vlenb817; CHECK-NEXT: slli a1, a1, 1818; CHECK-NEXT: add a1, sp, a1819; CHECK-NEXT: addi a1, a1, 16820; CHECK-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill821; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma822; CHECK-NEXT: vslidedown.vx v8, v8, a0823; CHECK-NEXT: vslidedown.vx v12, v12, a0824; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma825; CHECK-NEXT: vsext.vf2 v24, v8826; CHECK-NEXT: vsext.vf2 v28, v12827; CHECK-NEXT: vwmul.vv v8, v24, v28828; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma829; CHECK-NEXT: vslidedown.vi v0, v8, 28830; CHECK-NEXT: vslidedown.vi v24, v8, 26831; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma832; CHECK-NEXT: vadd.vv v24, v24, v0833; CHECK-NEXT: csrr a0, vlenb834; CHECK-NEXT: add a0, sp, a0835; CHECK-NEXT: addi a0, a0, 16836; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill837; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma838; CHECK-NEXT: vslidedown.vi v24, v8, 24839; CHECK-NEXT: vslidedown.vi v0, v8, 22840; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma841; CHECK-NEXT: vadd.vv v24, v0, v24842; CHECK-NEXT: addi a0, sp, 16843; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill844; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma845; CHECK-NEXT: vslidedown.vi v24, v8, 20846; CHECK-NEXT: vslidedown.vi v0, v8, 18847; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma848; CHECK-NEXT: vadd.vv v7, v0, v24849; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma850; CHECK-NEXT: vslidedown.vi v24, v16, 16851; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, ma852; CHECK-NEXT: vslidedown.vi v28, v16, 14853; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma854; CHECK-NEXT: vadd.vv v6, v28, v24855; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma856; CHECK-NEXT: vslidedown.vi v24, v8, 16857; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, ma858; CHECK-NEXT: vslidedown.vi v28, v8, 14859; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma860; CHECK-NEXT: vadd.vv v5, v28, v24861; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma862; CHECK-NEXT: vslidedown.vi v24, v16, 30863; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma864; CHECK-NEXT: vadd.vv v4, v24, v16865; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, ma866; CHECK-NEXT: vslidedown.vi v20, v16, 12867; CHECK-NEXT: vslidedown.vi v24, v16, 10868; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma869; CHECK-NEXT: vadd.vv v3, v24, v20870; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, ma871; CHECK-NEXT: vslidedown.vi v24, v8, 30872; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma873; CHECK-NEXT: vadd.vv v24, v24, v8874; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, ma875; CHECK-NEXT: vslidedown.vi v12, v8, 12876; CHECK-NEXT: vslidedown.vi v20, v8, 10877; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma878; CHECK-NEXT: vadd.vv v25, v20, v12879; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma880; CHECK-NEXT: vslidedown.vi v20, v16, 6881; CHECK-NEXT: vslidedown.vi v22, v16, 4882; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma883; CHECK-NEXT: vslidedown.vi v21, v16, 2884; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, ma885; CHECK-NEXT: vslidedown.vi v12, v16, 8886; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma887; CHECK-NEXT: vadd.vv v16, v20, v12888; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma889; CHECK-NEXT: vslidedown.vi v12, v8, 6890; CHECK-NEXT: vslidedown.vi v14, v8, 4891; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma892; CHECK-NEXT: vslidedown.vi v13, v8, 2893; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, ma894; CHECK-NEXT: vslidedown.vi v8, v8, 8895; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma896; CHECK-NEXT: vadd.vv v8, v12, v8897; CHECK-NEXT: vadd.vv v9, v21, v22898; CHECK-NEXT: vadd.vv v10, v13, v14899; CHECK-NEXT: csrr a0, vlenb900; CHECK-NEXT: slli a0, a0, 2901; CHECK-NEXT: add a0, sp, a0902; CHECK-NEXT: addi a0, a0, 16903; CHECK-NEXT: vl1r.v v11, (a0) # vscale x 8-byte Folded Reload904; CHECK-NEXT: vadd.vv v11, v11, v4905; CHECK-NEXT: csrr a0, vlenb906; CHECK-NEXT: slli a1, a0, 1907; CHECK-NEXT: add a0, a1, a0908; CHECK-NEXT: add a0, sp, a0909; CHECK-NEXT: addi a0, a0, 16910; CHECK-NEXT: vl1r.v v12, (a0) # vscale x 8-byte Folded Reload911; CHECK-NEXT: csrr a0, vlenb912; CHECK-NEXT: slli a0, a0, 1913; CHECK-NEXT: add a0, sp, a0914; CHECK-NEXT: addi a0, a0, 16915; CHECK-NEXT: vl1r.v v13, (a0) # vscale x 8-byte Folded Reload916; CHECK-NEXT: vadd.vv v12, v13, v12917; CHECK-NEXT: vadd.vv v13, v3, v6918; CHECK-NEXT: vadd.vv v9, v9, v16919; CHECK-NEXT: vadd.vv v11, v12, v11920; CHECK-NEXT: vadd.vv v9, v9, v13921; CHECK-NEXT: addi a0, sp, 16922; CHECK-NEXT: vl1r.v v12, (a0) # vscale x 8-byte Folded Reload923; CHECK-NEXT: vadd.vv v12, v7, v12924; CHECK-NEXT: vadd.vv v13, v25, v5925; CHECK-NEXT: vadd.vv v8, v10, v8926; CHECK-NEXT: vadd.vv v9, v9, v11927; CHECK-NEXT: vadd.vv v9, v24, v9928; CHECK-NEXT: csrr a0, vlenb929; CHECK-NEXT: add a0, sp, a0930; CHECK-NEXT: addi a0, a0, 16931; CHECK-NEXT: vl1r.v v10, (a0) # vscale x 8-byte Folded Reload932; CHECK-NEXT: vadd.vv v9, v10, v9933; CHECK-NEXT: vadd.vv v9, v12, v9934; CHECK-NEXT: vadd.vv v8, v8, v13935; CHECK-NEXT: vadd.vv v8, v8, v9936; CHECK-NEXT: csrr a0, vlenb937; CHECK-NEXT: slli a1, a0, 2938; CHECK-NEXT: add a0, a1, a0939; CHECK-NEXT: add sp, sp, a0940; CHECK-NEXT: .cfi_def_cfa sp, 16941; CHECK-NEXT: addi sp, sp, 16942; CHECK-NEXT: .cfi_def_cfa_offset 0943; CHECK-NEXT: ret944entry:945 %a.sext = sext <64 x i8> %a to <64 x i32>946 %b.sext = sext <64 x i8> %b to <64 x i32>947 %mul = mul <64 x i32> %a.sext, %b.sext948 %res = call <2 x i32> @llvm.vector.partial.reduce.add(<2 x i32> zeroinitializer, <64 x i32> %mul)949 ret <2 x i32> %res950}951 952define <4 x i32> @vqdot_vv_partial_reduce_v4i32_v16i8(<16 x i8> %a, <16 x i8> %b) {953; NODOT-LABEL: vqdot_vv_partial_reduce_v4i32_v16i8:954; NODOT: # %bb.0: # %entry955; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma956; NODOT-NEXT: vsext.vf2 v12, v8957; NODOT-NEXT: vsext.vf2 v14, v9958; NODOT-NEXT: vwmul.vv v8, v12, v14959; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma960; NODOT-NEXT: vslidedown.vi v12, v8, 12961; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma962; NODOT-NEXT: vadd.vv v16, v12, v8963; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma964; NODOT-NEXT: vslidedown.vi v12, v8, 8965; NODOT-NEXT: vsetivli zero, 4, e32, m2, ta, ma966; NODOT-NEXT: vslidedown.vi v8, v8, 4967; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma968; NODOT-NEXT: vadd.vv v8, v8, v12969; NODOT-NEXT: vadd.vv v8, v8, v16970; NODOT-NEXT: ret971;972; DOT-LABEL: vqdot_vv_partial_reduce_v4i32_v16i8:973; DOT: # %bb.0: # %entry974; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma975; DOT-NEXT: vmv.v.i v10, 0976; DOT-NEXT: vqdot.vv v10, v8, v9977; DOT-NEXT: vmv.v.v v8, v10978; DOT-NEXT: ret979entry:980 %a.sext = sext <16 x i8> %a to <16 x i32>981 %b.sext = sext <16 x i8> %b to <16 x i32>982 %mul = mul <16 x i32> %a.sext, %b.sext983 %res = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> zeroinitializer, <16 x i32> %mul)984 ret <4 x i32> %res985}986 987define <16 x i32> @vqdot_vv_partial_reduce_v16i32_v64i8(<64 x i8> %a, <64 x i8> %b) {988; NODOT-LABEL: vqdot_vv_partial_reduce_v16i32_v64i8:989; NODOT: # %bb.0: # %entry990; NODOT-NEXT: li a0, 32991; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma992; NODOT-NEXT: vsext.vf2 v16, v8993; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma994; NODOT-NEXT: vslidedown.vx v8, v8, a0995; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma996; NODOT-NEXT: vsext.vf2 v20, v12997; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma998; NODOT-NEXT: vslidedown.vx v12, v12, a0999; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1000; NODOT-NEXT: vsext.vf2 v24, v81001; NODOT-NEXT: vsext.vf2 v28, v121002; NODOT-NEXT: vwmul.vv v8, v16, v201003; NODOT-NEXT: vwmul.vv v16, v24, v281004; NODOT-NEXT: vsetivli zero, 16, e32, m8, ta, ma1005; NODOT-NEXT: vslidedown.vi v24, v8, 161006; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1007; NODOT-NEXT: vadd.vv v8, v24, v81008; NODOT-NEXT: vadd.vv v24, v8, v161009; NODOT-NEXT: vsetivli zero, 16, e32, m8, ta, ma1010; NODOT-NEXT: vslidedown.vi v8, v16, 161011; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1012; NODOT-NEXT: vadd.vv v8, v8, v241013; NODOT-NEXT: ret1014;1015; DOT-LABEL: vqdot_vv_partial_reduce_v16i32_v64i8:1016; DOT: # %bb.0: # %entry1017; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1018; DOT-NEXT: vmv.v.i v16, 01019; DOT-NEXT: vqdot.vv v16, v8, v121020; DOT-NEXT: vmv.v.v v8, v161021; DOT-NEXT: ret1022entry:1023 %a.sext = sext <64 x i8> %a to <64 x i32>1024 %b.sext = sext <64 x i8> %b to <64 x i32>1025 %mul = mul <64 x i32> %a.sext, %b.sext1026 %res = call <16 x i32> @llvm.vector.partial.reduce.add(<16 x i32> zeroinitializer, <64 x i32> %mul)1027 ret <16 x i32> %res1028}1029 1030define <4 x i32> @vqdot_vv_partial_reduce_m1_accum(<16 x i8> %a, <16 x i8> %b, <4 x i32> %accum) {1031; NODOT-LABEL: vqdot_vv_partial_reduce_m1_accum:1032; NODOT: # %bb.0: # %entry1033; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma1034; NODOT-NEXT: vsext.vf2 v16, v81035; NODOT-NEXT: vsext.vf2 v18, v91036; NODOT-NEXT: vwmul.vv v12, v16, v181037; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1038; NODOT-NEXT: vadd.vv v16, v10, v121039; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1040; NODOT-NEXT: vslidedown.vi v8, v12, 121041; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1042; NODOT-NEXT: vadd.vv v16, v8, v161043; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1044; NODOT-NEXT: vslidedown.vi v8, v12, 81045; NODOT-NEXT: vsetivli zero, 4, e32, m2, ta, ma1046; NODOT-NEXT: vslidedown.vi v10, v12, 41047; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1048; NODOT-NEXT: vadd.vv v8, v10, v81049; NODOT-NEXT: vadd.vv v8, v8, v161050; NODOT-NEXT: ret1051;1052; DOT-LABEL: vqdot_vv_partial_reduce_m1_accum:1053; DOT: # %bb.0: # %entry1054; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1055; DOT-NEXT: vqdot.vv v10, v8, v91056; DOT-NEXT: vmv.v.v v8, v101057; DOT-NEXT: ret1058entry:1059 %a.sext = sext <16 x i8> %a to <16 x i32>1060 %b.sext = sext <16 x i8> %b to <16 x i32>1061 %mul = mul <16 x i32> %a.sext, %b.sext1062 %res = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %accum, <16 x i32> %mul)1063 ret <4 x i32> %res1064}1065 1066define <16 x i32> @vqdot_vv_partial_reduce3(<16 x i8> %a, <16 x i8> %b) {1067; CHECK-LABEL: vqdot_vv_partial_reduce3:1068; CHECK: # %bb.0: # %entry1069; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1070; CHECK-NEXT: vsext.vf2 v12, v81071; CHECK-NEXT: vsext.vf2 v14, v91072; CHECK-NEXT: vwmul.vv v8, v12, v141073; CHECK-NEXT: ret1074entry:1075 %a.sext = sext <16 x i8> %a to <16 x i32>1076 %b.sext = sext <16 x i8> %b to <16 x i32>1077 %mul = mul <16 x i32> %a.sext, %b.sext1078 %res = call <16 x i32> @llvm.vector.partial.reduce.add.nvx8i32.nvx16i32.nvx16i32(<16 x i32> %mul, <16 x i32> zeroinitializer)1079 ret <16 x i32> %res1080}1081 1082; Test legalization - type split1083define <64 x i32> @vqdotsu_vv_partial_v64i32_v256i8(<256 x i8> %a, <256 x i8> %b) {1084; NODOT-LABEL: vqdotsu_vv_partial_v64i32_v256i8:1085; NODOT: # %bb.0: # %entry1086; NODOT-NEXT: addi sp, sp, -161087; NODOT-NEXT: .cfi_def_cfa_offset 161088; NODOT-NEXT: csrr a1, vlenb1089; NODOT-NEXT: slli a1, a1, 31090; NODOT-NEXT: mv a2, a11091; NODOT-NEXT: slli a1, a1, 21092; NODOT-NEXT: add a1, a1, a21093; NODOT-NEXT: sub sp, sp, a11094; NODOT-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb1095; NODOT-NEXT: csrr a1, vlenb1096; NODOT-NEXT: slli a1, a1, 41097; NODOT-NEXT: add a1, sp, a11098; NODOT-NEXT: addi a1, a1, 161099; NODOT-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1100; NODOT-NEXT: csrr a1, vlenb1101; NODOT-NEXT: slli a1, a1, 51102; NODOT-NEXT: add a1, sp, a11103; NODOT-NEXT: addi a1, a1, 161104; NODOT-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1105; NODOT-NEXT: addi a1, a0, 1281106; NODOT-NEXT: li a2, 1281107; NODOT-NEXT: vsetvli zero, a2, e8, m8, ta, ma1108; NODOT-NEXT: vle8.v v0, (a0)1109; NODOT-NEXT: csrr a0, vlenb1110; NODOT-NEXT: slli a0, a0, 31111; NODOT-NEXT: mv a3, a01112; NODOT-NEXT: slli a0, a0, 11113; NODOT-NEXT: add a0, a0, a31114; NODOT-NEXT: add a0, sp, a01115; NODOT-NEXT: addi a0, a0, 161116; NODOT-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill1117; NODOT-NEXT: li a0, 321118; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma1119; NODOT-NEXT: vslidedown.vx v24, v8, a01120; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1121; NODOT-NEXT: vsext.vf2 v8, v241122; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma1123; NODOT-NEXT: vslidedown.vx v12, v0, a01124; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1125; NODOT-NEXT: vzext.vf2 v4, v121126; NODOT-NEXT: vwmulsu.vv v24, v8, v41127; NODOT-NEXT: csrr a3, vlenb1128; NODOT-NEXT: slli a3, a3, 51129; NODOT-NEXT: add a3, sp, a31130; NODOT-NEXT: addi a3, a3, 161131; NODOT-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload1132; NODOT-NEXT: vsext.vf2 v4, v81133; NODOT-NEXT: csrr a3, vlenb1134; NODOT-NEXT: slli a3, a3, 31135; NODOT-NEXT: mv a4, a31136; NODOT-NEXT: slli a3, a3, 11137; NODOT-NEXT: add a3, a3, a41138; NODOT-NEXT: add a3, sp, a31139; NODOT-NEXT: addi a3, a3, 161140; NODOT-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload1141; NODOT-NEXT: vzext.vf2 v0, v81142; NODOT-NEXT: vsetvli zero, a2, e8, m8, ta, ma1143; NODOT-NEXT: vle8.v v8, (a1)1144; NODOT-NEXT: addi a1, sp, 161145; NODOT-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1146; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1147; NODOT-NEXT: vwmaccsu.vv v24, v4, v01148; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma1149; NODOT-NEXT: vslidedown.vx v4, v16, a01150; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1151; NODOT-NEXT: vsext.vf2 v12, v41152; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma1153; NODOT-NEXT: vslidedown.vx v4, v8, a01154; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1155; NODOT-NEXT: vzext.vf2 v16, v41156; NODOT-NEXT: vwmulsu.vv v0, v12, v161157; NODOT-NEXT: csrr a1, vlenb1158; NODOT-NEXT: slli a1, a1, 41159; NODOT-NEXT: add a1, sp, a11160; NODOT-NEXT: addi a1, a1, 161161; NODOT-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1162; NODOT-NEXT: vsext.vf2 v12, v161163; NODOT-NEXT: vzext.vf2 v20, v81164; NODOT-NEXT: vwmaccsu.vv v0, v12, v201165; NODOT-NEXT: li a1, 641166; NODOT-NEXT: csrr a2, vlenb1167; NODOT-NEXT: slli a2, a2, 51168; NODOT-NEXT: add a2, sp, a21169; NODOT-NEXT: addi a2, a2, 161170; NODOT-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1171; NODOT-NEXT: vsetvli zero, a1, e8, m8, ta, ma1172; NODOT-NEXT: vslidedown.vx v8, v16, a11173; NODOT-NEXT: csrr a2, vlenb1174; NODOT-NEXT: slli a2, a2, 51175; NODOT-NEXT: add a2, sp, a21176; NODOT-NEXT: addi a2, a2, 161177; NODOT-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1178; NODOT-NEXT: csrr a2, vlenb1179; NODOT-NEXT: slli a2, a2, 31180; NODOT-NEXT: mv a3, a21181; NODOT-NEXT: slli a2, a2, 11182; NODOT-NEXT: add a2, a2, a31183; NODOT-NEXT: add a2, sp, a21184; NODOT-NEXT: addi a2, a2, 161185; NODOT-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1186; NODOT-NEXT: vslidedown.vx v8, v16, a11187; NODOT-NEXT: csrr a2, vlenb1188; NODOT-NEXT: slli a2, a2, 31189; NODOT-NEXT: add a2, sp, a21190; NODOT-NEXT: addi a2, a2, 161191; NODOT-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1192; NODOT-NEXT: csrr a2, vlenb1193; NODOT-NEXT: slli a2, a2, 51194; NODOT-NEXT: add a2, sp, a21195; NODOT-NEXT: addi a2, a2, 161196; NODOT-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload1197; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1198; NODOT-NEXT: vsext.vf2 v16, v81199; NODOT-NEXT: csrr a2, vlenb1200; NODOT-NEXT: slli a2, a2, 31201; NODOT-NEXT: add a2, sp, a21202; NODOT-NEXT: addi a2, a2, 161203; NODOT-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload1204; NODOT-NEXT: vzext.vf2 v20, v81205; NODOT-NEXT: vwmaccsu.vv v24, v16, v201206; NODOT-NEXT: csrr a2, vlenb1207; NODOT-NEXT: slli a2, a2, 41208; NODOT-NEXT: add a2, sp, a21209; NODOT-NEXT: addi a2, a2, 161210; NODOT-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload1211; NODOT-NEXT: vsetvli zero, a1, e8, m8, ta, ma1212; NODOT-NEXT: vslidedown.vx v16, v16, a11213; NODOT-NEXT: addi a2, sp, 161214; NODOT-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload1215; NODOT-NEXT: vslidedown.vx v8, v8, a11216; NODOT-NEXT: csrr a1, vlenb1217; NODOT-NEXT: slli a1, a1, 31218; NODOT-NEXT: mv a2, a11219; NODOT-NEXT: slli a1, a1, 11220; NODOT-NEXT: add a1, a1, a21221; NODOT-NEXT: add a1, sp, a11222; NODOT-NEXT: addi a1, a1, 161223; NODOT-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1224; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1225; NODOT-NEXT: vsext.vf2 v8, v161226; NODOT-NEXT: csrr a1, vlenb1227; NODOT-NEXT: slli a1, a1, 41228; NODOT-NEXT: add a1, sp, a11229; NODOT-NEXT: addi a1, a1, 161230; NODOT-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill1231; NODOT-NEXT: csrr a1, vlenb1232; NODOT-NEXT: slli a1, a1, 31233; NODOT-NEXT: mv a2, a11234; NODOT-NEXT: slli a1, a1, 11235; NODOT-NEXT: add a1, a1, a21236; NODOT-NEXT: add a1, sp, a11237; NODOT-NEXT: addi a1, a1, 161238; NODOT-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1239; NODOT-NEXT: vzext.vf2 v20, v81240; NODOT-NEXT: csrr a1, vlenb1241; NODOT-NEXT: slli a1, a1, 41242; NODOT-NEXT: add a1, sp, a11243; NODOT-NEXT: addi a1, a1, 161244; NODOT-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1245; NODOT-NEXT: vwmaccsu.vv v0, v8, v201246; NODOT-NEXT: csrr a1, vlenb1247; NODOT-NEXT: slli a1, a1, 51248; NODOT-NEXT: add a1, sp, a11249; NODOT-NEXT: addi a1, a1, 161250; NODOT-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1251; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma1252; NODOT-NEXT: vslidedown.vx v20, v8, a01253; NODOT-NEXT: csrr a1, vlenb1254; NODOT-NEXT: slli a1, a1, 31255; NODOT-NEXT: add a1, sp, a11256; NODOT-NEXT: addi a1, a1, 161257; NODOT-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1258; NODOT-NEXT: vslidedown.vx v8, v8, a01259; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1260; NODOT-NEXT: vsext.vf2 v12, v201261; NODOT-NEXT: csrr a1, vlenb1262; NODOT-NEXT: slli a1, a1, 51263; NODOT-NEXT: add a1, sp, a11264; NODOT-NEXT: addi a1, a1, 161265; NODOT-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill1266; NODOT-NEXT: vzext.vf2 v12, v81267; NODOT-NEXT: csrr a1, vlenb1268; NODOT-NEXT: slli a1, a1, 51269; NODOT-NEXT: add a1, sp, a11270; NODOT-NEXT: addi a1, a1, 161271; NODOT-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload1272; NODOT-NEXT: vwmaccsu.vv v24, v8, v121273; NODOT-NEXT: vsetvli zero, a0, e8, m4, ta, ma1274; NODOT-NEXT: vslidedown.vx v12, v16, a01275; NODOT-NEXT: csrr a1, vlenb1276; NODOT-NEXT: slli a1, a1, 31277; NODOT-NEXT: mv a2, a11278; NODOT-NEXT: slli a1, a1, 11279; NODOT-NEXT: add a1, a1, a21280; NODOT-NEXT: add a1, sp, a11281; NODOT-NEXT: addi a1, a1, 161282; NODOT-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1283; NODOT-NEXT: vslidedown.vx v8, v16, a01284; NODOT-NEXT: vsetvli zero, a0, e16, m4, ta, ma1285; NODOT-NEXT: vsext.vf2 v16, v121286; NODOT-NEXT: vzext.vf2 v12, v81287; NODOT-NEXT: vwmaccsu.vv v0, v16, v121288; NODOT-NEXT: vmv8r.v v8, v241289; NODOT-NEXT: vmv8r.v v16, v01290; NODOT-NEXT: csrr a0, vlenb1291; NODOT-NEXT: slli a0, a0, 31292; NODOT-NEXT: mv a1, a01293; NODOT-NEXT: slli a0, a0, 21294; NODOT-NEXT: add a0, a0, a11295; NODOT-NEXT: add sp, sp, a01296; NODOT-NEXT: .cfi_def_cfa sp, 161297; NODOT-NEXT: addi sp, sp, 161298; NODOT-NEXT: .cfi_def_cfa_offset 01299; NODOT-NEXT: ret1300;1301; DOT-LABEL: vqdotsu_vv_partial_v64i32_v256i8:1302; DOT: # %bb.0: # %entry1303; DOT-NEXT: addi sp, sp, -161304; DOT-NEXT: .cfi_def_cfa_offset 161305; DOT-NEXT: csrr a1, vlenb1306; DOT-NEXT: slli a1, a1, 51307; DOT-NEXT: sub sp, sp, a11308; DOT-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb1309; DOT-NEXT: csrr a1, vlenb1310; DOT-NEXT: slli a1, a1, 31311; DOT-NEXT: mv a2, a11312; DOT-NEXT: slli a1, a1, 11313; DOT-NEXT: add a1, a1, a21314; DOT-NEXT: add a1, sp, a11315; DOT-NEXT: addi a1, a1, 161316; DOT-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1317; DOT-NEXT: csrr a1, vlenb1318; DOT-NEXT: slli a1, a1, 41319; DOT-NEXT: add a1, sp, a11320; DOT-NEXT: addi a1, a1, 161321; DOT-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1322; DOT-NEXT: addi a1, a0, 1281323; DOT-NEXT: li a2, 1281324; DOT-NEXT: vsetvli zero, a2, e8, m8, ta, ma1325; DOT-NEXT: vle8.v v8, (a0)1326; DOT-NEXT: csrr a0, vlenb1327; DOT-NEXT: slli a0, a0, 31328; DOT-NEXT: add a0, sp, a01329; DOT-NEXT: addi a0, a0, 161330; DOT-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1331; DOT-NEXT: li a0, 321332; DOT-NEXT: vle8.v v8, (a1)1333; DOT-NEXT: addi a1, sp, 161334; DOT-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1335; DOT-NEXT: vsetvli zero, a0, e32, m8, ta, ma1336; DOT-NEXT: vmv.v.i v24, 01337; DOT-NEXT: vmv.v.i v0, 01338; DOT-NEXT: csrr a0, vlenb1339; DOT-NEXT: slli a0, a0, 41340; DOT-NEXT: add a0, sp, a01341; DOT-NEXT: addi a0, a0, 161342; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1343; DOT-NEXT: csrr a0, vlenb1344; DOT-NEXT: slli a0, a0, 31345; DOT-NEXT: add a0, sp, a01346; DOT-NEXT: addi a0, a0, 161347; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1348; DOT-NEXT: vqdotsu.vv v0, v16, v81349; DOT-NEXT: csrr a0, vlenb1350; DOT-NEXT: slli a0, a0, 31351; DOT-NEXT: mv a1, a01352; DOT-NEXT: slli a0, a0, 11353; DOT-NEXT: add a0, a0, a11354; DOT-NEXT: add a0, sp, a01355; DOT-NEXT: addi a0, a0, 161356; DOT-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1357; DOT-NEXT: addi a0, sp, 161358; DOT-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1359; DOT-NEXT: vqdotsu.vv v24, v16, v81360; DOT-NEXT: vmv.v.v v8, v01361; DOT-NEXT: vmv.v.v v16, v241362; DOT-NEXT: csrr a0, vlenb1363; DOT-NEXT: slli a0, a0, 51364; DOT-NEXT: add sp, sp, a01365; DOT-NEXT: .cfi_def_cfa sp, 161366; DOT-NEXT: addi sp, sp, 161367; DOT-NEXT: .cfi_def_cfa_offset 01368; DOT-NEXT: ret1369entry:1370 %a.ext = sext <256 x i8> %a to <256 x i32>1371 %b.ext = zext <256 x i8> %b to <256 x i32>1372 %mul = mul <256 x i32> %b.ext, %a.ext1373 %res = call <64 x i32> @llvm.vector.partial.reduce.add(<64 x i32> zeroinitializer, <256 x i32> %mul)1374 ret <64 x i32> %res1375}1376 1377; Test legalization - integer promote1378define <4 x i31> @vqdotsu_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {1379; NODOT-LABEL: vqdotsu_vv_partial_v4i31_v16i7:1380; NODOT: # %bb.0: # %entry1381; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1382; NODOT-NEXT: vzext.vf4 v12, v81383; NODOT-NEXT: li a0, 1271384; NODOT-NEXT: vsetvli zero, zero, e8, m1, ta, ma1385; NODOT-NEXT: vand.vx v16, v9, a01386; NODOT-NEXT: lui a0, 5242881387; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma1388; NODOT-NEXT: vsll.vi v8, v12, 251389; NODOT-NEXT: addi a0, a0, -11390; NODOT-NEXT: vsra.vi v8, v8, 251391; NODOT-NEXT: vzext.vf4 v12, v161392; NODOT-NEXT: vmul.vv v8, v12, v81393; NODOT-NEXT: vand.vx v8, v8, a01394; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1395; NODOT-NEXT: vslidedown.vi v12, v8, 121396; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1397; NODOT-NEXT: vadd.vv v16, v12, v81398; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1399; NODOT-NEXT: vslidedown.vi v12, v8, 81400; NODOT-NEXT: vsetivli zero, 4, e32, m2, ta, ma1401; NODOT-NEXT: vslidedown.vi v8, v8, 41402; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1403; NODOT-NEXT: vadd.vv v8, v8, v121404; NODOT-NEXT: vadd.vv v8, v8, v161405; NODOT-NEXT: ret1406;1407; DOT-LABEL: vqdotsu_vv_partial_v4i31_v16i7:1408; DOT: # %bb.0: # %entry1409; DOT-NEXT: li a0, 1271410; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma1411; DOT-NEXT: vadd.vv v8, v8, v81412; DOT-NEXT: vand.vx v9, v9, a01413; DOT-NEXT: vsra.vi v10, v8, 11414; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1415; DOT-NEXT: vmv.v.i v8, 01416; DOT-NEXT: vqdotsu.vv v8, v10, v91417; DOT-NEXT: ret1418entry:1419 %a.ext = sext <16 x i7> %a to <16 x i31>1420 %b.ext = zext <16 x i7> %b to <16 x i31>1421 %mul = mul <16 x i31> %b.ext, %a.ext1422 %res = call <4 x i31> @llvm.vector.partial.reduce.add(<4 x i31> zeroinitializer, <16 x i31> %mul)1423 ret <4 x i31> %res1424}1425 1426 1427; Test legalization - expand1428define <1 x i32> @vqdotsu_vv_partial_v1i32_v2i8(<2 x i8> %a, <2 x i8> %b) {1429; CHECK-LABEL: vqdotsu_vv_partial_v1i32_v2i8:1430; CHECK: # %bb.0: # %entry1431; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma1432; CHECK-NEXT: vsext.vf2 v10, v81433; CHECK-NEXT: vzext.vf2 v8, v91434; CHECK-NEXT: vwmulsu.vv v9, v10, v81435; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1436; CHECK-NEXT: vslidedown.vi v8, v9, 11437; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1438; CHECK-NEXT: vadd.vv v8, v8, v91439; CHECK-NEXT: ret1440entry:1441 %a.ext = sext <2 x i8> %a to <2 x i32>1442 %b.ext = zext <2 x i8> %b to <2 x i32>1443 %mul = mul <2 x i32> %b.ext, %a.ext1444 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <2 x i32> %mul)1445 ret <1 x i32> %res1446}1447 1448; TODO: This isn't legal, but we could split it into two halves, and use1449; a pair of slides + two vqdotsu_vv here. Or alternatively, the mul1450; sequence + one vredsum, or a vadd reduce tree.1451define <1 x i32> @vqdotsu_vv_partial_v1i32_v8i8(<8 x i8> %a, <8 x i8> %b) {1452; CHECK-LABEL: vqdotsu_vv_partial_v1i32_v8i8:1453; CHECK: # %bb.0: # %entry1454; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1455; CHECK-NEXT: vsext.vf2 v10, v81456; CHECK-NEXT: vzext.vf2 v11, v91457; CHECK-NEXT: vwmulsu.vv v8, v10, v111458; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1459; CHECK-NEXT: vslidedown.vi v10, v8, 61460; CHECK-NEXT: vslidedown.vi v12, v8, 51461; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1462; CHECK-NEXT: vadd.vv v12, v12, v101463; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma1464; CHECK-NEXT: vslidedown.vi v10, v8, 71465; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1466; CHECK-NEXT: vslidedown.vi v11, v8, 31467; CHECK-NEXT: vslidedown.vi v13, v8, 21468; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1469; CHECK-NEXT: vadd.vv v10, v10, v81470; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma1471; CHECK-NEXT: vslidedown.vi v14, v8, 11472; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma1473; CHECK-NEXT: vslidedown.vi v8, v8, 41474; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma1475; CHECK-NEXT: vadd.vv v8, v11, v81476; CHECK-NEXT: vadd.vv v9, v14, v131477; CHECK-NEXT: vadd.vv v10, v12, v101478; CHECK-NEXT: vadd.vv v8, v9, v81479; CHECK-NEXT: vadd.vv v8, v8, v101480; CHECK-NEXT: ret1481entry:1482 %a.ext = sext <8 x i8> %a to <8 x i32>1483 %b.ext = zext <8 x i8> %b to <8 x i32>1484 %mul = mul <8 x i32> %b.ext, %a.ext1485 %res = call <1 x i32> @llvm.vector.partial.reduce.add(<1 x i32> zeroinitializer, <8 x i32> %mul)1486 ret <1 x i32> %res1487}1488 1489 1490define <4 x i32> @partial_of_sext(<16 x i8> %a) {1491; NODOT-LABEL: partial_of_sext:1492; NODOT: # %bb.0: # %entry1493; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1494; NODOT-NEXT: vsext.vf4 v12, v81495; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1496; NODOT-NEXT: vslidedown.vi v8, v12, 121497; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1498; NODOT-NEXT: vadd.vv v16, v8, v121499; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1500; NODOT-NEXT: vslidedown.vi v8, v12, 81501; NODOT-NEXT: vsetivli zero, 4, e32, m2, ta, ma1502; NODOT-NEXT: vslidedown.vi v10, v12, 41503; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1504; NODOT-NEXT: vadd.vv v8, v10, v81505; NODOT-NEXT: vadd.vv v8, v8, v161506; NODOT-NEXT: ret1507;1508; DOT-LABEL: partial_of_sext:1509; DOT: # %bb.0: # %entry1510; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma1511; DOT-NEXT: vmv.v.i v10, 11512; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1513; DOT-NEXT: vmv.v.i v9, 01514; DOT-NEXT: vqdot.vv v9, v8, v101515; DOT-NEXT: vmv.v.v v8, v91516; DOT-NEXT: ret1517entry:1518 %a.ext = sext <16 x i8> %a to <16 x i32>1519 %res = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> zeroinitializer, <16 x i32> %a.ext)1520 ret <4 x i32> %res1521}1522 1523define <4 x i32> @partial_of_zext(<16 x i8> %a) {1524; NODOT-LABEL: partial_of_zext:1525; NODOT: # %bb.0: # %entry1526; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1527; NODOT-NEXT: vzext.vf4 v12, v81528; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1529; NODOT-NEXT: vslidedown.vi v8, v12, 121530; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1531; NODOT-NEXT: vadd.vv v16, v8, v121532; NODOT-NEXT: vsetivli zero, 4, e32, m4, ta, ma1533; NODOT-NEXT: vslidedown.vi v8, v12, 81534; NODOT-NEXT: vsetivli zero, 4, e32, m2, ta, ma1535; NODOT-NEXT: vslidedown.vi v10, v12, 41536; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1537; NODOT-NEXT: vadd.vv v8, v10, v81538; NODOT-NEXT: vadd.vv v8, v8, v161539; NODOT-NEXT: ret1540;1541; DOT-LABEL: partial_of_zext:1542; DOT: # %bb.0: # %entry1543; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma1544; DOT-NEXT: vmv.v.i v10, 11545; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1546; DOT-NEXT: vmv.v.i v9, 01547; DOT-NEXT: vqdotu.vv v9, v8, v101548; DOT-NEXT: vmv.v.v v8, v91549; DOT-NEXT: ret1550entry:1551 %a.ext = zext <16 x i8> %a to <16 x i32>1552 %res = call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> zeroinitializer, <16 x i32> %a.ext)1553 ret <4 x i32> %res1554}1555 1556define i32 @vqdot_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {1557; NODOT-LABEL: vqdot_vv_accum_disjoint_or:1558; NODOT: # %bb.0: # %entry1559; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma1560; NODOT-NEXT: vsext.vf2 v16, v81561; NODOT-NEXT: vsext.vf2 v18, v91562; NODOT-NEXT: vwmul.vv v8, v16, v181563; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma1564; NODOT-NEXT: vor.vv v8, v8, v121565; NODOT-NEXT: vmv.s.x v12, zero1566; NODOT-NEXT: vredsum.vs v8, v8, v121567; NODOT-NEXT: vmv.x.s a0, v81568; NODOT-NEXT: ret1569;1570; DOT-LABEL: vqdot_vv_accum_disjoint_or:1571; DOT: # %bb.0: # %entry1572; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1573; DOT-NEXT: vmv1r.v v16, v121574; DOT-NEXT: vqdot.vv v16, v8, v91575; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma1576; DOT-NEXT: vmv.v.v v12, v161577; DOT-NEXT: vmv.s.x v8, zero1578; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1579; DOT-NEXT: vredsum.vs v8, v12, v81580; DOT-NEXT: vmv.x.s a0, v81581; DOT-NEXT: ret1582entry:1583 %a.sext = sext <16 x i8> %a to <16 x i32>1584 %b.sext = sext <16 x i8> %b to <16 x i32>1585 %mul = mul <16 x i32> %a.sext, %b.sext1586 %add = or disjoint <16 x i32> %mul, %x1587 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)1588 ret i32 %sum1589}1590 1591define i32 @vqdot_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {1592; CHECK-LABEL: vqdot_vv_accum_or:1593; CHECK: # %bb.0: # %entry1594; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1595; CHECK-NEXT: vsext.vf2 v16, v81596; CHECK-NEXT: vsext.vf2 v18, v91597; CHECK-NEXT: vwmul.vv v8, v16, v181598; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1599; CHECK-NEXT: vor.vv v8, v8, v121600; CHECK-NEXT: vmv.s.x v12, zero1601; CHECK-NEXT: vredsum.vs v8, v8, v121602; CHECK-NEXT: vmv.x.s a0, v81603; CHECK-NEXT: ret1604entry:1605 %a.sext = sext <16 x i8> %a to <16 x i32>1606 %b.sext = sext <16 x i8> %b to <16 x i32>1607 %mul = mul <16 x i32> %a.sext, %b.sext1608 %add = or <16 x i32> %mul, %x1609 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)1610 ret i32 %sum1611}1612 1613define i32 @vqdotu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {1614; NODOT-LABEL: vqdotu_vv_accum_disjoint_or:1615; NODOT: # %bb.0: # %entry1616; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma1617; NODOT-NEXT: vwmulu.vv v10, v8, v91618; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma1619; NODOT-NEXT: vwaddu.wv v12, v12, v101620; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma1621; NODOT-NEXT: vmv.s.x v8, zero1622; NODOT-NEXT: vredsum.vs v8, v12, v81623; NODOT-NEXT: vmv.x.s a0, v81624; NODOT-NEXT: ret1625;1626; DOT-LABEL: vqdotu_vv_accum_disjoint_or:1627; DOT: # %bb.0: # %entry1628; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1629; DOT-NEXT: vmv1r.v v16, v121630; DOT-NEXT: vqdotu.vv v16, v8, v91631; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma1632; DOT-NEXT: vmv.v.v v12, v161633; DOT-NEXT: vmv.s.x v8, zero1634; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1635; DOT-NEXT: vredsum.vs v8, v12, v81636; DOT-NEXT: vmv.x.s a0, v81637; DOT-NEXT: ret1638entry:1639 %a.zext = zext <16 x i8> %a to <16 x i32>1640 %b.zext = zext <16 x i8> %b to <16 x i32>1641 %mul = mul <16 x i32> %a.zext, %b.zext1642 %add = or disjoint <16 x i32> %mul, %x1643 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)1644 ret i32 %sum1645}1646 1647define i32 @vqdotsu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {1648; NODOT-LABEL: vqdotsu_vv_accum_disjoint_or:1649; NODOT: # %bb.0: # %entry1650; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma1651; NODOT-NEXT: vsext.vf2 v16, v81652; NODOT-NEXT: vzext.vf2 v18, v91653; NODOT-NEXT: vwmulsu.vv v8, v16, v181654; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma1655; NODOT-NEXT: vor.vv v8, v8, v121656; NODOT-NEXT: vmv.s.x v12, zero1657; NODOT-NEXT: vredsum.vs v8, v8, v121658; NODOT-NEXT: vmv.x.s a0, v81659; NODOT-NEXT: ret1660;1661; DOT-LABEL: vqdotsu_vv_accum_disjoint_or:1662; DOT: # %bb.0: # %entry1663; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma1664; DOT-NEXT: vmv1r.v v16, v121665; DOT-NEXT: vqdotsu.vv v16, v8, v91666; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma1667; DOT-NEXT: vmv.v.v v12, v161668; DOT-NEXT: vmv.s.x v8, zero1669; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma1670; DOT-NEXT: vredsum.vs v8, v12, v81671; DOT-NEXT: vmv.x.s a0, v81672; DOT-NEXT: ret1673entry:1674 %a.sext = sext <16 x i8> %a to <16 x i32>1675 %b.zext = zext <16 x i8> %b to <16 x i32>1676 %mul = mul <16 x i32> %a.sext, %b.zext1677 %add = or disjoint <16 x i32> %mul, %x1678 %sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)1679 ret i32 %sum1680}1681 1682;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1683; DOT32: {{.*}}1684; DOT64: {{.*}}1685