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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | \3; RUN: FileCheck %s -check-prefix=RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | \5; RUN: FileCheck %s -check-prefix=RV646 7; ================================================================================8; trunc <vscale x 1 x float>9; ================================================================================10 11define <vscale x 1 x i8> @trunc_nxv1f32_to_si8(<vscale x 1 x float> %x) {12; RV32-LABEL: trunc_nxv1f32_to_si8:13; RV32: # %bb.0:14; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma15; RV32-NEXT: vfabs.v v9, v816; RV32-NEXT: lui a0, 30720017; RV32-NEXT: fmv.w.x fa5, a018; RV32-NEXT: vmflt.vf v0, v9, fa519; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t20; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t21; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu22; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t23; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma24; RV32-NEXT: vfncvt.rtz.x.f.w v9, v825; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma26; RV32-NEXT: vnsrl.wi v8, v9, 027; RV32-NEXT: ret28;29; RV64-LABEL: trunc_nxv1f32_to_si8:30; RV64: # %bb.0:31; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma32; RV64-NEXT: vfabs.v v9, v833; RV64-NEXT: lui a0, 30720034; RV64-NEXT: fmv.w.x fa5, a035; RV64-NEXT: vmflt.vf v0, v9, fa536; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t37; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t38; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu39; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t40; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma41; RV64-NEXT: vfncvt.rtz.x.f.w v9, v842; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma43; RV64-NEXT: vnsrl.wi v8, v9, 044; RV64-NEXT: ret45 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)46 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i8>47 ret <vscale x 1 x i8> %b48}49 50define <vscale x 1 x i8> @trunc_nxv1f32_to_ui8(<vscale x 1 x float> %x) {51; RV32-LABEL: trunc_nxv1f32_to_ui8:52; RV32: # %bb.0:53; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma54; RV32-NEXT: vfabs.v v9, v855; RV32-NEXT: lui a0, 30720056; RV32-NEXT: fmv.w.x fa5, a057; RV32-NEXT: vmflt.vf v0, v9, fa558; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t59; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t60; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu61; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t62; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma63; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v864; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma65; RV32-NEXT: vnsrl.wi v8, v9, 066; RV32-NEXT: ret67;68; RV64-LABEL: trunc_nxv1f32_to_ui8:69; RV64: # %bb.0:70; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma71; RV64-NEXT: vfabs.v v9, v872; RV64-NEXT: lui a0, 30720073; RV64-NEXT: fmv.w.x fa5, a074; RV64-NEXT: vmflt.vf v0, v9, fa575; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t76; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t77; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu78; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t79; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma80; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v881; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma82; RV64-NEXT: vnsrl.wi v8, v9, 083; RV64-NEXT: ret84 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)85 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i8>86 ret <vscale x 1 x i8> %b87}88 89define <vscale x 1 x i16> @trunc_nxv1f32_to_si16(<vscale x 1 x float> %x) {90; RV32-LABEL: trunc_nxv1f32_to_si16:91; RV32: # %bb.0:92; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma93; RV32-NEXT: vfncvt.rtz.x.f.w v9, v894; RV32-NEXT: vmv1r.v v8, v995; RV32-NEXT: ret96;97; RV64-LABEL: trunc_nxv1f32_to_si16:98; RV64: # %bb.0:99; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma100; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8101; RV64-NEXT: vmv1r.v v8, v9102; RV64-NEXT: ret103 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)104 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i16>105 ret <vscale x 1 x i16> %b106}107 108define <vscale x 1 x i16> @trunc_nxv1f32_to_ui16(<vscale x 1 x float> %x) {109; RV32-LABEL: trunc_nxv1f32_to_ui16:110; RV32: # %bb.0:111; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma112; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8113; RV32-NEXT: vmv1r.v v8, v9114; RV32-NEXT: ret115;116; RV64-LABEL: trunc_nxv1f32_to_ui16:117; RV64: # %bb.0:118; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma119; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8120; RV64-NEXT: vmv1r.v v8, v9121; RV64-NEXT: ret122 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)123 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i16>124 ret <vscale x 1 x i16> %b125}126 127define <vscale x 1 x i32> @trunc_nxv1f32_to_si32(<vscale x 1 x float> %x) {128; RV32-LABEL: trunc_nxv1f32_to_si32:129; RV32: # %bb.0:130; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma131; RV32-NEXT: vfcvt.rtz.x.f.v v8, v8132; RV32-NEXT: ret133;134; RV64-LABEL: trunc_nxv1f32_to_si32:135; RV64: # %bb.0:136; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma137; RV64-NEXT: vfcvt.rtz.x.f.v v8, v8138; RV64-NEXT: ret139 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)140 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i32>141 ret <vscale x 1 x i32> %b142}143 144define <vscale x 1 x i32> @trunc_nxv1f32_to_ui32(<vscale x 1 x float> %x) {145; RV32-LABEL: trunc_nxv1f32_to_ui32:146; RV32: # %bb.0:147; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma148; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8149; RV32-NEXT: ret150;151; RV64-LABEL: trunc_nxv1f32_to_ui32:152; RV64: # %bb.0:153; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma154; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8155; RV64-NEXT: ret156 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)157 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i32>158 ret <vscale x 1 x i32> %b159}160 161define <vscale x 1 x i64> @trunc_nxv1f32_to_si64(<vscale x 1 x float> %x) {162; RV32-LABEL: trunc_nxv1f32_to_si64:163; RV32: # %bb.0:164; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma165; RV32-NEXT: vfwcvt.rtz.x.f.v v9, v8166; RV32-NEXT: vmv1r.v v8, v9167; RV32-NEXT: ret168;169; RV64-LABEL: trunc_nxv1f32_to_si64:170; RV64: # %bb.0:171; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma172; RV64-NEXT: vfwcvt.rtz.x.f.v v9, v8173; RV64-NEXT: vmv1r.v v8, v9174; RV64-NEXT: ret175 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)176 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i64>177 ret <vscale x 1 x i64> %b178}179 180define <vscale x 1 x i64> @trunc_nxv1f32_to_ui64(<vscale x 1 x float> %x) {181; RV32-LABEL: trunc_nxv1f32_to_ui64:182; RV32: # %bb.0:183; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma184; RV32-NEXT: vfwcvt.rtz.xu.f.v v9, v8185; RV32-NEXT: vmv1r.v v8, v9186; RV32-NEXT: ret187;188; RV64-LABEL: trunc_nxv1f32_to_ui64:189; RV64: # %bb.0:190; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma191; RV64-NEXT: vfwcvt.rtz.xu.f.v v9, v8192; RV64-NEXT: vmv1r.v v8, v9193; RV64-NEXT: ret194 %a = call <vscale x 1 x float> @llvm.trunc.nxv1f32(<vscale x 1 x float> %x)195 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i64>196 ret <vscale x 1 x i64> %b197}198 199; ================================================================================200; trunc <vscale x 4 x float>201; ================================================================================202 203define <vscale x 4 x i8> @trunc_nxv4f32_to_si8(<vscale x 4 x float> %x) {204; RV32-LABEL: trunc_nxv4f32_to_si8:205; RV32: # %bb.0:206; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma207; RV32-NEXT: vfabs.v v10, v8208; RV32-NEXT: lui a0, 307200209; RV32-NEXT: fmv.w.x fa5, a0210; RV32-NEXT: vmflt.vf v0, v10, fa5211; RV32-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t212; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t213; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu214; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t215; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma216; RV32-NEXT: vfncvt.rtz.x.f.w v10, v8217; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma218; RV32-NEXT: vnsrl.wi v8, v10, 0219; RV32-NEXT: ret220;221; RV64-LABEL: trunc_nxv4f32_to_si8:222; RV64: # %bb.0:223; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma224; RV64-NEXT: vfabs.v v10, v8225; RV64-NEXT: lui a0, 307200226; RV64-NEXT: fmv.w.x fa5, a0227; RV64-NEXT: vmflt.vf v0, v10, fa5228; RV64-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t229; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t230; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu231; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t232; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma233; RV64-NEXT: vfncvt.rtz.x.f.w v10, v8234; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma235; RV64-NEXT: vnsrl.wi v8, v10, 0236; RV64-NEXT: ret237 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)238 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i8>239 ret <vscale x 4 x i8> %b240}241 242define <vscale x 4 x i8> @trunc_nxv4f32_to_ui8(<vscale x 4 x float> %x) {243; RV32-LABEL: trunc_nxv4f32_to_ui8:244; RV32: # %bb.0:245; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma246; RV32-NEXT: vfabs.v v10, v8247; RV32-NEXT: lui a0, 307200248; RV32-NEXT: fmv.w.x fa5, a0249; RV32-NEXT: vmflt.vf v0, v10, fa5250; RV32-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t251; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t252; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu253; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t254; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma255; RV32-NEXT: vfncvt.rtz.xu.f.w v10, v8256; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma257; RV32-NEXT: vnsrl.wi v8, v10, 0258; RV32-NEXT: ret259;260; RV64-LABEL: trunc_nxv4f32_to_ui8:261; RV64: # %bb.0:262; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma263; RV64-NEXT: vfabs.v v10, v8264; RV64-NEXT: lui a0, 307200265; RV64-NEXT: fmv.w.x fa5, a0266; RV64-NEXT: vmflt.vf v0, v10, fa5267; RV64-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t268; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t269; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu270; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t271; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma272; RV64-NEXT: vfncvt.rtz.xu.f.w v10, v8273; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma274; RV64-NEXT: vnsrl.wi v8, v10, 0275; RV64-NEXT: ret276 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)277 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i8>278 ret <vscale x 4 x i8> %b279}280 281define <vscale x 4 x i16> @trunc_nxv4f32_to_si16(<vscale x 4 x float> %x) {282; RV32-LABEL: trunc_nxv4f32_to_si16:283; RV32: # %bb.0:284; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma285; RV32-NEXT: vfncvt.rtz.x.f.w v10, v8286; RV32-NEXT: vmv.v.v v8, v10287; RV32-NEXT: ret288;289; RV64-LABEL: trunc_nxv4f32_to_si16:290; RV64: # %bb.0:291; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma292; RV64-NEXT: vfncvt.rtz.x.f.w v10, v8293; RV64-NEXT: vmv.v.v v8, v10294; RV64-NEXT: ret295 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)296 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>297 ret <vscale x 4 x i16> %b298}299 300define <vscale x 4 x i16> @trunc_nxv4f32_to_ui16(<vscale x 4 x float> %x) {301; RV32-LABEL: trunc_nxv4f32_to_ui16:302; RV32: # %bb.0:303; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma304; RV32-NEXT: vfncvt.rtz.xu.f.w v10, v8305; RV32-NEXT: vmv.v.v v8, v10306; RV32-NEXT: ret307;308; RV64-LABEL: trunc_nxv4f32_to_ui16:309; RV64: # %bb.0:310; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma311; RV64-NEXT: vfncvt.rtz.xu.f.w v10, v8312; RV64-NEXT: vmv.v.v v8, v10313; RV64-NEXT: ret314 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)315 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i16>316 ret <vscale x 4 x i16> %b317}318 319define <vscale x 4 x i32> @trunc_nxv4f32_to_si32(<vscale x 4 x float> %x) {320; RV32-LABEL: trunc_nxv4f32_to_si32:321; RV32: # %bb.0:322; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma323; RV32-NEXT: vfcvt.rtz.x.f.v v8, v8324; RV32-NEXT: ret325;326; RV64-LABEL: trunc_nxv4f32_to_si32:327; RV64: # %bb.0:328; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma329; RV64-NEXT: vfcvt.rtz.x.f.v v8, v8330; RV64-NEXT: ret331 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)332 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i32>333 ret <vscale x 4 x i32> %b334}335 336define <vscale x 4 x i32> @trunc_nxv4f32_to_ui32(<vscale x 4 x float> %x) {337; RV32-LABEL: trunc_nxv4f32_to_ui32:338; RV32: # %bb.0:339; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma340; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8341; RV32-NEXT: ret342;343; RV64-LABEL: trunc_nxv4f32_to_ui32:344; RV64: # %bb.0:345; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma346; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8347; RV64-NEXT: ret348 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)349 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i32>350 ret <vscale x 4 x i32> %b351}352 353define <vscale x 4 x i64> @trunc_nxv4f32_to_si64(<vscale x 4 x float> %x) {354; RV32-LABEL: trunc_nxv4f32_to_si64:355; RV32: # %bb.0:356; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma357; RV32-NEXT: vmv2r.v v12, v8358; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v12359; RV32-NEXT: ret360;361; RV64-LABEL: trunc_nxv4f32_to_si64:362; RV64: # %bb.0:363; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma364; RV64-NEXT: vmv2r.v v12, v8365; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v12366; RV64-NEXT: ret367 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)368 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i64>369 ret <vscale x 4 x i64> %b370}371 372define <vscale x 4 x i64> @trunc_nxv4f32_to_ui64(<vscale x 4 x float> %x) {373; RV32-LABEL: trunc_nxv4f32_to_ui64:374; RV32: # %bb.0:375; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma376; RV32-NEXT: vmv2r.v v12, v8377; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v12378; RV32-NEXT: ret379;380; RV64-LABEL: trunc_nxv4f32_to_ui64:381; RV64: # %bb.0:382; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma383; RV64-NEXT: vmv2r.v v12, v8384; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v12385; RV64-NEXT: ret386 %a = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> %x)387 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i64>388 ret <vscale x 4 x i64> %b389}390 391; ================================================================================392; ceil <vscale x 1 x float>393; ================================================================================394 395define <vscale x 1 x i8> @ceil_nxv1f32_to_si8(<vscale x 1 x float> %x) {396; RV32-LABEL: ceil_nxv1f32_to_si8:397; RV32: # %bb.0:398; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma399; RV32-NEXT: vfabs.v v9, v8400; RV32-NEXT: lui a0, 307200401; RV32-NEXT: fmv.w.x fa5, a0402; RV32-NEXT: vmflt.vf v0, v9, fa5403; RV32-NEXT: fsrmi a0, 3404; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t405; RV32-NEXT: fsrm a0406; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t407; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu408; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t409; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma410; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8411; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma412; RV32-NEXT: vnsrl.wi v8, v9, 0413; RV32-NEXT: ret414;415; RV64-LABEL: ceil_nxv1f32_to_si8:416; RV64: # %bb.0:417; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma418; RV64-NEXT: vfabs.v v9, v8419; RV64-NEXT: lui a0, 307200420; RV64-NEXT: fmv.w.x fa5, a0421; RV64-NEXT: vmflt.vf v0, v9, fa5422; RV64-NEXT: fsrmi a0, 3423; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t424; RV64-NEXT: fsrm a0425; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t426; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu427; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t428; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma429; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8430; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma431; RV64-NEXT: vnsrl.wi v8, v9, 0432; RV64-NEXT: ret433 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)434 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i8>435 ret <vscale x 1 x i8> %b436}437 438define <vscale x 1 x i8> @ceil_nxv1f32_to_ui8(<vscale x 1 x float> %x) {439; RV32-LABEL: ceil_nxv1f32_to_ui8:440; RV32: # %bb.0:441; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma442; RV32-NEXT: vfabs.v v9, v8443; RV32-NEXT: lui a0, 307200444; RV32-NEXT: fmv.w.x fa5, a0445; RV32-NEXT: vmflt.vf v0, v9, fa5446; RV32-NEXT: fsrmi a0, 3447; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t448; RV32-NEXT: fsrm a0449; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t450; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu451; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t452; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma453; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8454; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma455; RV32-NEXT: vnsrl.wi v8, v9, 0456; RV32-NEXT: ret457;458; RV64-LABEL: ceil_nxv1f32_to_ui8:459; RV64: # %bb.0:460; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma461; RV64-NEXT: vfabs.v v9, v8462; RV64-NEXT: lui a0, 307200463; RV64-NEXT: fmv.w.x fa5, a0464; RV64-NEXT: vmflt.vf v0, v9, fa5465; RV64-NEXT: fsrmi a0, 3466; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t467; RV64-NEXT: fsrm a0468; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t469; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu470; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t471; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma472; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8473; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma474; RV64-NEXT: vnsrl.wi v8, v9, 0475; RV64-NEXT: ret476 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)477 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i8>478 ret <vscale x 1 x i8> %b479}480 481define <vscale x 1 x i16> @ceil_nxv1f32_to_si16(<vscale x 1 x float> %x) {482; RV32-LABEL: ceil_nxv1f32_to_si16:483; RV32: # %bb.0:484; RV32-NEXT: fsrmi a0, 3485; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma486; RV32-NEXT: vfncvt.x.f.w v9, v8487; RV32-NEXT: fsrm a0488; RV32-NEXT: vmv1r.v v8, v9489; RV32-NEXT: ret490;491; RV64-LABEL: ceil_nxv1f32_to_si16:492; RV64: # %bb.0:493; RV64-NEXT: fsrmi a0, 3494; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma495; RV64-NEXT: vfncvt.x.f.w v9, v8496; RV64-NEXT: fsrm a0497; RV64-NEXT: vmv1r.v v8, v9498; RV64-NEXT: ret499 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)500 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i16>501 ret <vscale x 1 x i16> %b502}503 504define <vscale x 1 x i16> @ceil_nxv1f32_to_ui16(<vscale x 1 x float> %x) {505; RV32-LABEL: ceil_nxv1f32_to_ui16:506; RV32: # %bb.0:507; RV32-NEXT: fsrmi a0, 3508; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma509; RV32-NEXT: vfncvt.xu.f.w v9, v8510; RV32-NEXT: fsrm a0511; RV32-NEXT: vmv1r.v v8, v9512; RV32-NEXT: ret513;514; RV64-LABEL: ceil_nxv1f32_to_ui16:515; RV64: # %bb.0:516; RV64-NEXT: fsrmi a0, 3517; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma518; RV64-NEXT: vfncvt.xu.f.w v9, v8519; RV64-NEXT: fsrm a0520; RV64-NEXT: vmv1r.v v8, v9521; RV64-NEXT: ret522 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)523 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i16>524 ret <vscale x 1 x i16> %b525}526 527define <vscale x 1 x i32> @ceil_nxv1f32_to_si32(<vscale x 1 x float> %x) {528; RV32-LABEL: ceil_nxv1f32_to_si32:529; RV32: # %bb.0:530; RV32-NEXT: fsrmi a0, 3531; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma532; RV32-NEXT: vfcvt.x.f.v v8, v8533; RV32-NEXT: fsrm a0534; RV32-NEXT: ret535;536; RV64-LABEL: ceil_nxv1f32_to_si32:537; RV64: # %bb.0:538; RV64-NEXT: fsrmi a0, 3539; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma540; RV64-NEXT: vfcvt.x.f.v v8, v8541; RV64-NEXT: fsrm a0542; RV64-NEXT: ret543 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)544 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i32>545 ret <vscale x 1 x i32> %b546}547 548define <vscale x 1 x i32> @ceil_nxv1f32_to_ui32(<vscale x 1 x float> %x) {549; RV32-LABEL: ceil_nxv1f32_to_ui32:550; RV32: # %bb.0:551; RV32-NEXT: fsrmi a0, 3552; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma553; RV32-NEXT: vfcvt.xu.f.v v8, v8554; RV32-NEXT: fsrm a0555; RV32-NEXT: ret556;557; RV64-LABEL: ceil_nxv1f32_to_ui32:558; RV64: # %bb.0:559; RV64-NEXT: fsrmi a0, 3560; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma561; RV64-NEXT: vfcvt.xu.f.v v8, v8562; RV64-NEXT: fsrm a0563; RV64-NEXT: ret564 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)565 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i32>566 ret <vscale x 1 x i32> %b567}568 569define <vscale x 1 x i64> @ceil_nxv1f32_to_si64(<vscale x 1 x float> %x) {570; RV32-LABEL: ceil_nxv1f32_to_si64:571; RV32: # %bb.0:572; RV32-NEXT: fsrmi a0, 3573; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma574; RV32-NEXT: vfwcvt.x.f.v v9, v8575; RV32-NEXT: fsrm a0576; RV32-NEXT: vmv1r.v v8, v9577; RV32-NEXT: ret578;579; RV64-LABEL: ceil_nxv1f32_to_si64:580; RV64: # %bb.0:581; RV64-NEXT: fsrmi a0, 3582; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma583; RV64-NEXT: vfwcvt.x.f.v v9, v8584; RV64-NEXT: fsrm a0585; RV64-NEXT: vmv1r.v v8, v9586; RV64-NEXT: ret587 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)588 %b = fptosi <vscale x 1 x float> %a to <vscale x 1 x i64>589 ret <vscale x 1 x i64> %b590}591 592define <vscale x 1 x i64> @ceil_nxv1f32_to_ui64(<vscale x 1 x float> %x) {593; RV32-LABEL: ceil_nxv1f32_to_ui64:594; RV32: # %bb.0:595; RV32-NEXT: fsrmi a0, 3596; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma597; RV32-NEXT: vfwcvt.xu.f.v v9, v8598; RV32-NEXT: fsrm a0599; RV32-NEXT: vmv1r.v v8, v9600; RV32-NEXT: ret601;602; RV64-LABEL: ceil_nxv1f32_to_ui64:603; RV64: # %bb.0:604; RV64-NEXT: fsrmi a0, 3605; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma606; RV64-NEXT: vfwcvt.xu.f.v v9, v8607; RV64-NEXT: fsrm a0608; RV64-NEXT: vmv1r.v v8, v9609; RV64-NEXT: ret610 %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)611 %b = fptoui <vscale x 1 x float> %a to <vscale x 1 x i64>612 ret <vscale x 1 x i64> %b613}614 615; ================================================================================616; ceil <vscale x 4 x float>617; ================================================================================618 619define <vscale x 4 x i8> @ceil_nxv4f32_to_si8(<vscale x 4 x float> %x) {620; RV32-LABEL: ceil_nxv4f32_to_si8:621; RV32: # %bb.0:622; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma623; RV32-NEXT: vfabs.v v10, v8624; RV32-NEXT: lui a0, 307200625; RV32-NEXT: fmv.w.x fa5, a0626; RV32-NEXT: vmflt.vf v0, v10, fa5627; RV32-NEXT: fsrmi a0, 3628; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t629; RV32-NEXT: fsrm a0630; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t631; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu632; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t633; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma634; RV32-NEXT: vfncvt.rtz.x.f.w v10, v8635; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma636; RV32-NEXT: vnsrl.wi v8, v10, 0637; RV32-NEXT: ret638;639; RV64-LABEL: ceil_nxv4f32_to_si8:640; RV64: # %bb.0:641; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma642; RV64-NEXT: vfabs.v v10, v8643; RV64-NEXT: lui a0, 307200644; RV64-NEXT: fmv.w.x fa5, a0645; RV64-NEXT: vmflt.vf v0, v10, fa5646; RV64-NEXT: fsrmi a0, 3647; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t648; RV64-NEXT: fsrm a0649; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t650; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu651; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t652; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma653; RV64-NEXT: vfncvt.rtz.x.f.w v10, v8654; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma655; RV64-NEXT: vnsrl.wi v8, v10, 0656; RV64-NEXT: ret657 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)658 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i8>659 ret <vscale x 4 x i8> %b660}661 662define <vscale x 4 x i8> @ceil_nxv4f32_to_ui8(<vscale x 4 x float> %x) {663; RV32-LABEL: ceil_nxv4f32_to_ui8:664; RV32: # %bb.0:665; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma666; RV32-NEXT: vfabs.v v10, v8667; RV32-NEXT: lui a0, 307200668; RV32-NEXT: fmv.w.x fa5, a0669; RV32-NEXT: vmflt.vf v0, v10, fa5670; RV32-NEXT: fsrmi a0, 3671; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t672; RV32-NEXT: fsrm a0673; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t674; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu675; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t676; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma677; RV32-NEXT: vfncvt.rtz.xu.f.w v10, v8678; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma679; RV32-NEXT: vnsrl.wi v8, v10, 0680; RV32-NEXT: ret681;682; RV64-LABEL: ceil_nxv4f32_to_ui8:683; RV64: # %bb.0:684; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma685; RV64-NEXT: vfabs.v v10, v8686; RV64-NEXT: lui a0, 307200687; RV64-NEXT: fmv.w.x fa5, a0688; RV64-NEXT: vmflt.vf v0, v10, fa5689; RV64-NEXT: fsrmi a0, 3690; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t691; RV64-NEXT: fsrm a0692; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t693; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu694; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t695; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma696; RV64-NEXT: vfncvt.rtz.xu.f.w v10, v8697; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma698; RV64-NEXT: vnsrl.wi v8, v10, 0699; RV64-NEXT: ret700 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)701 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i8>702 ret <vscale x 4 x i8> %b703}704 705define <vscale x 4 x i16> @ceil_nxv4f32_to_si16(<vscale x 4 x float> %x) {706; RV32-LABEL: ceil_nxv4f32_to_si16:707; RV32: # %bb.0:708; RV32-NEXT: fsrmi a0, 3709; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma710; RV32-NEXT: vfncvt.x.f.w v10, v8711; RV32-NEXT: fsrm a0712; RV32-NEXT: vmv.v.v v8, v10713; RV32-NEXT: ret714;715; RV64-LABEL: ceil_nxv4f32_to_si16:716; RV64: # %bb.0:717; RV64-NEXT: fsrmi a0, 3718; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma719; RV64-NEXT: vfncvt.x.f.w v10, v8720; RV64-NEXT: fsrm a0721; RV64-NEXT: vmv.v.v v8, v10722; RV64-NEXT: ret723 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)724 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>725 ret <vscale x 4 x i16> %b726}727 728define <vscale x 4 x i16> @ceil_nxv4f32_to_ui16(<vscale x 4 x float> %x) {729; RV32-LABEL: ceil_nxv4f32_to_ui16:730; RV32: # %bb.0:731; RV32-NEXT: fsrmi a0, 3732; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma733; RV32-NEXT: vfncvt.xu.f.w v10, v8734; RV32-NEXT: fsrm a0735; RV32-NEXT: vmv.v.v v8, v10736; RV32-NEXT: ret737;738; RV64-LABEL: ceil_nxv4f32_to_ui16:739; RV64: # %bb.0:740; RV64-NEXT: fsrmi a0, 3741; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma742; RV64-NEXT: vfncvt.xu.f.w v10, v8743; RV64-NEXT: fsrm a0744; RV64-NEXT: vmv.v.v v8, v10745; RV64-NEXT: ret746 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)747 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i16>748 ret <vscale x 4 x i16> %b749}750 751define <vscale x 4 x i32> @ceil_nxv4f32_to_si32(<vscale x 4 x float> %x) {752; RV32-LABEL: ceil_nxv4f32_to_si32:753; RV32: # %bb.0:754; RV32-NEXT: fsrmi a0, 3755; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma756; RV32-NEXT: vfcvt.x.f.v v8, v8757; RV32-NEXT: fsrm a0758; RV32-NEXT: ret759;760; RV64-LABEL: ceil_nxv4f32_to_si32:761; RV64: # %bb.0:762; RV64-NEXT: fsrmi a0, 3763; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma764; RV64-NEXT: vfcvt.x.f.v v8, v8765; RV64-NEXT: fsrm a0766; RV64-NEXT: ret767 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)768 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i32>769 ret <vscale x 4 x i32> %b770}771 772define <vscale x 4 x i32> @ceil_nxv4f32_to_ui32(<vscale x 4 x float> %x) {773; RV32-LABEL: ceil_nxv4f32_to_ui32:774; RV32: # %bb.0:775; RV32-NEXT: fsrmi a0, 3776; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma777; RV32-NEXT: vfcvt.xu.f.v v8, v8778; RV32-NEXT: fsrm a0779; RV32-NEXT: ret780;781; RV64-LABEL: ceil_nxv4f32_to_ui32:782; RV64: # %bb.0:783; RV64-NEXT: fsrmi a0, 3784; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma785; RV64-NEXT: vfcvt.xu.f.v v8, v8786; RV64-NEXT: fsrm a0787; RV64-NEXT: ret788 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)789 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i32>790 ret <vscale x 4 x i32> %b791}792 793define <vscale x 4 x i64> @ceil_nxv4f32_to_si64(<vscale x 4 x float> %x) {794; RV32-LABEL: ceil_nxv4f32_to_si64:795; RV32: # %bb.0:796; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma797; RV32-NEXT: vmv2r.v v12, v8798; RV32-NEXT: fsrmi a0, 3799; RV32-NEXT: vfwcvt.x.f.v v8, v12800; RV32-NEXT: fsrm a0801; RV32-NEXT: ret802;803; RV64-LABEL: ceil_nxv4f32_to_si64:804; RV64: # %bb.0:805; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma806; RV64-NEXT: vmv2r.v v12, v8807; RV64-NEXT: fsrmi a0, 3808; RV64-NEXT: vfwcvt.x.f.v v8, v12809; RV64-NEXT: fsrm a0810; RV64-NEXT: ret811 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)812 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i64>813 ret <vscale x 4 x i64> %b814}815 816define <vscale x 4 x i64> @ceil_nxv4f32_to_ui64(<vscale x 4 x float> %x) {817; RV32-LABEL: ceil_nxv4f32_to_ui64:818; RV32: # %bb.0:819; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma820; RV32-NEXT: vmv2r.v v12, v8821; RV32-NEXT: fsrmi a0, 3822; RV32-NEXT: vfwcvt.xu.f.v v8, v12823; RV32-NEXT: fsrm a0824; RV32-NEXT: ret825;826; RV64-LABEL: ceil_nxv4f32_to_ui64:827; RV64: # %bb.0:828; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma829; RV64-NEXT: vmv2r.v v12, v8830; RV64-NEXT: fsrmi a0, 3831; RV64-NEXT: vfwcvt.xu.f.v v8, v12832; RV64-NEXT: fsrm a0833; RV64-NEXT: ret834 %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)835 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i64>836 ret <vscale x 4 x i64> %b837}838 839; ================================================================================840; rint <vscale x 4 x float>841; ================================================================================842 843define <vscale x 4 x i8> @rint_nxv4f32_to_si8(<vscale x 4 x float> %x) {844; RV32-LABEL: rint_nxv4f32_to_si8:845; RV32: # %bb.0:846; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma847; RV32-NEXT: vfabs.v v10, v8848; RV32-NEXT: lui a0, 307200849; RV32-NEXT: fmv.w.x fa5, a0850; RV32-NEXT: vmflt.vf v0, v10, fa5851; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t852; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t853; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu854; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t855; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma856; RV32-NEXT: vfncvt.rtz.x.f.w v10, v8857; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma858; RV32-NEXT: vnsrl.wi v8, v10, 0859; RV32-NEXT: ret860;861; RV64-LABEL: rint_nxv4f32_to_si8:862; RV64: # %bb.0:863; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma864; RV64-NEXT: vfabs.v v10, v8865; RV64-NEXT: lui a0, 307200866; RV64-NEXT: fmv.w.x fa5, a0867; RV64-NEXT: vmflt.vf v0, v10, fa5868; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t869; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t870; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu871; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t872; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma873; RV64-NEXT: vfncvt.rtz.x.f.w v10, v8874; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma875; RV64-NEXT: vnsrl.wi v8, v10, 0876; RV64-NEXT: ret877 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)878 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i8>879 ret <vscale x 4 x i8> %b880}881 882define <vscale x 4 x i8> @rint_nxv4f32_to_ui8(<vscale x 4 x float> %x) {883; RV32-LABEL: rint_nxv4f32_to_ui8:884; RV32: # %bb.0:885; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma886; RV32-NEXT: vfabs.v v10, v8887; RV32-NEXT: lui a0, 307200888; RV32-NEXT: fmv.w.x fa5, a0889; RV32-NEXT: vmflt.vf v0, v10, fa5890; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t891; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t892; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu893; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t894; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma895; RV32-NEXT: vfncvt.rtz.xu.f.w v10, v8896; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma897; RV32-NEXT: vnsrl.wi v8, v10, 0898; RV32-NEXT: ret899;900; RV64-LABEL: rint_nxv4f32_to_ui8:901; RV64: # %bb.0:902; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma903; RV64-NEXT: vfabs.v v10, v8904; RV64-NEXT: lui a0, 307200905; RV64-NEXT: fmv.w.x fa5, a0906; RV64-NEXT: vmflt.vf v0, v10, fa5907; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t908; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t909; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu910; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t911; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma912; RV64-NEXT: vfncvt.rtz.xu.f.w v10, v8913; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma914; RV64-NEXT: vnsrl.wi v8, v10, 0915; RV64-NEXT: ret916 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)917 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i8>918 ret <vscale x 4 x i8> %b919}920 921define <vscale x 4 x i16> @rint_nxv4f32_to_si16(<vscale x 4 x float> %x) {922; RV32-LABEL: rint_nxv4f32_to_si16:923; RV32: # %bb.0:924; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma925; RV32-NEXT: vfncvt.x.f.w v10, v8926; RV32-NEXT: vmv.v.v v8, v10927; RV32-NEXT: ret928;929; RV64-LABEL: rint_nxv4f32_to_si16:930; RV64: # %bb.0:931; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma932; RV64-NEXT: vfncvt.x.f.w v10, v8933; RV64-NEXT: vmv.v.v v8, v10934; RV64-NEXT: ret935 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)936 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>937 ret <vscale x 4 x i16> %b938}939 940define <vscale x 4 x i16> @rint_nxv4f32_to_ui16(<vscale x 4 x float> %x) {941; RV32-LABEL: rint_nxv4f32_to_ui16:942; RV32: # %bb.0:943; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma944; RV32-NEXT: vfncvt.xu.f.w v10, v8945; RV32-NEXT: vmv.v.v v8, v10946; RV32-NEXT: ret947;948; RV64-LABEL: rint_nxv4f32_to_ui16:949; RV64: # %bb.0:950; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma951; RV64-NEXT: vfncvt.xu.f.w v10, v8952; RV64-NEXT: vmv.v.v v8, v10953; RV64-NEXT: ret954 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)955 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i16>956 ret <vscale x 4 x i16> %b957}958 959define <vscale x 4 x i32> @rint_nxv4f32_to_si32(<vscale x 4 x float> %x) {960; RV32-LABEL: rint_nxv4f32_to_si32:961; RV32: # %bb.0:962; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma963; RV32-NEXT: vfcvt.x.f.v v8, v8964; RV32-NEXT: ret965;966; RV64-LABEL: rint_nxv4f32_to_si32:967; RV64: # %bb.0:968; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma969; RV64-NEXT: vfcvt.x.f.v v8, v8970; RV64-NEXT: ret971 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)972 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i32>973 ret <vscale x 4 x i32> %b974}975 976define <vscale x 4 x i32> @rint_nxv4f32_to_ui32(<vscale x 4 x float> %x) {977; RV32-LABEL: rint_nxv4f32_to_ui32:978; RV32: # %bb.0:979; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma980; RV32-NEXT: vfcvt.xu.f.v v8, v8981; RV32-NEXT: ret982;983; RV64-LABEL: rint_nxv4f32_to_ui32:984; RV64: # %bb.0:985; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma986; RV64-NEXT: vfcvt.xu.f.v v8, v8987; RV64-NEXT: ret988 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)989 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i32>990 ret <vscale x 4 x i32> %b991}992 993define <vscale x 4 x i64> @rint_nxv4f32_to_si64(<vscale x 4 x float> %x) {994; RV32-LABEL: rint_nxv4f32_to_si64:995; RV32: # %bb.0:996; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma997; RV32-NEXT: vmv2r.v v12, v8998; RV32-NEXT: vfwcvt.x.f.v v8, v12999; RV32-NEXT: ret1000;1001; RV64-LABEL: rint_nxv4f32_to_si64:1002; RV64: # %bb.0:1003; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma1004; RV64-NEXT: vmv2r.v v12, v81005; RV64-NEXT: vfwcvt.x.f.v v8, v121006; RV64-NEXT: ret1007 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)1008 %b = fptosi <vscale x 4 x float> %a to <vscale x 4 x i64>1009 ret <vscale x 4 x i64> %b1010}1011 1012define <vscale x 4 x i64> @rint_nxv4f32_to_ui64(<vscale x 4 x float> %x) {1013; RV32-LABEL: rint_nxv4f32_to_ui64:1014; RV32: # %bb.0:1015; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma1016; RV32-NEXT: vmv2r.v v12, v81017; RV32-NEXT: vfwcvt.xu.f.v v8, v121018; RV32-NEXT: ret1019;1020; RV64-LABEL: rint_nxv4f32_to_ui64:1021; RV64: # %bb.0:1022; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma1023; RV64-NEXT: vmv2r.v v12, v81024; RV64-NEXT: vfwcvt.xu.f.v v8, v121025; RV64-NEXT: ret1026 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)1027 %b = fptoui <vscale x 4 x float> %a to <vscale x 4 x i64>1028 ret <vscale x 4 x i64> %b1029}1030