731 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \5; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH10; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \11; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN12; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \13; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN14; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \15; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN16; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \17; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN18 19define <vscale x 1 x bfloat> @vfmax_nxv1bf16_vv(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) {20; CHECK-LABEL: vfmax_nxv1bf16_vv:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma23; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v824; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma25; CHECK-NEXT: vmfeq.vv v0, v10, v1026; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma27; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v928; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma29; CHECK-NEXT: vmerge.vvm v9, v10, v8, v030; CHECK-NEXT: vmfeq.vv v0, v8, v831; CHECK-NEXT: vmerge.vvm v8, v8, v10, v032; CHECK-NEXT: vfmax.vv v9, v8, v933; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma34; CHECK-NEXT: vfncvtbf16.f.f.w v8, v935; CHECK-NEXT: ret36 %v = call <vscale x 1 x bfloat> @llvm.maximum.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b)37 ret <vscale x 1 x bfloat> %v38}39 40define <vscale x 2 x bfloat> @vfmax_nxv2bf16_vv(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {41; CHECK-LABEL: vfmax_nxv2bf16_vv:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma44; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v845; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma46; CHECK-NEXT: vmfeq.vv v0, v10, v1047; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma48; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v949; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma50; CHECK-NEXT: vmerge.vvm v9, v10, v8, v051; CHECK-NEXT: vmfeq.vv v0, v8, v852; CHECK-NEXT: vmerge.vvm v8, v8, v10, v053; CHECK-NEXT: vfmax.vv v9, v8, v954; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma55; CHECK-NEXT: vfncvtbf16.f.f.w v8, v956; CHECK-NEXT: ret57 %v = call <vscale x 2 x bfloat> @llvm.maximum.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)58 ret <vscale x 2 x bfloat> %v59}60 61define <vscale x 4 x bfloat> @vfmax_nxv4bf16_vv(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {62; CHECK-LABEL: vfmax_nxv4bf16_vv:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma65; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v866; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma67; CHECK-NEXT: vmfeq.vv v0, v10, v1068; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma69; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v970; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma71; CHECK-NEXT: vmerge.vvm v8, v10, v12, v072; CHECK-NEXT: vmfeq.vv v0, v12, v1273; CHECK-NEXT: vmerge.vvm v10, v12, v10, v074; CHECK-NEXT: vfmax.vv v10, v10, v875; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma76; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1077; CHECK-NEXT: ret78 %v = call <vscale x 4 x bfloat> @llvm.maximum.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)79 ret <vscale x 4 x bfloat> %v80}81 82define <vscale x 8 x bfloat> @vfmax_nxv8bf16_vv(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {83; CHECK-LABEL: vfmax_nxv8bf16_vv:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma86; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v887; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma88; CHECK-NEXT: vmfeq.vv v0, v12, v1289; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma90; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v1091; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma92; CHECK-NEXT: vmerge.vvm v8, v12, v16, v093; CHECK-NEXT: vmfeq.vv v0, v16, v1694; CHECK-NEXT: vmerge.vvm v12, v16, v12, v095; CHECK-NEXT: vfmax.vv v12, v12, v896; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma97; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1298; CHECK-NEXT: ret99 %v = call <vscale x 8 x bfloat> @llvm.maximum.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)100 ret <vscale x 8 x bfloat> %v101}102 103define <vscale x 16 x bfloat> @vfmax_nxv16bf16_vv(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) {104; CHECK-LABEL: vfmax_nxv16bf16_vv:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma107; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12108; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8109; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma110; CHECK-NEXT: vmfeq.vv v0, v24, v24111; CHECK-NEXT: vmfeq.vv v7, v16, v16112; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0113; CHECK-NEXT: vmv1r.v v0, v7114; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0115; CHECK-NEXT: vfmax.vv v16, v16, v8116; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma117; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16118; CHECK-NEXT: ret119 %v = call <vscale x 16 x bfloat> @llvm.maximum.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b)120 ret <vscale x 16 x bfloat> %v121}122 123define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) nounwind {124; ZVFH-LABEL: vfmax_nxv32bf16_vv:125; ZVFH: # %bb.0:126; ZVFH-NEXT: addi sp, sp, -16127; ZVFH-NEXT: csrr a0, vlenb128; ZVFH-NEXT: slli a0, a0, 3129; ZVFH-NEXT: mv a1, a0130; ZVFH-NEXT: slli a0, a0, 1131; ZVFH-NEXT: add a0, a0, a1132; ZVFH-NEXT: sub sp, sp, a0133; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma134; ZVFH-NEXT: vmv8r.v v24, v16135; ZVFH-NEXT: csrr a0, vlenb136; ZVFH-NEXT: slli a0, a0, 3137; ZVFH-NEXT: add a0, sp, a0138; ZVFH-NEXT: addi a0, a0, 16139; ZVFH-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill140; ZVFH-NEXT: vmv8r.v v0, v8141; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v24142; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v0143; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma144; ZVFH-NEXT: vmfeq.vv v0, v8, v8145; ZVFH-NEXT: vmfeq.vv v3, v16, v16146; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0147; ZVFH-NEXT: csrr a0, vlenb148; ZVFH-NEXT: slli a0, a0, 4149; ZVFH-NEXT: add a0, sp, a0150; ZVFH-NEXT: addi a0, a0, 16151; ZVFH-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill152; ZVFH-NEXT: vmv1r.v v0, v3153; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0154; ZVFH-NEXT: addi a0, sp, 16155; ZVFH-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill156; ZVFH-NEXT: csrr a0, vlenb157; ZVFH-NEXT: slli a0, a0, 3158; ZVFH-NEXT: add a0, sp, a0159; ZVFH-NEXT: addi a0, a0, 16160; ZVFH-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload161; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma162; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v12163; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v4164; ZVFH-NEXT: csrr a0, vlenb165; ZVFH-NEXT: slli a0, a0, 4166; ZVFH-NEXT: add a0, sp, a0167; ZVFH-NEXT: addi a0, a0, 16168; ZVFH-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload169; ZVFH-NEXT: addi a0, sp, 16170; ZVFH-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload171; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma172; ZVFH-NEXT: vfmax.vv v16, v0, v16173; ZVFH-NEXT: csrr a0, vlenb174; ZVFH-NEXT: slli a0, a0, 4175; ZVFH-NEXT: add a0, sp, a0176; ZVFH-NEXT: addi a0, a0, 16177; ZVFH-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill178; ZVFH-NEXT: vmfeq.vv v0, v8, v8179; ZVFH-NEXT: vmfeq.vv v7, v24, v24180; ZVFH-NEXT: vmerge.vvm v16, v8, v24, v0181; ZVFH-NEXT: vmv1r.v v0, v7182; ZVFH-NEXT: vmerge.vvm v8, v24, v8, v0183; ZVFH-NEXT: vfmax.vv v16, v8, v16184; ZVFH-NEXT: csrr a0, vlenb185; ZVFH-NEXT: slli a0, a0, 4186; ZVFH-NEXT: add a0, sp, a0187; ZVFH-NEXT: addi a0, a0, 16188; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload189; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma190; ZVFH-NEXT: vfncvtbf16.f.f.w v8, v24191; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v16192; ZVFH-NEXT: csrr a0, vlenb193; ZVFH-NEXT: slli a0, a0, 3194; ZVFH-NEXT: mv a1, a0195; ZVFH-NEXT: slli a0, a0, 1196; ZVFH-NEXT: add a0, a0, a1197; ZVFH-NEXT: add sp, sp, a0198; ZVFH-NEXT: addi sp, sp, 16199; ZVFH-NEXT: ret200;201; ZVFHMIN-LABEL: vfmax_nxv32bf16_vv:202; ZVFHMIN: # %bb.0:203; ZVFHMIN-NEXT: addi sp, sp, -16204; ZVFHMIN-NEXT: csrr a0, vlenb205; ZVFHMIN-NEXT: li a1, 24206; ZVFHMIN-NEXT: mul a0, a0, a1207; ZVFHMIN-NEXT: sub sp, sp, a0208; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma209; ZVFHMIN-NEXT: vmv8r.v v24, v16210; ZVFHMIN-NEXT: csrr a0, vlenb211; ZVFHMIN-NEXT: slli a0, a0, 3212; ZVFHMIN-NEXT: add a0, sp, a0213; ZVFHMIN-NEXT: addi a0, a0, 16214; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill215; ZVFHMIN-NEXT: vmv8r.v v0, v8216; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v24217; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v0218; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma219; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8220; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16221; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0222; ZVFHMIN-NEXT: csrr a0, vlenb223; ZVFHMIN-NEXT: slli a0, a0, 4224; ZVFHMIN-NEXT: add a0, sp, a0225; ZVFHMIN-NEXT: addi a0, a0, 16226; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill227; ZVFHMIN-NEXT: vmv1r.v v0, v3228; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0229; ZVFHMIN-NEXT: addi a0, sp, 16230; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill231; ZVFHMIN-NEXT: csrr a0, vlenb232; ZVFHMIN-NEXT: slli a0, a0, 3233; ZVFHMIN-NEXT: add a0, sp, a0234; ZVFHMIN-NEXT: addi a0, a0, 16235; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload236; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma237; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v12238; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v4239; ZVFHMIN-NEXT: csrr a0, vlenb240; ZVFHMIN-NEXT: slli a0, a0, 4241; ZVFHMIN-NEXT: add a0, sp, a0242; ZVFHMIN-NEXT: addi a0, a0, 16243; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload244; ZVFHMIN-NEXT: addi a0, sp, 16245; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload246; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma247; ZVFHMIN-NEXT: vfmax.vv v16, v0, v16248; ZVFHMIN-NEXT: csrr a0, vlenb249; ZVFHMIN-NEXT: slli a0, a0, 4250; ZVFHMIN-NEXT: add a0, sp, a0251; ZVFHMIN-NEXT: addi a0, a0, 16252; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill253; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8254; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24255; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0256; ZVFHMIN-NEXT: vmv1r.v v0, v7257; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0258; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16259; ZVFHMIN-NEXT: csrr a0, vlenb260; ZVFHMIN-NEXT: slli a0, a0, 4261; ZVFHMIN-NEXT: add a0, sp, a0262; ZVFHMIN-NEXT: addi a0, a0, 16263; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload264; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma265; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v24266; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v16267; ZVFHMIN-NEXT: csrr a0, vlenb268; ZVFHMIN-NEXT: li a1, 24269; ZVFHMIN-NEXT: mul a0, a0, a1270; ZVFHMIN-NEXT: add sp, sp, a0271; ZVFHMIN-NEXT: addi sp, sp, 16272; ZVFHMIN-NEXT: ret273 %v = call <vscale x 32 x bfloat> @llvm.maximum.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)274 ret <vscale x 32 x bfloat> %v275}276 277define <vscale x 1 x half> @vfmax_nxv1f16_vv(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {278; ZVFH-LABEL: vfmax_nxv1f16_vv:279; ZVFH: # %bb.0:280; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma281; ZVFH-NEXT: vmfeq.vv v0, v8, v8282; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0283; ZVFH-NEXT: vmfeq.vv v0, v9, v9284; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0285; ZVFH-NEXT: vfmax.vv v8, v8, v10286; ZVFH-NEXT: ret287;288; ZVFHMIN-LABEL: vfmax_nxv1f16_vv:289; ZVFHMIN: # %bb.0:290; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma291; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8292; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma293; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10294; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma295; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9296; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma297; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0298; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8299; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0300; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9301; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma302; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9303; ZVFHMIN-NEXT: ret304 %v = call <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b)305 ret <vscale x 1 x half> %v306}307 308define <vscale x 2 x half> @vfmax_nxv2f16_vv(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {309; ZVFH-LABEL: vfmax_nxv2f16_vv:310; ZVFH: # %bb.0:311; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma312; ZVFH-NEXT: vmfeq.vv v0, v8, v8313; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0314; ZVFH-NEXT: vmfeq.vv v0, v9, v9315; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0316; ZVFH-NEXT: vfmax.vv v8, v8, v10317; ZVFH-NEXT: ret318;319; ZVFHMIN-LABEL: vfmax_nxv2f16_vv:320; ZVFHMIN: # %bb.0:321; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma322; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8323; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma324; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10325; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma326; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9327; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma328; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0329; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8330; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0331; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9332; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma333; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9334; ZVFHMIN-NEXT: ret335 %v = call <vscale x 2 x half> @llvm.maximum.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)336 ret <vscale x 2 x half> %v337}338 339define <vscale x 4 x half> @vfmax_nxv4f16_vv(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {340; ZVFH-LABEL: vfmax_nxv4f16_vv:341; ZVFH: # %bb.0:342; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma343; ZVFH-NEXT: vmfeq.vv v0, v8, v8344; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0345; ZVFH-NEXT: vmfeq.vv v0, v9, v9346; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0347; ZVFH-NEXT: vfmax.vv v8, v8, v10348; ZVFH-NEXT: ret349;350; ZVFHMIN-LABEL: vfmax_nxv4f16_vv:351; ZVFHMIN: # %bb.0:352; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma353; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8354; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma355; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10356; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma357; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9358; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma359; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0360; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12361; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0362; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8363; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma364; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10365; ZVFHMIN-NEXT: ret366 %v = call <vscale x 4 x half> @llvm.maximum.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)367 ret <vscale x 4 x half> %v368}369 370define <vscale x 8 x half> @vfmax_nxv8f16_vv(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {371; ZVFH-LABEL: vfmax_nxv8f16_vv:372; ZVFH: # %bb.0:373; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma374; ZVFH-NEXT: vmfeq.vv v0, v8, v8375; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0376; ZVFH-NEXT: vmfeq.vv v0, v10, v10377; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0378; ZVFH-NEXT: vfmax.vv v8, v8, v12379; ZVFH-NEXT: ret380;381; ZVFHMIN-LABEL: vfmax_nxv8f16_vv:382; ZVFHMIN: # %bb.0:383; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma384; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8385; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma386; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12387; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma388; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10389; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma390; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0391; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16392; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0393; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8394; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma395; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12396; ZVFHMIN-NEXT: ret397 %v = call <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)398 ret <vscale x 8 x half> %v399}400 401define <vscale x 16 x half> @vfmax_nxv16f16_vv(<vscale x 16 x half> %a, <vscale x 16 x half> %b) {402; ZVFH-LABEL: vfmax_nxv16f16_vv:403; ZVFH: # %bb.0:404; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma405; ZVFH-NEXT: vmfeq.vv v0, v8, v8406; ZVFH-NEXT: vmerge.vvm v16, v8, v12, v0407; ZVFH-NEXT: vmfeq.vv v0, v12, v12408; ZVFH-NEXT: vmerge.vvm v8, v12, v8, v0409; ZVFH-NEXT: vfmax.vv v8, v8, v16410; ZVFH-NEXT: ret411;412; ZVFHMIN-LABEL: vfmax_nxv16f16_vv:413; ZVFHMIN: # %bb.0:414; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma415; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12416; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8417; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma418; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24419; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16420; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0421; ZVFHMIN-NEXT: vmv1r.v v0, v7422; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0423; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8424; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma425; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16426; ZVFHMIN-NEXT: ret427 %v = call <vscale x 16 x half> @llvm.maximum.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b)428 ret <vscale x 16 x half> %v429}430 431define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale x 32 x half> %b) nounwind {432; ZVFH-LABEL: vfmax_nxv32f16_vv:433; ZVFH: # %bb.0:434; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma435; ZVFH-NEXT: vmfeq.vv v0, v8, v8436; ZVFH-NEXT: vmfeq.vv v7, v16, v16437; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0438; ZVFH-NEXT: vmv1r.v v0, v7439; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0440; ZVFH-NEXT: vfmax.vv v8, v8, v24441; ZVFH-NEXT: ret442;443; ZVFHMIN-LABEL: vfmax_nxv32f16_vv:444; ZVFHMIN: # %bb.0:445; ZVFHMIN-NEXT: addi sp, sp, -16446; ZVFHMIN-NEXT: csrr a0, vlenb447; ZVFHMIN-NEXT: li a1, 24448; ZVFHMIN-NEXT: mul a0, a0, a1449; ZVFHMIN-NEXT: sub sp, sp, a0450; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma451; ZVFHMIN-NEXT: vmv8r.v v24, v16452; ZVFHMIN-NEXT: csrr a0, vlenb453; ZVFHMIN-NEXT: slli a0, a0, 3454; ZVFHMIN-NEXT: add a0, sp, a0455; ZVFHMIN-NEXT: addi a0, a0, 16456; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill457; ZVFHMIN-NEXT: vmv8r.v v0, v8458; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24459; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0460; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma461; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8462; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16463; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0464; ZVFHMIN-NEXT: csrr a0, vlenb465; ZVFHMIN-NEXT: slli a0, a0, 4466; ZVFHMIN-NEXT: add a0, sp, a0467; ZVFHMIN-NEXT: addi a0, a0, 16468; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill469; ZVFHMIN-NEXT: vmv1r.v v0, v3470; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0471; ZVFHMIN-NEXT: addi a0, sp, 16472; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill473; ZVFHMIN-NEXT: csrr a0, vlenb474; ZVFHMIN-NEXT: slli a0, a0, 3475; ZVFHMIN-NEXT: add a0, sp, a0476; ZVFHMIN-NEXT: addi a0, a0, 16477; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload478; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma479; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12480; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4481; ZVFHMIN-NEXT: csrr a0, vlenb482; ZVFHMIN-NEXT: slli a0, a0, 4483; ZVFHMIN-NEXT: add a0, sp, a0484; ZVFHMIN-NEXT: addi a0, a0, 16485; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload486; ZVFHMIN-NEXT: addi a0, sp, 16487; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload488; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma489; ZVFHMIN-NEXT: vfmax.vv v16, v0, v16490; ZVFHMIN-NEXT: csrr a0, vlenb491; ZVFHMIN-NEXT: slli a0, a0, 4492; ZVFHMIN-NEXT: add a0, sp, a0493; ZVFHMIN-NEXT: addi a0, a0, 16494; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill495; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8496; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24497; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0498; ZVFHMIN-NEXT: vmv1r.v v0, v7499; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0500; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16501; ZVFHMIN-NEXT: csrr a0, vlenb502; ZVFHMIN-NEXT: slli a0, a0, 4503; ZVFHMIN-NEXT: add a0, sp, a0504; ZVFHMIN-NEXT: addi a0, a0, 16505; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload506; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma507; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24508; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16509; ZVFHMIN-NEXT: csrr a0, vlenb510; ZVFHMIN-NEXT: li a1, 24511; ZVFHMIN-NEXT: mul a0, a0, a1512; ZVFHMIN-NEXT: add sp, sp, a0513; ZVFHMIN-NEXT: addi sp, sp, 16514; ZVFHMIN-NEXT: ret515 %v = call <vscale x 32 x half> @llvm.maximum.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)516 ret <vscale x 32 x half> %v517}518 519define <vscale x 1 x float> @vfmax_nxv1f32_vv(<vscale x 1 x float> %a, <vscale x 1 x float> %b) {520; CHECK-LABEL: vfmax_nxv1f32_vv:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma523; CHECK-NEXT: vmfeq.vv v0, v8, v8524; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0525; CHECK-NEXT: vmfeq.vv v0, v9, v9526; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0527; CHECK-NEXT: vfmax.vv v8, v8, v10528; CHECK-NEXT: ret529 %v = call <vscale x 1 x float> @llvm.maximum.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b)530 ret <vscale x 1 x float> %v531}532 533define <vscale x 2 x float> @vfmax_nxv2f32_vv(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {534; CHECK-LABEL: vfmax_nxv2f32_vv:535; CHECK: # %bb.0:536; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma537; CHECK-NEXT: vmfeq.vv v0, v8, v8538; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0539; CHECK-NEXT: vmfeq.vv v0, v9, v9540; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0541; CHECK-NEXT: vfmax.vv v8, v8, v10542; CHECK-NEXT: ret543 %v = call <vscale x 2 x float> @llvm.maximum.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)544 ret <vscale x 2 x float> %v545}546 547define <vscale x 4 x float> @vfmax_nxv4f32_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {548; CHECK-LABEL: vfmax_nxv4f32_vv:549; CHECK: # %bb.0:550; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma551; CHECK-NEXT: vmfeq.vv v0, v8, v8552; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0553; CHECK-NEXT: vmfeq.vv v0, v10, v10554; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0555; CHECK-NEXT: vfmax.vv v8, v8, v12556; CHECK-NEXT: ret557 %v = call <vscale x 4 x float> @llvm.maximum.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)558 ret <vscale x 4 x float> %v559}560 561define <vscale x 8 x float> @vfmax_nxv8f32_vv(<vscale x 8 x float> %a, <vscale x 8 x float> %b) {562; CHECK-LABEL: vfmax_nxv8f32_vv:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma565; CHECK-NEXT: vmfeq.vv v0, v8, v8566; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0567; CHECK-NEXT: vmfeq.vv v0, v12, v12568; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0569; CHECK-NEXT: vfmax.vv v8, v8, v16570; CHECK-NEXT: ret571 %v = call <vscale x 8 x float> @llvm.maximum.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b)572 ret <vscale x 8 x float> %v573}574 575define <vscale x 16 x float> @vfmax_nxv16f32_vv(<vscale x 16 x float> %a, <vscale x 16 x float> %b) nounwind {576; CHECK-LABEL: vfmax_nxv16f32_vv:577; CHECK: # %bb.0:578; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma579; CHECK-NEXT: vmfeq.vv v0, v8, v8580; CHECK-NEXT: vmfeq.vv v7, v16, v16581; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0582; CHECK-NEXT: vmv1r.v v0, v7583; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0584; CHECK-NEXT: vfmax.vv v8, v8, v24585; CHECK-NEXT: ret586 %v = call <vscale x 16 x float> @llvm.maximum.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)587 ret <vscale x 16 x float> %v588}589 590define <vscale x 1 x double> @vfmax_nxv1f64_vv(<vscale x 1 x double> %a, <vscale x 1 x double> %b) {591; CHECK-LABEL: vfmax_nxv1f64_vv:592; CHECK: # %bb.0:593; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma594; CHECK-NEXT: vmfeq.vv v0, v8, v8595; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0596; CHECK-NEXT: vmfeq.vv v0, v9, v9597; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0598; CHECK-NEXT: vfmax.vv v8, v8, v10599; CHECK-NEXT: ret600 %v = call <vscale x 1 x double> @llvm.maximum.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b)601 ret <vscale x 1 x double> %v602}603 604define <vscale x 2 x double> @vfmax_nxv2f64_vv(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {605; CHECK-LABEL: vfmax_nxv2f64_vv:606; CHECK: # %bb.0:607; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma608; CHECK-NEXT: vmfeq.vv v0, v8, v8609; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0610; CHECK-NEXT: vmfeq.vv v0, v10, v10611; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0612; CHECK-NEXT: vfmax.vv v8, v8, v12613; CHECK-NEXT: ret614 %v = call <vscale x 2 x double> @llvm.maximum.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)615 ret <vscale x 2 x double> %v616}617 618define <vscale x 4 x double> @vfmax_nxv4f64_vv(<vscale x 4 x double> %a, <vscale x 4 x double> %b) {619; CHECK-LABEL: vfmax_nxv4f64_vv:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma622; CHECK-NEXT: vmfeq.vv v0, v8, v8623; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0624; CHECK-NEXT: vmfeq.vv v0, v12, v12625; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0626; CHECK-NEXT: vfmax.vv v8, v8, v16627; CHECK-NEXT: ret628 %v = call <vscale x 4 x double> @llvm.maximum.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b)629 ret <vscale x 4 x double> %v630}631 632define <vscale x 8 x double> @vfmax_nxv8f64_vv(<vscale x 8 x double> %a, <vscale x 8 x double> %b) nounwind {633; CHECK-LABEL: vfmax_nxv8f64_vv:634; CHECK: # %bb.0:635; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma636; CHECK-NEXT: vmfeq.vv v0, v8, v8637; CHECK-NEXT: vmfeq.vv v7, v16, v16638; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0639; CHECK-NEXT: vmv1r.v v0, v7640; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0641; CHECK-NEXT: vfmax.vv v8, v8, v24642; CHECK-NEXT: ret643 %v = call <vscale x 8 x double> @llvm.maximum.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)644 ret <vscale x 8 x double> %v645}646 647define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnan(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {648; ZVFH-LABEL: vfmax_nxv1f16_vv_nnan:649; ZVFH: # %bb.0:650; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma651; ZVFH-NEXT: vfmax.vv v8, v8, v9652; ZVFH-NEXT: ret653;654; ZVFHMIN-LABEL: vfmax_nxv1f16_vv_nnan:655; ZVFHMIN: # %bb.0:656; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma657; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9658; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8659; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma660; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10661; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma662; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9663; ZVFHMIN-NEXT: ret664 %v = call nnan <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b)665 ret <vscale x 1 x half> %v666}667 668define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {669; ZVFH-LABEL: vfmax_nxv1f16_vv_nnana:670; ZVFH: # %bb.0:671; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, mu672; ZVFH-NEXT: vmfeq.vv v0, v9, v9673; ZVFH-NEXT: vmv1r.v v10, v9674; ZVFH-NEXT: vfadd.vv v10, v8, v8, v0.t675; ZVFH-NEXT: vfmax.vv v8, v10, v9676; ZVFH-NEXT: ret677;678; ZVFHMIN-LABEL: vfmax_nxv1f16_vv_nnana:679; ZVFHMIN: # %bb.0:680; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma681; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8682; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9683; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma684; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10685; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8686; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu687; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9688; ZVFHMIN-NEXT: vmv1r.v v9, v8689; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t690; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma691; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8692; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma693; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9694; ZVFHMIN-NEXT: ret695 %c = fadd nnan <vscale x 1 x half> %a, %a696 %v = call <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %c, <vscale x 1 x half> %b)697 ret <vscale x 1 x half> %v698}699 700define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {701; ZVFH-LABEL: vfmax_nxv1f16_vv_nnanb:702; ZVFH: # %bb.0:703; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, mu704; ZVFH-NEXT: vmfeq.vv v0, v8, v8705; ZVFH-NEXT: vmv1r.v v10, v8706; ZVFH-NEXT: vfadd.vv v10, v9, v9, v0.t707; ZVFH-NEXT: vfmax.vv v8, v8, v10708; ZVFH-NEXT: ret709;710; ZVFHMIN-LABEL: vfmax_nxv1f16_vv_nnanb:711; ZVFHMIN: # %bb.0:712; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma713; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9714; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8715; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma716; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10717; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9718; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu719; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8720; ZVFHMIN-NEXT: vmv1r.v v8, v9721; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t722; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma723; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8724; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma725; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9726; ZVFHMIN-NEXT: ret727 %c = fadd nnan <vscale x 1 x half> %b, %b728 %v = call <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %c)729 ret <vscale x 1 x half> %v730}731