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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv32 \9; RUN: -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \10; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \11; RUN: --check-prefixes=CHECK,ZVFHMIN12; RUN: llc -mtriple=riscv64 \13; RUN: -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \14; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \15; RUN: --check-prefixes=CHECK,ZVFHMIN16 17define <vscale x 1 x bfloat> @vfmax_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {18; CHECK-LABEL: vfmax_vv_nxv1bf16:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma21; CHECK-NEXT: vmv1r.v v10, v022; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v9, v0.t23; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t24; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma25; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t26; CHECK-NEXT: vmerge.vvm v8, v9, v11, v027; CHECK-NEXT: vmv1r.v v0, v1028; CHECK-NEXT: vmfeq.vv v0, v11, v11, v0.t29; CHECK-NEXT: vmerge.vvm v9, v11, v9, v030; CHECK-NEXT: vmv1r.v v0, v1031; CHECK-NEXT: vfmax.vv v9, v9, v8, v0.t32; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma33; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t34; CHECK-NEXT: ret35 %v = call <vscale x 1 x bfloat> @llvm.vp.maximum.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 %evl)36 ret <vscale x 1 x bfloat> %v37}38 39define <vscale x 1 x bfloat> @vfmax_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 zeroext %evl) {40; CHECK-LABEL: vfmax_vv_nxv1bf16_unmasked:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma43; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v844; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma45; CHECK-NEXT: vmfeq.vv v0, v10, v1046; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma47; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v948; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma49; CHECK-NEXT: vmerge.vvm v9, v10, v8, v050; CHECK-NEXT: vmfeq.vv v0, v8, v851; CHECK-NEXT: vmerge.vvm v8, v8, v10, v052; CHECK-NEXT: vfmax.vv v9, v8, v953; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma54; CHECK-NEXT: vfncvtbf16.f.f.w v8, v955; CHECK-NEXT: ret56 %v = call <vscale x 1 x bfloat> @llvm.vp.maximum.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)57 ret <vscale x 1 x bfloat> %v58}59 60define <vscale x 2 x bfloat> @vfmax_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {61; CHECK-LABEL: vfmax_vv_nxv2bf16:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma64; CHECK-NEXT: vmv1r.v v10, v065; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v9, v0.t66; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t67; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma68; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t69; CHECK-NEXT: vmerge.vvm v8, v9, v11, v070; CHECK-NEXT: vmv1r.v v0, v1071; CHECK-NEXT: vmfeq.vv v0, v11, v11, v0.t72; CHECK-NEXT: vmerge.vvm v9, v11, v9, v073; CHECK-NEXT: vmv1r.v v0, v1074; CHECK-NEXT: vfmax.vv v9, v9, v8, v0.t75; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma76; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t77; CHECK-NEXT: ret78 %v = call <vscale x 2 x bfloat> @llvm.vp.maximum.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 %evl)79 ret <vscale x 2 x bfloat> %v80}81 82define <vscale x 2 x bfloat> @vfmax_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evl) {83; CHECK-LABEL: vfmax_vv_nxv2bf16_unmasked:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma86; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v887; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma88; CHECK-NEXT: vmfeq.vv v0, v10, v1089; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma90; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v991; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma92; CHECK-NEXT: vmerge.vvm v9, v10, v8, v093; CHECK-NEXT: vmfeq.vv v0, v8, v894; CHECK-NEXT: vmerge.vvm v8, v8, v10, v095; CHECK-NEXT: vfmax.vv v9, v8, v996; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma97; CHECK-NEXT: vfncvtbf16.f.f.w v8, v998; CHECK-NEXT: ret99 %v = call <vscale x 2 x bfloat> @llvm.vp.maximum.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)100 ret <vscale x 2 x bfloat> %v101}102 103define <vscale x 4 x bfloat> @vfmax_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {104; CHECK-LABEL: vfmax_vv_nxv4bf16:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma107; CHECK-NEXT: vmv1r.v v10, v0108; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9, v0.t109; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v8, v0.t110; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma111; CHECK-NEXT: vmfeq.vv v8, v14, v14, v0.t112; CHECK-NEXT: vmv1r.v v0, v8113; CHECK-NEXT: vmerge.vvm v16, v14, v12, v0114; CHECK-NEXT: vmv1r.v v0, v10115; CHECK-NEXT: vmfeq.vv v8, v12, v12, v0.t116; CHECK-NEXT: vmv1r.v v0, v8117; CHECK-NEXT: vmerge.vvm v8, v12, v14, v0118; CHECK-NEXT: vmv1r.v v0, v10119; CHECK-NEXT: vfmax.vv v12, v8, v16, v0.t120; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma121; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t122; CHECK-NEXT: ret123 %v = call <vscale x 4 x bfloat> @llvm.vp.maximum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 %evl)124 ret <vscale x 4 x bfloat> %v125}126 127define <vscale x 4 x bfloat> @vfmax_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 zeroext %evl) {128; CHECK-LABEL: vfmax_vv_nxv4bf16_unmasked:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma131; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8132; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma133; CHECK-NEXT: vmfeq.vv v0, v10, v10134; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma135; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9136; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma137; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0138; CHECK-NEXT: vmfeq.vv v0, v12, v12139; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0140; CHECK-NEXT: vfmax.vv v10, v10, v8141; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma142; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10143; CHECK-NEXT: ret144 %v = call <vscale x 4 x bfloat> @llvm.vp.maximum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)145 ret <vscale x 4 x bfloat> %v146}147 148define <vscale x 8 x bfloat> @vfmax_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {149; CHECK-LABEL: vfmax_vv_nxv8bf16:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma152; CHECK-NEXT: vmv1r.v v12, v0153; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10, v0.t154; CHECK-NEXT: vfwcvtbf16.f.f.v v20, v8, v0.t155; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma156; CHECK-NEXT: vmfeq.vv v8, v20, v20, v0.t157; CHECK-NEXT: vmv1r.v v0, v8158; CHECK-NEXT: vmerge.vvm v24, v20, v16, v0159; CHECK-NEXT: vmv1r.v v0, v12160; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t161; CHECK-NEXT: vmv1r.v v0, v8162; CHECK-NEXT: vmerge.vvm v8, v16, v20, v0163; CHECK-NEXT: vmv1r.v v0, v12164; CHECK-NEXT: vfmax.vv v16, v8, v24, v0.t165; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma166; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t167; CHECK-NEXT: ret168 %v = call <vscale x 8 x bfloat> @llvm.vp.maximum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 %evl)169 ret <vscale x 8 x bfloat> %v170}171 172define <vscale x 8 x bfloat> @vfmax_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 zeroext %evl) {173; CHECK-LABEL: vfmax_vv_nxv8bf16_unmasked:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma176; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8177; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma178; CHECK-NEXT: vmfeq.vv v0, v12, v12179; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma180; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10181; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma182; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0183; CHECK-NEXT: vmfeq.vv v0, v16, v16184; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0185; CHECK-NEXT: vfmax.vv v12, v12, v8186; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma187; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12188; CHECK-NEXT: ret189 %v = call <vscale x 8 x bfloat> @llvm.vp.maximum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)190 ret <vscale x 8 x bfloat> %v191}192 193define <vscale x 16 x bfloat> @vfmax_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {194; CHECK-LABEL: vfmax_vv_nxv16bf16:195; CHECK: # %bb.0:196; CHECK-NEXT: addi sp, sp, -16197; CHECK-NEXT: .cfi_def_cfa_offset 16198; CHECK-NEXT: csrr a1, vlenb199; CHECK-NEXT: slli a1, a1, 3200; CHECK-NEXT: sub sp, sp, a1201; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb202; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma203; CHECK-NEXT: vmv1r.v v7, v0204; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t205; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t206; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma207; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t208; CHECK-NEXT: vmv1r.v v0, v8209; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0210; CHECK-NEXT: addi a0, sp, 16211; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill212; CHECK-NEXT: vmv1r.v v0, v7213; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t214; CHECK-NEXT: vmv1r.v v0, v8215; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0216; CHECK-NEXT: vmv1r.v v0, v7217; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload218; CHECK-NEXT: vfmax.vv v16, v8, v16, v0.t219; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma220; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t221; CHECK-NEXT: csrr a0, vlenb222; CHECK-NEXT: slli a0, a0, 3223; CHECK-NEXT: add sp, sp, a0224; CHECK-NEXT: .cfi_def_cfa sp, 16225; CHECK-NEXT: addi sp, sp, 16226; CHECK-NEXT: .cfi_def_cfa_offset 0227; CHECK-NEXT: ret228 %v = call <vscale x 16 x bfloat> @llvm.vp.maximum.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 %evl)229 ret <vscale x 16 x bfloat> %v230}231 232define <vscale x 16 x bfloat> @vfmax_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 zeroext %evl) {233; CHECK-LABEL: vfmax_vv_nxv16bf16_unmasked:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma236; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12237; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8238; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma239; CHECK-NEXT: vmfeq.vv v0, v24, v24240; CHECK-NEXT: vmfeq.vv v7, v16, v16241; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0242; CHECK-NEXT: vmv1r.v v0, v7243; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0244; CHECK-NEXT: vfmax.vv v16, v16, v8245; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma246; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16247; CHECK-NEXT: ret248 %v = call <vscale x 16 x bfloat> @llvm.vp.maximum.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)249 ret <vscale x 16 x bfloat> %v250}251 252define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {253; CHECK-LABEL: vfmax_vv_nxv32bf16:254; CHECK: # %bb.0:255; CHECK-NEXT: addi sp, sp, -16256; CHECK-NEXT: .cfi_def_cfa_offset 16257; CHECK-NEXT: csrr a1, vlenb258; CHECK-NEXT: li a2, 24259; CHECK-NEXT: mul a1, a1, a2260; CHECK-NEXT: sub sp, sp, a1261; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb262; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma263; CHECK-NEXT: vmv1r.v v7, v0264; CHECK-NEXT: csrr a1, vlenb265; CHECK-NEXT: slli a1, a1, 4266; CHECK-NEXT: add a1, sp, a1267; CHECK-NEXT: addi a1, a1, 16268; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill269; CHECK-NEXT: csrr a2, vlenb270; CHECK-NEXT: slli a1, a2, 1271; CHECK-NEXT: srli a2, a2, 2272; CHECK-NEXT: sub a3, a0, a1273; CHECK-NEXT: vslidedown.vx v6, v0, a2274; CHECK-NEXT: sltu a2, a0, a3275; CHECK-NEXT: addi a2, a2, -1276; CHECK-NEXT: and a2, a2, a3277; CHECK-NEXT: vmv1r.v v0, v6278; CHECK-NEXT: addi a3, sp, 16279; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill280; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma281; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t282; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma283; CHECK-NEXT: vmfeq.vv v5, v16, v16, v0.t284; CHECK-NEXT: vmv8r.v v8, v16285; CHECK-NEXT: csrr a2, vlenb286; CHECK-NEXT: slli a2, a2, 4287; CHECK-NEXT: add a2, sp, a2288; CHECK-NEXT: addi a2, a2, 16289; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload290; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma291; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t292; CHECK-NEXT: vmv1r.v v0, v5293; CHECK-NEXT: vmv8r.v v24, v8294; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma295; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0296; CHECK-NEXT: csrr a2, vlenb297; CHECK-NEXT: slli a2, a2, 3298; CHECK-NEXT: add a2, sp, a2299; CHECK-NEXT: addi a2, a2, 16300; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill301; CHECK-NEXT: vmv1r.v v0, v6302; CHECK-NEXT: vmfeq.vv v12, v16, v16, v0.t303; CHECK-NEXT: vmv1r.v v0, v12304; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0305; CHECK-NEXT: vmv1r.v v0, v6306; CHECK-NEXT: csrr a2, vlenb307; CHECK-NEXT: slli a2, a2, 3308; CHECK-NEXT: add a2, sp, a2309; CHECK-NEXT: addi a2, a2, 16310; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload311; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t312; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma313; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t314; CHECK-NEXT: bltu a0, a1, .LBB10_2315; CHECK-NEXT: # %bb.1:316; CHECK-NEXT: mv a0, a1317; CHECK-NEXT: .LBB10_2:318; CHECK-NEXT: vmv1r.v v0, v7319; CHECK-NEXT: addi a1, sp, 16320; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload321; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma322; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t323; CHECK-NEXT: csrr a0, vlenb324; CHECK-NEXT: slli a0, a0, 3325; CHECK-NEXT: add a0, sp, a0326; CHECK-NEXT: addi a0, a0, 16327; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill328; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma329; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t330; CHECK-NEXT: csrr a0, vlenb331; CHECK-NEXT: slli a0, a0, 4332; CHECK-NEXT: add a0, sp, a0333; CHECK-NEXT: addi a0, a0, 16334; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload335; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma336; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t337; CHECK-NEXT: vmv1r.v v0, v8338; CHECK-NEXT: csrr a0, vlenb339; CHECK-NEXT: slli a0, a0, 3340; CHECK-NEXT: add a0, sp, a0341; CHECK-NEXT: addi a0, a0, 16342; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload343; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma344; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0345; CHECK-NEXT: csrr a0, vlenb346; CHECK-NEXT: slli a0, a0, 4347; CHECK-NEXT: add a0, sp, a0348; CHECK-NEXT: addi a0, a0, 16349; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill350; CHECK-NEXT: vmv1r.v v0, v7351; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t352; CHECK-NEXT: vmv1r.v v0, v8353; CHECK-NEXT: csrr a0, vlenb354; CHECK-NEXT: slli a0, a0, 3355; CHECK-NEXT: add a0, sp, a0356; CHECK-NEXT: addi a0, a0, 16357; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload358; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0359; CHECK-NEXT: vmv1r.v v0, v7360; CHECK-NEXT: csrr a0, vlenb361; CHECK-NEXT: slli a0, a0, 4362; CHECK-NEXT: add a0, sp, a0363; CHECK-NEXT: addi a0, a0, 16364; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload365; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t366; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma367; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t368; CHECK-NEXT: csrr a0, vlenb369; CHECK-NEXT: li a1, 24370; CHECK-NEXT: mul a0, a0, a1371; CHECK-NEXT: add sp, sp, a0372; CHECK-NEXT: .cfi_def_cfa sp, 16373; CHECK-NEXT: addi sp, sp, 16374; CHECK-NEXT: .cfi_def_cfa_offset 0375; CHECK-NEXT: ret376 %v = call <vscale x 32 x bfloat> @llvm.vp.maximum.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 %evl)377 ret <vscale x 32 x bfloat> %v378}379 380define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 zeroext %evl) {381; CHECK-LABEL: vfmax_vv_nxv32bf16_unmasked:382; CHECK: # %bb.0:383; CHECK-NEXT: addi sp, sp, -16384; CHECK-NEXT: .cfi_def_cfa_offset 16385; CHECK-NEXT: csrr a1, vlenb386; CHECK-NEXT: li a2, 24387; CHECK-NEXT: mul a1, a1, a2388; CHECK-NEXT: sub sp, sp, a1389; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb390; CHECK-NEXT: csrr a1, vlenb391; CHECK-NEXT: slli a1, a1, 4392; CHECK-NEXT: add a1, sp, a1393; CHECK-NEXT: addi a1, a1, 16394; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill395; CHECK-NEXT: csrr a2, vlenb396; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma397; CHECK-NEXT: vmset.m v16398; CHECK-NEXT: slli a1, a2, 1399; CHECK-NEXT: srli a2, a2, 2400; CHECK-NEXT: sub a3, a0, a1401; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma402; CHECK-NEXT: vslidedown.vx v7, v16, a2403; CHECK-NEXT: sltu a2, a0, a3404; CHECK-NEXT: addi a2, a2, -1405; CHECK-NEXT: and a2, a2, a3406; CHECK-NEXT: vmv1r.v v0, v7407; CHECK-NEXT: csrr a3, vlenb408; CHECK-NEXT: slli a3, a3, 3409; CHECK-NEXT: add a3, sp, a3410; CHECK-NEXT: addi a3, a3, 16411; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill412; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma413; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t414; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma415; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t416; CHECK-NEXT: vmv8r.v v8, v16417; CHECK-NEXT: csrr a2, vlenb418; CHECK-NEXT: slli a2, a2, 4419; CHECK-NEXT: add a2, sp, a2420; CHECK-NEXT: addi a2, a2, 16421; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload422; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma423; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t424; CHECK-NEXT: vmv1r.v v0, v6425; CHECK-NEXT: vmv8r.v v24, v8426; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma427; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0428; CHECK-NEXT: addi a2, sp, 16429; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill430; CHECK-NEXT: vmv1r.v v0, v7431; CHECK-NEXT: vmfeq.vv v12, v16, v16, v0.t432; CHECK-NEXT: vmv1r.v v0, v12433; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0434; CHECK-NEXT: vmv1r.v v0, v7435; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload436; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t437; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma438; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t439; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill440; CHECK-NEXT: bltu a0, a1, .LBB11_2441; CHECK-NEXT: # %bb.1:442; CHECK-NEXT: mv a0, a1443; CHECK-NEXT: .LBB11_2:444; CHECK-NEXT: csrr a1, vlenb445; CHECK-NEXT: slli a1, a1, 3446; CHECK-NEXT: add a1, sp, a1447; CHECK-NEXT: addi a1, a1, 16448; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload449; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma450; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16451; CHECK-NEXT: csrr a0, vlenb452; CHECK-NEXT: slli a0, a0, 4453; CHECK-NEXT: add a0, sp, a0454; CHECK-NEXT: addi a0, a0, 16455; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload456; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0457; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma458; CHECK-NEXT: vmfeq.vv v0, v8, v8459; CHECK-NEXT: vmfeq.vv v7, v16, v16460; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0461; CHECK-NEXT: csrr a0, vlenb462; CHECK-NEXT: slli a0, a0, 4463; CHECK-NEXT: add a0, sp, a0464; CHECK-NEXT: addi a0, a0, 16465; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill466; CHECK-NEXT: vmv1r.v v0, v7467; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0468; CHECK-NEXT: csrr a0, vlenb469; CHECK-NEXT: slli a0, a0, 4470; CHECK-NEXT: add a0, sp, a0471; CHECK-NEXT: addi a0, a0, 16472; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload473; CHECK-NEXT: vfmax.vv v16, v16, v24474; CHECK-NEXT: addi a0, sp, 16475; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload476; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma477; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16478; CHECK-NEXT: csrr a0, vlenb479; CHECK-NEXT: li a1, 24480; CHECK-NEXT: mul a0, a0, a1481; CHECK-NEXT: add sp, sp, a0482; CHECK-NEXT: .cfi_def_cfa sp, 16483; CHECK-NEXT: addi sp, sp, 16484; CHECK-NEXT: .cfi_def_cfa_offset 0485; CHECK-NEXT: ret486 %v = call <vscale x 32 x bfloat> @llvm.vp.maximum.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)487 ret <vscale x 32 x bfloat> %v488}489 490define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {491; ZVFH-LABEL: vfmax_vv_nxv1f16:492; ZVFH: # %bb.0:493; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma494; ZVFH-NEXT: vmv1r.v v10, v0495; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t496; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0497; ZVFH-NEXT: vmv1r.v v0, v10498; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t499; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0500; ZVFH-NEXT: vmv1r.v v0, v10501; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t502; ZVFH-NEXT: ret503;504; ZVFHMIN-LABEL: vfmax_vv_nxv1f16:505; ZVFHMIN: # %bb.0:506; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma507; ZVFHMIN-NEXT: vmv1r.v v10, v0508; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t509; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t510; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma511; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t512; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0513; ZVFHMIN-NEXT: vmv1r.v v0, v10514; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t515; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0516; ZVFHMIN-NEXT: vmv1r.v v0, v10517; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8, v0.t518; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma519; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t520; ZVFHMIN-NEXT: ret521 %v = call <vscale x 1 x half> @llvm.vp.maximum.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 %evl)522 ret <vscale x 1 x half> %v523}524 525define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, i32 zeroext %evl) {526; ZVFH-LABEL: vfmax_vv_nxv1f16_unmasked:527; ZVFH: # %bb.0:528; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma529; ZVFH-NEXT: vmfeq.vv v0, v8, v8530; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0531; ZVFH-NEXT: vmfeq.vv v0, v9, v9532; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0533; ZVFH-NEXT: vfmax.vv v8, v8, v10534; ZVFH-NEXT: ret535;536; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked:537; ZVFHMIN: # %bb.0:538; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma539; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8540; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma541; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10542; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma543; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9544; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma545; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0546; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8547; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0548; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9549; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma550; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9551; ZVFHMIN-NEXT: ret552 %v = call <vscale x 1 x half> @llvm.vp.maximum.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)553 ret <vscale x 1 x half> %v554}555 556define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {557; ZVFH-LABEL: vfmax_vv_nxv2f16:558; ZVFH: # %bb.0:559; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma560; ZVFH-NEXT: vmv1r.v v10, v0561; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t562; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0563; ZVFH-NEXT: vmv1r.v v0, v10564; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t565; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0566; ZVFH-NEXT: vmv1r.v v0, v10567; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t568; ZVFH-NEXT: ret569;570; ZVFHMIN-LABEL: vfmax_vv_nxv2f16:571; ZVFHMIN: # %bb.0:572; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma573; ZVFHMIN-NEXT: vmv1r.v v10, v0574; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t575; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t576; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma577; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t578; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0579; ZVFHMIN-NEXT: vmv1r.v v0, v10580; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t581; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0582; ZVFHMIN-NEXT: vmv1r.v v0, v10583; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8, v0.t584; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma585; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t586; ZVFHMIN-NEXT: ret587 %v = call <vscale x 2 x half> @llvm.vp.maximum.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 %evl)588 ret <vscale x 2 x half> %v589}590 591define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evl) {592; ZVFH-LABEL: vfmax_vv_nxv2f16_unmasked:593; ZVFH: # %bb.0:594; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma595; ZVFH-NEXT: vmfeq.vv v0, v8, v8596; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0597; ZVFH-NEXT: vmfeq.vv v0, v9, v9598; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0599; ZVFH-NEXT: vfmax.vv v8, v8, v10600; ZVFH-NEXT: ret601;602; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked:603; ZVFHMIN: # %bb.0:604; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma605; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8606; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma607; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10608; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma609; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9610; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma611; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0612; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8613; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0614; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9615; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma616; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9617; ZVFHMIN-NEXT: ret618 %v = call <vscale x 2 x half> @llvm.vp.maximum.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)619 ret <vscale x 2 x half> %v620}621 622define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {623; ZVFH-LABEL: vfmax_vv_nxv4f16:624; ZVFH: # %bb.0:625; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma626; ZVFH-NEXT: vmv1r.v v10, v0627; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t628; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0629; ZVFH-NEXT: vmv1r.v v0, v10630; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t631; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0632; ZVFH-NEXT: vmv1r.v v0, v10633; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t634; ZVFH-NEXT: ret635;636; ZVFHMIN-LABEL: vfmax_vv_nxv4f16:637; ZVFHMIN: # %bb.0:638; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma639; ZVFHMIN-NEXT: vmv1r.v v10, v0640; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t641; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t642; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma643; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t644; ZVFHMIN-NEXT: vmv1r.v v0, v8645; ZVFHMIN-NEXT: vmerge.vvm v16, v14, v12, v0646; ZVFHMIN-NEXT: vmv1r.v v0, v10647; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t648; ZVFHMIN-NEXT: vmv1r.v v0, v8649; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v14, v0650; ZVFHMIN-NEXT: vmv1r.v v0, v10651; ZVFHMIN-NEXT: vfmax.vv v12, v8, v16, v0.t652; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma653; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t654; ZVFHMIN-NEXT: ret655 %v = call <vscale x 4 x half> @llvm.vp.maximum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)656 ret <vscale x 4 x half> %v657}658 659define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, i32 zeroext %evl) {660; ZVFH-LABEL: vfmax_vv_nxv4f16_unmasked:661; ZVFH: # %bb.0:662; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma663; ZVFH-NEXT: vmfeq.vv v0, v8, v8664; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0665; ZVFH-NEXT: vmfeq.vv v0, v9, v9666; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0667; ZVFH-NEXT: vfmax.vv v8, v8, v10668; ZVFH-NEXT: ret669;670; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked:671; ZVFHMIN: # %bb.0:672; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma673; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8674; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma675; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10676; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma677; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9678; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma679; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0680; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12681; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0682; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8683; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma684; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10685; ZVFHMIN-NEXT: ret686 %v = call <vscale x 4 x half> @llvm.vp.maximum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)687 ret <vscale x 4 x half> %v688}689 690define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {691; ZVFH-LABEL: vfmax_vv_nxv8f16:692; ZVFH: # %bb.0:693; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma694; ZVFH-NEXT: vmv1r.v v12, v0695; ZVFH-NEXT: vmfeq.vv v13, v8, v8, v0.t696; ZVFH-NEXT: vmv1r.v v0, v13697; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0698; ZVFH-NEXT: vmv1r.v v0, v12699; ZVFH-NEXT: vmfeq.vv v13, v10, v10, v0.t700; ZVFH-NEXT: vmv1r.v v0, v13701; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0702; ZVFH-NEXT: vmv1r.v v0, v12703; ZVFH-NEXT: vfmax.vv v8, v8, v14, v0.t704; ZVFH-NEXT: ret705;706; ZVFHMIN-LABEL: vfmax_vv_nxv8f16:707; ZVFHMIN: # %bb.0:708; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma709; ZVFHMIN-NEXT: vmv1r.v v12, v0710; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t711; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t712; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma713; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t714; ZVFHMIN-NEXT: vmv1r.v v0, v8715; ZVFHMIN-NEXT: vmerge.vvm v24, v20, v16, v0716; ZVFHMIN-NEXT: vmv1r.v v0, v12717; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t718; ZVFHMIN-NEXT: vmv1r.v v0, v8719; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v20, v0720; ZVFHMIN-NEXT: vmv1r.v v0, v12721; ZVFHMIN-NEXT: vfmax.vv v16, v8, v24, v0.t722; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma723; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t724; ZVFHMIN-NEXT: ret725 %v = call <vscale x 8 x half> @llvm.vp.maximum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)726 ret <vscale x 8 x half> %v727}728 729define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, i32 zeroext %evl) {730; ZVFH-LABEL: vfmax_vv_nxv8f16_unmasked:731; ZVFH: # %bb.0:732; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma733; ZVFH-NEXT: vmfeq.vv v0, v8, v8734; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0735; ZVFH-NEXT: vmfeq.vv v0, v10, v10736; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0737; ZVFH-NEXT: vfmax.vv v8, v8, v12738; ZVFH-NEXT: ret739;740; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked:741; ZVFHMIN: # %bb.0:742; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma743; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8744; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma745; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12746; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma747; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10748; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma749; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0750; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16751; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0752; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8753; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma754; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12755; ZVFHMIN-NEXT: ret756 %v = call <vscale x 8 x half> @llvm.vp.maximum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)757 ret <vscale x 8 x half> %v758}759 760define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {761; ZVFH-LABEL: vfmax_vv_nxv16f16:762; ZVFH: # %bb.0:763; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma764; ZVFH-NEXT: vmv1r.v v16, v0765; ZVFH-NEXT: vmfeq.vv v17, v8, v8, v0.t766; ZVFH-NEXT: vmv1r.v v0, v17767; ZVFH-NEXT: vmerge.vvm v20, v8, v12, v0768; ZVFH-NEXT: vmv1r.v v0, v16769; ZVFH-NEXT: vmfeq.vv v17, v12, v12, v0.t770; ZVFH-NEXT: vmv1r.v v0, v17771; ZVFH-NEXT: vmerge.vvm v8, v12, v8, v0772; ZVFH-NEXT: vmv1r.v v0, v16773; ZVFH-NEXT: vfmax.vv v8, v8, v20, v0.t774; ZVFH-NEXT: ret775;776; ZVFHMIN-LABEL: vfmax_vv_nxv16f16:777; ZVFHMIN: # %bb.0:778; ZVFHMIN-NEXT: addi sp, sp, -16779; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16780; ZVFHMIN-NEXT: csrr a1, vlenb781; ZVFHMIN-NEXT: slli a1, a1, 3782; ZVFHMIN-NEXT: sub sp, sp, a1783; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb784; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma785; ZVFHMIN-NEXT: vmv1r.v v7, v0786; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t787; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t788; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma789; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t790; ZVFHMIN-NEXT: vmv1r.v v0, v8791; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0792; ZVFHMIN-NEXT: addi a0, sp, 16793; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill794; ZVFHMIN-NEXT: vmv1r.v v0, v7795; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t796; ZVFHMIN-NEXT: vmv1r.v v0, v8797; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0798; ZVFHMIN-NEXT: vmv1r.v v0, v7799; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload800; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16, v0.t801; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma802; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t803; ZVFHMIN-NEXT: csrr a0, vlenb804; ZVFHMIN-NEXT: slli a0, a0, 3805; ZVFHMIN-NEXT: add sp, sp, a0806; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16807; ZVFHMIN-NEXT: addi sp, sp, 16808; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0809; ZVFHMIN-NEXT: ret810 %v = call <vscale x 16 x half> @llvm.vp.maximum.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 %evl)811 ret <vscale x 16 x half> %v812}813 814define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, i32 zeroext %evl) {815; ZVFH-LABEL: vfmax_vv_nxv16f16_unmasked:816; ZVFH: # %bb.0:817; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma818; ZVFH-NEXT: vmfeq.vv v0, v8, v8819; ZVFH-NEXT: vmerge.vvm v16, v8, v12, v0820; ZVFH-NEXT: vmfeq.vv v0, v12, v12821; ZVFH-NEXT: vmerge.vvm v8, v12, v8, v0822; ZVFH-NEXT: vfmax.vv v8, v8, v16823; ZVFH-NEXT: ret824;825; ZVFHMIN-LABEL: vfmax_vv_nxv16f16_unmasked:826; ZVFHMIN: # %bb.0:827; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma828; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12829; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8830; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma831; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24832; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16833; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0834; ZVFHMIN-NEXT: vmv1r.v v0, v7835; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0836; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8837; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma838; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16839; ZVFHMIN-NEXT: ret840 %v = call <vscale x 16 x half> @llvm.vp.maximum.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)841 ret <vscale x 16 x half> %v842}843 844define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {845; ZVFH-LABEL: vfmax_vv_nxv32f16:846; ZVFH: # %bb.0:847; ZVFH-NEXT: addi sp, sp, -16848; ZVFH-NEXT: .cfi_def_cfa_offset 16849; ZVFH-NEXT: csrr a1, vlenb850; ZVFH-NEXT: slli a1, a1, 3851; ZVFH-NEXT: sub sp, sp, a1852; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb853; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma854; ZVFH-NEXT: vmv1r.v v7, v0855; ZVFH-NEXT: vmfeq.vv v25, v8, v8, v0.t856; ZVFH-NEXT: vmv1r.v v0, v25857; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0858; ZVFH-NEXT: addi a0, sp, 16859; ZVFH-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill860; ZVFH-NEXT: vmv1r.v v0, v7861; ZVFH-NEXT: vmfeq.vv v25, v16, v16, v0.t862; ZVFH-NEXT: vmv1r.v v0, v25863; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0864; ZVFH-NEXT: vmv1r.v v0, v7865; ZVFH-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload866; ZVFH-NEXT: vfmax.vv v8, v8, v16, v0.t867; ZVFH-NEXT: csrr a0, vlenb868; ZVFH-NEXT: slli a0, a0, 3869; ZVFH-NEXT: add sp, sp, a0870; ZVFH-NEXT: .cfi_def_cfa sp, 16871; ZVFH-NEXT: addi sp, sp, 16872; ZVFH-NEXT: .cfi_def_cfa_offset 0873; ZVFH-NEXT: ret874;875; ZVFHMIN-LABEL: vfmax_vv_nxv32f16:876; ZVFHMIN: # %bb.0:877; ZVFHMIN-NEXT: addi sp, sp, -16878; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16879; ZVFHMIN-NEXT: csrr a1, vlenb880; ZVFHMIN-NEXT: li a2, 24881; ZVFHMIN-NEXT: mul a1, a1, a2882; ZVFHMIN-NEXT: sub sp, sp, a1883; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb884; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma885; ZVFHMIN-NEXT: vmv1r.v v7, v0886; ZVFHMIN-NEXT: csrr a1, vlenb887; ZVFHMIN-NEXT: slli a1, a1, 4888; ZVFHMIN-NEXT: add a1, sp, a1889; ZVFHMIN-NEXT: addi a1, a1, 16890; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill891; ZVFHMIN-NEXT: csrr a2, vlenb892; ZVFHMIN-NEXT: slli a1, a2, 1893; ZVFHMIN-NEXT: srli a2, a2, 2894; ZVFHMIN-NEXT: sub a3, a0, a1895; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2896; ZVFHMIN-NEXT: sltu a2, a0, a3897; ZVFHMIN-NEXT: addi a2, a2, -1898; ZVFHMIN-NEXT: and a2, a2, a3899; ZVFHMIN-NEXT: vmv1r.v v0, v6900; ZVFHMIN-NEXT: addi a3, sp, 16901; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill902; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma903; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t904; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma905; ZVFHMIN-NEXT: vmfeq.vv v5, v16, v16, v0.t906; ZVFHMIN-NEXT: vmv8r.v v8, v16907; ZVFHMIN-NEXT: csrr a2, vlenb908; ZVFHMIN-NEXT: slli a2, a2, 4909; ZVFHMIN-NEXT: add a2, sp, a2910; ZVFHMIN-NEXT: addi a2, a2, 16911; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload912; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma913; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t914; ZVFHMIN-NEXT: vmv1r.v v0, v5915; ZVFHMIN-NEXT: vmv8r.v v24, v8916; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma917; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0918; ZVFHMIN-NEXT: csrr a2, vlenb919; ZVFHMIN-NEXT: slli a2, a2, 3920; ZVFHMIN-NEXT: add a2, sp, a2921; ZVFHMIN-NEXT: addi a2, a2, 16922; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill923; ZVFHMIN-NEXT: vmv1r.v v0, v6924; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t925; ZVFHMIN-NEXT: vmv1r.v v0, v12926; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0927; ZVFHMIN-NEXT: vmv1r.v v0, v6928; ZVFHMIN-NEXT: csrr a2, vlenb929; ZVFHMIN-NEXT: slli a2, a2, 3930; ZVFHMIN-NEXT: add a2, sp, a2931; ZVFHMIN-NEXT: addi a2, a2, 16932; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload933; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t934; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma935; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t936; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2937; ZVFHMIN-NEXT: # %bb.1:938; ZVFHMIN-NEXT: mv a0, a1939; ZVFHMIN-NEXT: .LBB22_2:940; ZVFHMIN-NEXT: vmv1r.v v0, v7941; ZVFHMIN-NEXT: addi a1, sp, 16942; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload943; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma944; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t945; ZVFHMIN-NEXT: csrr a0, vlenb946; ZVFHMIN-NEXT: slli a0, a0, 3947; ZVFHMIN-NEXT: add a0, sp, a0948; ZVFHMIN-NEXT: addi a0, a0, 16949; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill950; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma951; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t952; ZVFHMIN-NEXT: csrr a0, vlenb953; ZVFHMIN-NEXT: slli a0, a0, 4954; ZVFHMIN-NEXT: add a0, sp, a0955; ZVFHMIN-NEXT: addi a0, a0, 16956; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload957; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma958; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t959; ZVFHMIN-NEXT: vmv1r.v v0, v8960; ZVFHMIN-NEXT: csrr a0, vlenb961; ZVFHMIN-NEXT: slli a0, a0, 3962; ZVFHMIN-NEXT: add a0, sp, a0963; ZVFHMIN-NEXT: addi a0, a0, 16964; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload965; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma966; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0967; ZVFHMIN-NEXT: csrr a0, vlenb968; ZVFHMIN-NEXT: slli a0, a0, 4969; ZVFHMIN-NEXT: add a0, sp, a0970; ZVFHMIN-NEXT: addi a0, a0, 16971; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill972; ZVFHMIN-NEXT: vmv1r.v v0, v7973; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t974; ZVFHMIN-NEXT: vmv1r.v v0, v8975; ZVFHMIN-NEXT: csrr a0, vlenb976; ZVFHMIN-NEXT: slli a0, a0, 3977; ZVFHMIN-NEXT: add a0, sp, a0978; ZVFHMIN-NEXT: addi a0, a0, 16979; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload980; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0981; ZVFHMIN-NEXT: vmv1r.v v0, v7982; ZVFHMIN-NEXT: csrr a0, vlenb983; ZVFHMIN-NEXT: slli a0, a0, 4984; ZVFHMIN-NEXT: add a0, sp, a0985; ZVFHMIN-NEXT: addi a0, a0, 16986; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload987; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t988; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma989; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t990; ZVFHMIN-NEXT: csrr a0, vlenb991; ZVFHMIN-NEXT: li a1, 24992; ZVFHMIN-NEXT: mul a0, a0, a1993; ZVFHMIN-NEXT: add sp, sp, a0994; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16995; ZVFHMIN-NEXT: addi sp, sp, 16996; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0997; ZVFHMIN-NEXT: ret998 %v = call <vscale x 32 x half> @llvm.vp.maximum.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 %evl)999 ret <vscale x 32 x half> %v1000}1001 1002define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, i32 zeroext %evl) {1003; ZVFH-LABEL: vfmax_vv_nxv32f16_unmasked:1004; ZVFH: # %bb.0:1005; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma1006; ZVFH-NEXT: vmfeq.vv v0, v8, v81007; ZVFH-NEXT: vmfeq.vv v7, v16, v161008; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v01009; ZVFH-NEXT: vmv1r.v v0, v71010; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v01011; ZVFH-NEXT: vfmax.vv v8, v8, v241012; ZVFH-NEXT: ret1013;1014; ZVFHMIN-LABEL: vfmax_vv_nxv32f16_unmasked:1015; ZVFHMIN: # %bb.0:1016; ZVFHMIN-NEXT: addi sp, sp, -161017; ZVFHMIN-NEXT: .cfi_def_cfa_offset 161018; ZVFHMIN-NEXT: csrr a1, vlenb1019; ZVFHMIN-NEXT: li a2, 241020; ZVFHMIN-NEXT: mul a1, a1, a21021; ZVFHMIN-NEXT: sub sp, sp, a11022; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1023; ZVFHMIN-NEXT: csrr a1, vlenb1024; ZVFHMIN-NEXT: slli a1, a1, 41025; ZVFHMIN-NEXT: add a1, sp, a11026; ZVFHMIN-NEXT: addi a1, a1, 161027; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1028; ZVFHMIN-NEXT: csrr a2, vlenb1029; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma1030; ZVFHMIN-NEXT: vmset.m v161031; ZVFHMIN-NEXT: slli a1, a2, 11032; ZVFHMIN-NEXT: srli a2, a2, 21033; ZVFHMIN-NEXT: sub a3, a0, a11034; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma1035; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a21036; ZVFHMIN-NEXT: sltu a2, a0, a31037; ZVFHMIN-NEXT: addi a2, a2, -11038; ZVFHMIN-NEXT: and a2, a2, a31039; ZVFHMIN-NEXT: vmv1r.v v0, v71040; ZVFHMIN-NEXT: csrr a3, vlenb1041; ZVFHMIN-NEXT: slli a3, a3, 31042; ZVFHMIN-NEXT: add a3, sp, a31043; ZVFHMIN-NEXT: addi a3, a3, 161044; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill1045; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma1046; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t1047; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma1048; ZVFHMIN-NEXT: vmfeq.vv v6, v16, v16, v0.t1049; ZVFHMIN-NEXT: vmv8r.v v8, v161050; ZVFHMIN-NEXT: csrr a2, vlenb1051; ZVFHMIN-NEXT: slli a2, a2, 41052; ZVFHMIN-NEXT: add a2, sp, a21053; ZVFHMIN-NEXT: addi a2, a2, 161054; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload1055; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma1056; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t1057; ZVFHMIN-NEXT: vmv1r.v v0, v61058; ZVFHMIN-NEXT: vmv8r.v v24, v81059; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma1060; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v01061; ZVFHMIN-NEXT: addi a2, sp, 161062; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1063; ZVFHMIN-NEXT: vmv1r.v v0, v71064; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t1065; ZVFHMIN-NEXT: vmv1r.v v0, v121066; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v01067; ZVFHMIN-NEXT: vmv1r.v v0, v71068; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload1069; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t1070; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma1071; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t1072; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1073; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_21074; ZVFHMIN-NEXT: # %bb.1:1075; ZVFHMIN-NEXT: mv a0, a11076; ZVFHMIN-NEXT: .LBB23_2:1077; ZVFHMIN-NEXT: csrr a1, vlenb1078; ZVFHMIN-NEXT: slli a1, a1, 31079; ZVFHMIN-NEXT: add a1, sp, a11080; ZVFHMIN-NEXT: addi a1, a1, 161081; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1082; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma1083; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v161084; ZVFHMIN-NEXT: csrr a0, vlenb1085; ZVFHMIN-NEXT: slli a0, a0, 41086; ZVFHMIN-NEXT: add a0, sp, a01087; ZVFHMIN-NEXT: addi a0, a0, 161088; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload1089; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v01090; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma1091; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v81092; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v161093; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v01094; ZVFHMIN-NEXT: csrr a0, vlenb1095; ZVFHMIN-NEXT: slli a0, a0, 41096; ZVFHMIN-NEXT: add a0, sp, a01097; ZVFHMIN-NEXT: addi a0, a0, 161098; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill1099; ZVFHMIN-NEXT: vmv1r.v v0, v71100; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v01101; ZVFHMIN-NEXT: csrr a0, vlenb1102; ZVFHMIN-NEXT: slli a0, a0, 41103; ZVFHMIN-NEXT: add a0, sp, a01104; ZVFHMIN-NEXT: addi a0, a0, 161105; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1106; ZVFHMIN-NEXT: vfmax.vv v16, v16, v241107; ZVFHMIN-NEXT: addi a0, sp, 161108; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1109; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma1110; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v161111; ZVFHMIN-NEXT: csrr a0, vlenb1112; ZVFHMIN-NEXT: li a1, 241113; ZVFHMIN-NEXT: mul a0, a0, a11114; ZVFHMIN-NEXT: add sp, sp, a01115; ZVFHMIN-NEXT: .cfi_def_cfa sp, 161116; ZVFHMIN-NEXT: addi sp, sp, 161117; ZVFHMIN-NEXT: .cfi_def_cfa_offset 01118; ZVFHMIN-NEXT: ret1119 %v = call <vscale x 32 x half> @llvm.vp.maximum.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)1120 ret <vscale x 32 x half> %v1121}1122 1123define <vscale x 1 x float> @vfmax_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {1124; CHECK-LABEL: vfmax_vv_nxv1f32:1125; CHECK: # %bb.0:1126; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1127; CHECK-NEXT: vmv1r.v v10, v01128; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t1129; CHECK-NEXT: vmerge.vvm v11, v8, v9, v01130; CHECK-NEXT: vmv1r.v v0, v101131; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t1132; CHECK-NEXT: vmerge.vvm v8, v9, v8, v01133; CHECK-NEXT: vmv1r.v v0, v101134; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t1135; CHECK-NEXT: ret1136 %v = call <vscale x 1 x float> @llvm.vp.maximum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)1137 ret <vscale x 1 x float> %v1138}1139 1140define <vscale x 1 x float> @vfmax_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, i32 zeroext %evl) {1141; CHECK-LABEL: vfmax_vv_nxv1f32_unmasked:1142; CHECK: # %bb.0:1143; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1144; CHECK-NEXT: vmfeq.vv v0, v8, v81145; CHECK-NEXT: vmerge.vvm v10, v8, v9, v01146; CHECK-NEXT: vmfeq.vv v0, v9, v91147; CHECK-NEXT: vmerge.vvm v8, v9, v8, v01148; CHECK-NEXT: vfmax.vv v8, v8, v101149; CHECK-NEXT: ret1150 %v = call <vscale x 1 x float> @llvm.vp.maximum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1151 ret <vscale x 1 x float> %v1152}1153 1154define <vscale x 2 x float> @vfmax_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {1155; CHECK-LABEL: vfmax_vv_nxv2f32:1156; CHECK: # %bb.0:1157; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1158; CHECK-NEXT: vmv1r.v v10, v01159; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t1160; CHECK-NEXT: vmerge.vvm v11, v8, v9, v01161; CHECK-NEXT: vmv1r.v v0, v101162; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t1163; CHECK-NEXT: vmerge.vvm v8, v9, v8, v01164; CHECK-NEXT: vmv1r.v v0, v101165; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t1166; CHECK-NEXT: ret1167 %v = call <vscale x 2 x float> @llvm.vp.maximum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)1168 ret <vscale x 2 x float> %v1169}1170 1171define <vscale x 2 x float> @vfmax_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evl) {1172; CHECK-LABEL: vfmax_vv_nxv2f32_unmasked:1173; CHECK: # %bb.0:1174; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1175; CHECK-NEXT: vmfeq.vv v0, v8, v81176; CHECK-NEXT: vmerge.vvm v10, v8, v9, v01177; CHECK-NEXT: vmfeq.vv v0, v9, v91178; CHECK-NEXT: vmerge.vvm v8, v9, v8, v01179; CHECK-NEXT: vfmax.vv v8, v8, v101180; CHECK-NEXT: ret1181 %v = call <vscale x 2 x float> @llvm.vp.maximum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1182 ret <vscale x 2 x float> %v1183}1184 1185define <vscale x 4 x float> @vfmax_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {1186; CHECK-LABEL: vfmax_vv_nxv4f32:1187; CHECK: # %bb.0:1188; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1189; CHECK-NEXT: vmv1r.v v12, v01190; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t1191; CHECK-NEXT: vmv1r.v v0, v131192; CHECK-NEXT: vmerge.vvm v14, v8, v10, v01193; CHECK-NEXT: vmv1r.v v0, v121194; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t1195; CHECK-NEXT: vmv1r.v v0, v131196; CHECK-NEXT: vmerge.vvm v8, v10, v8, v01197; CHECK-NEXT: vmv1r.v v0, v121198; CHECK-NEXT: vfmax.vv v8, v8, v14, v0.t1199; CHECK-NEXT: ret1200 %v = call <vscale x 4 x float> @llvm.vp.maximum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)1201 ret <vscale x 4 x float> %v1202}1203 1204define <vscale x 4 x float> @vfmax_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, i32 zeroext %evl) {1205; CHECK-LABEL: vfmax_vv_nxv4f32_unmasked:1206; CHECK: # %bb.0:1207; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1208; CHECK-NEXT: vmfeq.vv v0, v8, v81209; CHECK-NEXT: vmerge.vvm v12, v8, v10, v01210; CHECK-NEXT: vmfeq.vv v0, v10, v101211; CHECK-NEXT: vmerge.vvm v8, v10, v8, v01212; CHECK-NEXT: vfmax.vv v8, v8, v121213; CHECK-NEXT: ret1214 %v = call <vscale x 4 x float> @llvm.vp.maximum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1215 ret <vscale x 4 x float> %v1216}1217 1218define <vscale x 8 x float> @vfmax_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {1219; CHECK-LABEL: vfmax_vv_nxv8f32:1220; CHECK: # %bb.0:1221; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1222; CHECK-NEXT: vmv1r.v v16, v01223; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t1224; CHECK-NEXT: vmv1r.v v0, v171225; CHECK-NEXT: vmerge.vvm v20, v8, v12, v01226; CHECK-NEXT: vmv1r.v v0, v161227; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t1228; CHECK-NEXT: vmv1r.v v0, v171229; CHECK-NEXT: vmerge.vvm v8, v12, v8, v01230; CHECK-NEXT: vmv1r.v v0, v161231; CHECK-NEXT: vfmax.vv v8, v8, v20, v0.t1232; CHECK-NEXT: ret1233 %v = call <vscale x 8 x float> @llvm.vp.maximum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)1234 ret <vscale x 8 x float> %v1235}1236 1237define <vscale x 8 x float> @vfmax_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, i32 zeroext %evl) {1238; CHECK-LABEL: vfmax_vv_nxv8f32_unmasked:1239; CHECK: # %bb.0:1240; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1241; CHECK-NEXT: vmfeq.vv v0, v8, v81242; CHECK-NEXT: vmerge.vvm v16, v8, v12, v01243; CHECK-NEXT: vmfeq.vv v0, v12, v121244; CHECK-NEXT: vmerge.vvm v8, v12, v8, v01245; CHECK-NEXT: vfmax.vv v8, v8, v161246; CHECK-NEXT: ret1247 %v = call <vscale x 8 x float> @llvm.vp.maximum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1248 ret <vscale x 8 x float> %v1249}1250 1251define <vscale x 1 x double> @vfmax_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {1252; CHECK-LABEL: vfmax_vv_nxv1f64:1253; CHECK: # %bb.0:1254; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1255; CHECK-NEXT: vmv1r.v v10, v01256; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t1257; CHECK-NEXT: vmerge.vvm v11, v8, v9, v01258; CHECK-NEXT: vmv1r.v v0, v101259; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t1260; CHECK-NEXT: vmerge.vvm v8, v9, v8, v01261; CHECK-NEXT: vmv1r.v v0, v101262; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t1263; CHECK-NEXT: ret1264 %v = call <vscale x 1 x double> @llvm.vp.maximum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)1265 ret <vscale x 1 x double> %v1266}1267 1268define <vscale x 1 x double> @vfmax_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evl) {1269; CHECK-LABEL: vfmax_vv_nxv1f64_unmasked:1270; CHECK: # %bb.0:1271; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1272; CHECK-NEXT: vmfeq.vv v0, v8, v81273; CHECK-NEXT: vmerge.vvm v10, v8, v9, v01274; CHECK-NEXT: vmfeq.vv v0, v9, v91275; CHECK-NEXT: vmerge.vvm v8, v9, v8, v01276; CHECK-NEXT: vfmax.vv v8, v8, v101277; CHECK-NEXT: ret1278 %v = call <vscale x 1 x double> @llvm.vp.maximum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1279 ret <vscale x 1 x double> %v1280}1281 1282define <vscale x 2 x double> @vfmax_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {1283; CHECK-LABEL: vfmax_vv_nxv2f64:1284; CHECK: # %bb.0:1285; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1286; CHECK-NEXT: vmv1r.v v12, v01287; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t1288; CHECK-NEXT: vmv1r.v v0, v131289; CHECK-NEXT: vmerge.vvm v14, v8, v10, v01290; CHECK-NEXT: vmv1r.v v0, v121291; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t1292; CHECK-NEXT: vmv1r.v v0, v131293; CHECK-NEXT: vmerge.vvm v8, v10, v8, v01294; CHECK-NEXT: vmv1r.v v0, v121295; CHECK-NEXT: vfmax.vv v8, v8, v14, v0.t1296; CHECK-NEXT: ret1297 %v = call <vscale x 2 x double> @llvm.vp.maximum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)1298 ret <vscale x 2 x double> %v1299}1300 1301define <vscale x 2 x double> @vfmax_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, i32 zeroext %evl) {1302; CHECK-LABEL: vfmax_vv_nxv2f64_unmasked:1303; CHECK: # %bb.0:1304; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1305; CHECK-NEXT: vmfeq.vv v0, v8, v81306; CHECK-NEXT: vmerge.vvm v12, v8, v10, v01307; CHECK-NEXT: vmfeq.vv v0, v10, v101308; CHECK-NEXT: vmerge.vvm v8, v10, v8, v01309; CHECK-NEXT: vfmax.vv v8, v8, v121310; CHECK-NEXT: ret1311 %v = call <vscale x 2 x double> @llvm.vp.maximum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1312 ret <vscale x 2 x double> %v1313}1314 1315define <vscale x 4 x double> @vfmax_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {1316; CHECK-LABEL: vfmax_vv_nxv4f64:1317; CHECK: # %bb.0:1318; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1319; CHECK-NEXT: vmv1r.v v16, v01320; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t1321; CHECK-NEXT: vmv1r.v v0, v171322; CHECK-NEXT: vmerge.vvm v20, v8, v12, v01323; CHECK-NEXT: vmv1r.v v0, v161324; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t1325; CHECK-NEXT: vmv1r.v v0, v171326; CHECK-NEXT: vmerge.vvm v8, v12, v8, v01327; CHECK-NEXT: vmv1r.v v0, v161328; CHECK-NEXT: vfmax.vv v8, v8, v20, v0.t1329; CHECK-NEXT: ret1330 %v = call <vscale x 4 x double> @llvm.vp.maximum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)1331 ret <vscale x 4 x double> %v1332}1333 1334define <vscale x 4 x double> @vfmax_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, i32 zeroext %evl) {1335; CHECK-LABEL: vfmax_vv_nxv4f64_unmasked:1336; CHECK: # %bb.0:1337; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1338; CHECK-NEXT: vmfeq.vv v0, v8, v81339; CHECK-NEXT: vmerge.vvm v16, v8, v12, v01340; CHECK-NEXT: vmfeq.vv v0, v12, v121341; CHECK-NEXT: vmerge.vvm v8, v12, v8, v01342; CHECK-NEXT: vfmax.vv v8, v8, v161343; CHECK-NEXT: ret1344 %v = call <vscale x 4 x double> @llvm.vp.maximum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1345 ret <vscale x 4 x double> %v1346}1347 1348define <vscale x 8 x double> @vfmax_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {1349; CHECK-LABEL: vfmax_vv_nxv8f64:1350; CHECK: # %bb.0:1351; CHECK-NEXT: addi sp, sp, -161352; CHECK-NEXT: .cfi_def_cfa_offset 161353; CHECK-NEXT: csrr a1, vlenb1354; CHECK-NEXT: slli a1, a1, 31355; CHECK-NEXT: sub sp, sp, a11356; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1357; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1358; CHECK-NEXT: vmv1r.v v7, v01359; CHECK-NEXT: vmfeq.vv v25, v8, v8, v0.t1360; CHECK-NEXT: vmv1r.v v0, v251361; CHECK-NEXT: vmerge.vvm v24, v8, v16, v01362; CHECK-NEXT: addi a0, sp, 161363; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill1364; CHECK-NEXT: vmv1r.v v0, v71365; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t1366; CHECK-NEXT: vmv1r.v v0, v251367; CHECK-NEXT: vmerge.vvm v8, v16, v8, v01368; CHECK-NEXT: vmv1r.v v0, v71369; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1370; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t1371; CHECK-NEXT: csrr a0, vlenb1372; CHECK-NEXT: slli a0, a0, 31373; CHECK-NEXT: add sp, sp, a01374; CHECK-NEXT: .cfi_def_cfa sp, 161375; CHECK-NEXT: addi sp, sp, 161376; CHECK-NEXT: .cfi_def_cfa_offset 01377; CHECK-NEXT: ret1378 %v = call <vscale x 8 x double> @llvm.vp.maximum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)1379 ret <vscale x 8 x double> %v1380}1381 1382define <vscale x 8 x double> @vfmax_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, i32 zeroext %evl) {1383; CHECK-LABEL: vfmax_vv_nxv8f64_unmasked:1384; CHECK: # %bb.0:1385; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1386; CHECK-NEXT: vmfeq.vv v0, v8, v81387; CHECK-NEXT: vmfeq.vv v7, v16, v161388; CHECK-NEXT: vmerge.vvm v24, v8, v16, v01389; CHECK-NEXT: vmv1r.v v0, v71390; CHECK-NEXT: vmerge.vvm v8, v16, v8, v01391; CHECK-NEXT: vfmax.vv v8, v8, v241392; CHECK-NEXT: ret1393 %v = call <vscale x 8 x double> @llvm.vp.maximum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1394 ret <vscale x 8 x double> %v1395}1396 1397define <vscale x 16 x double> @vfmax_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x double> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {1398; CHECK-LABEL: vfmax_vv_nxv16f64:1399; CHECK: # %bb.0:1400; CHECK-NEXT: addi sp, sp, -161401; CHECK-NEXT: .cfi_def_cfa_offset 161402; CHECK-NEXT: csrr a1, vlenb1403; CHECK-NEXT: li a3, 241404; CHECK-NEXT: mul a1, a1, a31405; CHECK-NEXT: sub sp, sp, a11406; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1407; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1408; CHECK-NEXT: vmv1r.v v7, v01409; CHECK-NEXT: csrr a1, vlenb1410; CHECK-NEXT: slli a1, a1, 41411; CHECK-NEXT: add a1, sp, a11412; CHECK-NEXT: addi a1, a1, 161413; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1414; CHECK-NEXT: csrr a1, vlenb1415; CHECK-NEXT: slli a3, a1, 31416; CHECK-NEXT: srli a4, a1, 31417; CHECK-NEXT: vslidedown.vx v6, v0, a41418; CHECK-NEXT: sub a4, a2, a11419; CHECK-NEXT: add a3, a0, a31420; CHECK-NEXT: vl8re64.v v8, (a3)1421; CHECK-NEXT: sltu a3, a2, a41422; CHECK-NEXT: addi a3, a3, -11423; CHECK-NEXT: and a3, a3, a41424; CHECK-NEXT: vmv1r.v v0, v61425; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma1426; CHECK-NEXT: vmfeq.vv v26, v16, v16, v0.t1427; CHECK-NEXT: vmv1r.v v0, v261428; CHECK-NEXT: vmerge.vvm v24, v16, v8, v01429; CHECK-NEXT: csrr a3, vlenb1430; CHECK-NEXT: slli a3, a3, 31431; CHECK-NEXT: add a3, sp, a31432; CHECK-NEXT: addi a3, a3, 161433; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill1434; CHECK-NEXT: vmv8r.v v24, v161435; CHECK-NEXT: vmv1r.v v0, v61436; CHECK-NEXT: vmfeq.vv v5, v8, v8, v0.t1437; CHECK-NEXT: vl8re64.v v16, (a0)1438; CHECK-NEXT: vmv1r.v v0, v51439; CHECK-NEXT: vmerge.vvm v8, v8, v24, v01440; CHECK-NEXT: vmv1r.v v0, v61441; CHECK-NEXT: csrr a0, vlenb1442; CHECK-NEXT: slli a0, a0, 31443; CHECK-NEXT: add a0, sp, a01444; CHECK-NEXT: addi a0, a0, 161445; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1446; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t1447; CHECK-NEXT: csrr a0, vlenb1448; CHECK-NEXT: slli a0, a0, 31449; CHECK-NEXT: add a0, sp, a01450; CHECK-NEXT: addi a0, a0, 161451; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1452; CHECK-NEXT: bltu a2, a1, .LBB40_21453; CHECK-NEXT: # %bb.1:1454; CHECK-NEXT: mv a2, a11455; CHECK-NEXT: .LBB40_2:1456; CHECK-NEXT: vmv1r.v v0, v71457; CHECK-NEXT: csrr a0, vlenb1458; CHECK-NEXT: slli a0, a0, 41459; CHECK-NEXT: add a0, sp, a01460; CHECK-NEXT: addi a0, a0, 161461; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1462; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma1463; CHECK-NEXT: vmfeq.vv v25, v8, v8, v0.t1464; CHECK-NEXT: vmv1r.v v0, v251465; CHECK-NEXT: vmerge.vvm v24, v8, v16, v01466; CHECK-NEXT: addi a0, sp, 161467; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill1468; CHECK-NEXT: vmv1r.v v0, v71469; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t1470; CHECK-NEXT: vmv1r.v v0, v251471; CHECK-NEXT: vmerge.vvm v16, v16, v8, v01472; CHECK-NEXT: vmv1r.v v0, v71473; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1474; CHECK-NEXT: vfmax.vv v8, v16, v8, v0.t1475; CHECK-NEXT: csrr a0, vlenb1476; CHECK-NEXT: slli a0, a0, 31477; CHECK-NEXT: add a0, sp, a01478; CHECK-NEXT: addi a0, a0, 161479; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1480; CHECK-NEXT: csrr a0, vlenb1481; CHECK-NEXT: li a1, 241482; CHECK-NEXT: mul a0, a0, a11483; CHECK-NEXT: add sp, sp, a01484; CHECK-NEXT: .cfi_def_cfa sp, 161485; CHECK-NEXT: addi sp, sp, 161486; CHECK-NEXT: .cfi_def_cfa_offset 01487; CHECK-NEXT: ret1488 %v = call <vscale x 16 x double> @llvm.vp.maximum.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x double> %vb, <vscale x 16 x i1> %m, i32 %evl)1489 ret <vscale x 16 x double> %v1490}1491 1492define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, <vscale x 16 x double> %vb, i32 zeroext %evl) {1493; CHECK-LABEL: vfmax_vv_nxv16f64_unmasked:1494; CHECK: # %bb.0:1495; CHECK-NEXT: addi sp, sp, -161496; CHECK-NEXT: .cfi_def_cfa_offset 161497; CHECK-NEXT: csrr a1, vlenb1498; CHECK-NEXT: li a3, 241499; CHECK-NEXT: mul a1, a1, a31500; CHECK-NEXT: sub sp, sp, a11501; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1502; CHECK-NEXT: csrr a1, vlenb1503; CHECK-NEXT: slli a1, a1, 41504; CHECK-NEXT: add a1, sp, a11505; CHECK-NEXT: addi a1, a1, 161506; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1507; CHECK-NEXT: csrr a1, vlenb1508; CHECK-NEXT: slli a3, a1, 31509; CHECK-NEXT: sub a4, a2, a11510; CHECK-NEXT: add a3, a0, a31511; CHECK-NEXT: vl8re64.v v24, (a3)1512; CHECK-NEXT: sltu a3, a2, a41513; CHECK-NEXT: addi a3, a3, -11514; CHECK-NEXT: and a3, a3, a41515; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma1516; CHECK-NEXT: vmfeq.vv v0, v16, v161517; CHECK-NEXT: vmfeq.vv v7, v24, v241518; CHECK-NEXT: vl8re64.v v8, (a0)1519; CHECK-NEXT: csrr a0, vlenb1520; CHECK-NEXT: slli a0, a0, 31521; CHECK-NEXT: add a0, sp, a01522; CHECK-NEXT: addi a0, a0, 161523; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1524; CHECK-NEXT: vmerge.vvm v8, v16, v24, v01525; CHECK-NEXT: vmv1r.v v0, v71526; CHECK-NEXT: vmerge.vvm v16, v24, v16, v01527; CHECK-NEXT: vfmax.vv v8, v16, v81528; CHECK-NEXT: addi a0, sp, 161529; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1530; CHECK-NEXT: bltu a2, a1, .LBB41_21531; CHECK-NEXT: # %bb.1:1532; CHECK-NEXT: mv a2, a11533; CHECK-NEXT: .LBB41_2:1534; CHECK-NEXT: csrr a0, vlenb1535; CHECK-NEXT: slli a0, a0, 41536; CHECK-NEXT: add a0, sp, a01537; CHECK-NEXT: addi a0, a0, 161538; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1539; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma1540; CHECK-NEXT: vmfeq.vv v0, v16, v161541; CHECK-NEXT: csrr a0, vlenb1542; CHECK-NEXT: slli a0, a0, 31543; CHECK-NEXT: add a0, sp, a01544; CHECK-NEXT: addi a0, a0, 161545; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1546; CHECK-NEXT: vmfeq.vv v7, v8, v81547; CHECK-NEXT: vmerge.vvm v24, v16, v8, v01548; CHECK-NEXT: vmv1r.v v0, v71549; CHECK-NEXT: vmerge.vvm v8, v8, v16, v01550; CHECK-NEXT: vfmax.vv v8, v8, v241551; CHECK-NEXT: addi a0, sp, 161552; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1553; CHECK-NEXT: csrr a0, vlenb1554; CHECK-NEXT: li a1, 241555; CHECK-NEXT: mul a0, a0, a11556; CHECK-NEXT: add sp, sp, a01557; CHECK-NEXT: .cfi_def_cfa sp, 161558; CHECK-NEXT: addi sp, sp, 161559; CHECK-NEXT: .cfi_def_cfa_offset 01560; CHECK-NEXT: ret1561 %v = call <vscale x 16 x double> @llvm.vp.maximum.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x double> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1562 ret <vscale x 16 x double> %v1563}1564