422 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zbb -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s3 4define i64 @reduce_add(i64 %x, <4 x i64> %v) {5; CHECK-LABEL: reduce_add:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma8; CHECK-NEXT: vmv.s.x v10, a09; CHECK-NEXT: vredsum.vs v8, v8, v1010; CHECK-NEXT: vmv.x.s a0, v811; CHECK-NEXT: ret12entry:13 %rdx = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)14 %res = add i64 %rdx, %x15 ret i64 %res16}17 18define i64 @reduce_add2(<4 x i64> %v) {19; CHECK-LABEL: reduce_add2:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma22; CHECK-NEXT: vmv.v.i v10, 823; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma24; CHECK-NEXT: vredsum.vs v8, v8, v1025; CHECK-NEXT: vmv.x.s a0, v826; CHECK-NEXT: ret27entry:28 %rdx = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)29 %res = add i64 %rdx, 830 ret i64 %res31}32 33define i64 @reduce_and(i64 %x, <4 x i64> %v) {34; CHECK-LABEL: reduce_and:35; CHECK: # %bb.0: # %entry36; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma37; CHECK-NEXT: vredand.vs v8, v8, v838; CHECK-NEXT: vmv.x.s a1, v839; CHECK-NEXT: and a0, a1, a040; CHECK-NEXT: ret41entry:42 %rdx = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)43 %res = and i64 %rdx, %x44 ret i64 %res45}46 47define i64 @reduce_and2(<4 x i64> %v) {48; CHECK-LABEL: reduce_and2:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma51; CHECK-NEXT: vredand.vs v8, v8, v852; CHECK-NEXT: vmv.x.s a0, v853; CHECK-NEXT: andi a0, a0, 854; CHECK-NEXT: ret55entry:56 %rdx = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)57 %res = and i64 %rdx, 858 ret i64 %res59}60 61define i64 @reduce_or(i64 %x, <4 x i64> %v) {62; CHECK-LABEL: reduce_or:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma65; CHECK-NEXT: vredor.vs v8, v8, v866; CHECK-NEXT: vmv.x.s a1, v867; CHECK-NEXT: or a0, a1, a068; CHECK-NEXT: ret69entry:70 %rdx = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)71 %res = or i64 %rdx, %x72 ret i64 %res73}74 75define i64 @reduce_or2(<4 x i64> %v) {76; CHECK-LABEL: reduce_or2:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma79; CHECK-NEXT: vredor.vs v8, v8, v880; CHECK-NEXT: vmv.x.s a0, v881; CHECK-NEXT: ori a0, a0, 882; CHECK-NEXT: ret83entry:84 %rdx = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)85 %res = or i64 %rdx, 886 ret i64 %res87}88 89define i64 @reduce_xor(i64 %x, <4 x i64> %v) {90; CHECK-LABEL: reduce_xor:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma93; CHECK-NEXT: vmv.s.x v10, a094; CHECK-NEXT: vredxor.vs v8, v8, v1095; CHECK-NEXT: vmv.x.s a0, v896; CHECK-NEXT: ret97entry:98 %rdx = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)99 %res = xor i64 %rdx, %x100 ret i64 %res101}102 103define i64 @reduce_xor2(<4 x i64> %v) {104; CHECK-LABEL: reduce_xor2:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma107; CHECK-NEXT: vmv.s.x v10, zero108; CHECK-NEXT: vredxor.vs v8, v8, v10109; CHECK-NEXT: vmv.x.s a0, v8110; CHECK-NEXT: andi a0, a0, 8111; CHECK-NEXT: ret112entry:113 %rdx = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)114 %res = and i64 %rdx, 8115 ret i64 %res116}117 118define i64 @reduce_umax(i64 %x, <4 x i64> %v) {119; CHECK-LABEL: reduce_umax:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma122; CHECK-NEXT: vredmaxu.vs v8, v8, v8123; CHECK-NEXT: vmv.x.s a1, v8124; CHECK-NEXT: maxu a0, a1, a0125; CHECK-NEXT: ret126entry:127 %rdx = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)128 %res = call i64 @llvm.umax.i64(i64 %rdx, i64 %x)129 ret i64 %res130}131 132define i64 @reduce_umax2(<4 x i64> %v) {133; CHECK-LABEL: reduce_umax2:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma136; CHECK-NEXT: vredmaxu.vs v8, v8, v8137; CHECK-NEXT: vmv.x.s a0, v8138; CHECK-NEXT: li a1, 8139; CHECK-NEXT: maxu a0, a0, a1140; CHECK-NEXT: ret141entry:142 %rdx = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)143 %res = call i64 @llvm.umax.i64(i64 %rdx, i64 8)144 ret i64 %res145}146 147define i64 @reduce_umin(i64 %x, <4 x i64> %v) {148; CHECK-LABEL: reduce_umin:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma151; CHECK-NEXT: vredminu.vs v8, v8, v8152; CHECK-NEXT: vmv.x.s a1, v8153; CHECK-NEXT: minu a0, a1, a0154; CHECK-NEXT: ret155entry:156 %rdx = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)157 %res = call i64 @llvm.umin.i64(i64 %rdx, i64 %x)158 ret i64 %res159}160 161define i64 @reduce_umin2(<4 x i64> %v) {162; CHECK-LABEL: reduce_umin2:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma165; CHECK-NEXT: vredminu.vs v8, v8, v8166; CHECK-NEXT: vmv.x.s a0, v8167; CHECK-NEXT: li a1, 8168; CHECK-NEXT: minu a0, a0, a1169; CHECK-NEXT: ret170entry:171 %rdx = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)172 %res = call i64 @llvm.umin.i64(i64 %rdx, i64 8)173 ret i64 %res174}175 176define i64 @reduce_smax(i64 %x, <4 x i64> %v) {177; CHECK-LABEL: reduce_smax:178; CHECK: # %bb.0: # %entry179; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma180; CHECK-NEXT: vredmax.vs v8, v8, v8181; CHECK-NEXT: vmv.x.s a1, v8182; CHECK-NEXT: max a0, a1, a0183; CHECK-NEXT: ret184entry:185 %rdx = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)186 %res = call i64 @llvm.smax.i64(i64 %rdx, i64 %x)187 ret i64 %res188}189 190define i64 @reduce_smax2(<4 x i64> %v) {191; CHECK-LABEL: reduce_smax2:192; CHECK: # %bb.0: # %entry193; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma194; CHECK-NEXT: vredmax.vs v8, v8, v8195; CHECK-NEXT: vmv.x.s a0, v8196; CHECK-NEXT: li a1, 8197; CHECK-NEXT: max a0, a0, a1198; CHECK-NEXT: ret199entry:200 %rdx = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)201 %res = call i64 @llvm.smax.i64(i64 %rdx, i64 8)202 ret i64 %res203}204 205define i64 @reduce_smin(i64 %x, <4 x i64> %v) {206; CHECK-LABEL: reduce_smin:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma209; CHECK-NEXT: vredmin.vs v8, v8, v8210; CHECK-NEXT: vmv.x.s a1, v8211; CHECK-NEXT: min a0, a1, a0212; CHECK-NEXT: ret213entry:214 %rdx = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)215 %res = call i64 @llvm.smin.i64(i64 %rdx, i64 %x)216 ret i64 %res217}218 219define i64 @reduce_smin2(<4 x i64> %v) {220; CHECK-LABEL: reduce_smin2:221; CHECK: # %bb.0: # %entry222; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma223; CHECK-NEXT: vredmin.vs v8, v8, v8224; CHECK-NEXT: vmv.x.s a0, v8225; CHECK-NEXT: li a1, 8226; CHECK-NEXT: min a0, a0, a1227; CHECK-NEXT: ret228entry:229 %rdx = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)230 %res = call i64 @llvm.smin.i64(i64 %rdx, i64 8)231 ret i64 %res232}233 234define float @reduce_fadd(float %x, <4 x float> %v) {235; CHECK-LABEL: reduce_fadd:236; CHECK: # %bb.0: # %entry237; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma238; CHECK-NEXT: vfmv.s.f v9, fa0239; CHECK-NEXT: vfredusum.vs v8, v8, v9240; CHECK-NEXT: vfmv.f.s fa0, v8241; CHECK-NEXT: ret242entry:243 %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float %x, <4 x float> %v)244 ret float %rdx245}246 247define float @reduce_fadd2(float %x, <4 x float> %v) {248; CHECK-LABEL: reduce_fadd2:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma251; CHECK-NEXT: vfmv.s.f v9, fa0252; CHECK-NEXT: vfredusum.vs v8, v8, v9253; CHECK-NEXT: vfmv.f.s fa0, v8254; CHECK-NEXT: ret255entry:256 %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.0, <4 x float> %v)257 %res = fadd fast float %rdx, %x258 ret float %res259}260 261define float @reduce_fadd3(float %x, <4 x float> %v, ptr %rdxptr) {262; CHECK-LABEL: reduce_fadd3:263; CHECK: # %bb.0: # %entry264; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma265; CHECK-NEXT: vmv.s.x v9, zero266; CHECK-NEXT: vfredusum.vs v8, v8, v9267; CHECK-NEXT: vfmv.f.s fa5, v8268; CHECK-NEXT: fadd.s fa0, fa5, fa0269; CHECK-NEXT: fsw fa5, 0(a0)270; CHECK-NEXT: ret271entry:272 %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.0, <4 x float> %v)273 %res = fadd fast float %rdx, %x274 store float %rdx, ptr %rdxptr275 ret float %res276}277 278define float @reduce_fadd4(float %x, float %y, <4 x float> %v, <4 x float> %w) {279; CHECK-LABEL: reduce_fadd4:280; CHECK: # %bb.0: # %entry281; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma282; CHECK-NEXT: vfmv.s.f v10, fa0283; CHECK-NEXT: vfredusum.vs v8, v8, v10284; CHECK-NEXT: vfmv.s.f v10, fa1285; CHECK-NEXT: vfredusum.vs v9, v9, v10286; CHECK-NEXT: vfmv.f.s fa5, v8287; CHECK-NEXT: vfmv.f.s fa4, v9288; CHECK-NEXT: fdiv.s fa0, fa5, fa4289; CHECK-NEXT: ret290entry:291 %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.0, <4 x float> %v)292 %rdx2 = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.0, <4 x float> %w)293 %res = fadd fast float %rdx, %x294 %res2 = fadd fast float %rdx2, %y295 %div = fdiv fast float %res, %res2296 ret float %div297}298 299define float @reduce_fmax(float %x, <4 x float> %v) {300; CHECK-LABEL: reduce_fmax:301; CHECK: # %bb.0: # %entry302; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma303; CHECK-NEXT: vfredmax.vs v8, v8, v8304; CHECK-NEXT: vfmv.f.s fa5, v8305; CHECK-NEXT: fmax.s fa0, fa0, fa5306; CHECK-NEXT: ret307entry:308 %rdx = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)309 %res = call float @llvm.maxnum.f32(float %x, float %rdx)310 ret float %res311}312 313define float @reduce_fmin(float %x, <4 x float> %v) {314; CHECK-LABEL: reduce_fmin:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma317; CHECK-NEXT: vfredmin.vs v8, v8, v8318; CHECK-NEXT: vfmv.f.s fa5, v8319; CHECK-NEXT: fmin.s fa0, fa0, fa5320; CHECK-NEXT: ret321entry:322 %rdx = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)323 %res = call float @llvm.minnum.f32(float %x, float %rdx)324 ret float %res325}326 327define void @crash(<2 x i32> %0) {328; CHECK-LABEL: crash:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma331; CHECK-NEXT: vmv.x.s a0, v8332; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma333; CHECK-NEXT: vmv.v.i v8, 0334; CHECK-NEXT: vmv.s.x v9, a0335; CHECK-NEXT: vredsum.vs v8, v8, v9336; CHECK-NEXT: vmv.x.s a0, v8337; CHECK-NEXT: sb a0, 0(zero)338; CHECK-NEXT: ret339entry:340 %1 = extractelement <2 x i32> %0, i64 0341 %2 = tail call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> zeroinitializer)342 %3 = zext i16 %2 to i32343 %op.rdx = add i32 %1, %3344 %conv18.us = trunc i32 %op.rdx to i8345 store i8 %conv18.us, ptr null, align 1346 ret void347}348 349define i64 @op_then_reduce(<4 x i64> %v, <4 x i64> %v2) {350; CHECK-LABEL: op_then_reduce:351; CHECK: # %bb.0: # %entry352; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma353; CHECK-NEXT: vadd.vv v8, v8, v10354; CHECK-NEXT: vmv.s.x v10, zero355; CHECK-NEXT: vredsum.vs v8, v8, v10356; CHECK-NEXT: vmv.x.s a0, v8357; CHECK-NEXT: ret358entry:359 %rdx1 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)360 %rdx2 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v2)361 %res = add i64 %rdx1, %rdx2362 ret i64 %res363}364 365define i64 @two_reduce_scalar_bypass(<4 x i64> %v, <4 x i64> %v2) {366; CHECK-LABEL: two_reduce_scalar_bypass:367; CHECK: # %bb.0: # %entry368; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma369; CHECK-NEXT: vmv.s.x v12, zero370; CHECK-NEXT: vredxor.vs v8, v8, v12371; CHECK-NEXT: vredsum.vs v8, v10, v8372; CHECK-NEXT: vmv.x.s a0, v8373; CHECK-NEXT: ret374entry:375 %rdx1 = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)376 %rdx2 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v2)377 %res = add i64 %rdx1, %rdx2378 ret i64 %res379}380 381define i64 @two_reduce_scalar_bypass_zext(<4 x i64> %v, <4 x i32> %v2) {382; CHECK-LABEL: two_reduce_scalar_bypass_zext:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma385; CHECK-NEXT: vmv.s.x v11, zero386; CHECK-NEXT: vredsum.vs v10, v10, v11387; CHECK-NEXT: vmv.x.s a0, v10388; CHECK-NEXT: slli a0, a0, 32389; CHECK-NEXT: srli a0, a0, 32390; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma391; CHECK-NEXT: vmv.s.x v10, a0392; CHECK-NEXT: vredsum.vs v8, v8, v10393; CHECK-NEXT: vmv.x.s a0, v8394; CHECK-NEXT: ret395entry:396 %rdx1 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)397 %rdx2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v2)398 %rdx2.zext = zext i32 %rdx2 to i64399 %res = add i64 %rdx1, %rdx2.zext400 ret i64 %res401}402 403define i64 @two_reduce_scalar_bypass_sext(<4 x i64> %v, <4 x i32> %v2) {404; CHECK-LABEL: two_reduce_scalar_bypass_sext:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma407; CHECK-NEXT: vmv.s.x v11, zero408; CHECK-NEXT: vredsum.vs v10, v10, v11409; CHECK-NEXT: vmv.x.s a0, v10410; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma411; CHECK-NEXT: vmv.s.x v10, a0412; CHECK-NEXT: vredsum.vs v8, v8, v10413; CHECK-NEXT: vmv.x.s a0, v8414; CHECK-NEXT: ret415entry:416 %rdx1 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)417 %rdx2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v2)418 %rdx2.zext = sext i32 %rdx2 to i64419 %res = add i64 %rdx1, %rdx2.zext420 ret i64 %res421}422