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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5; The following binop x, (zext i1) tests will be vector-legalized into a vselect6; of two splat_vectors, but on RV64 the splat value will be implicitly7; truncated:8;9; t15: nxv2i32 = splat_vector Constant:i64<1>10; t13: nxv2i32 = splat_vector Constant:i64<0>11; t16: nxv2i32 = vselect t2, t15, t1312; t7: nxv2i32 = add t4, t1613;14; Make sure that foldSelectWithIdentityConstant in DAGCombiner.cpp handles the15; truncating splat, so we pull the vselect back and fold it into a mask.16 17define <vscale x 2 x i32> @i1_zext_add(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {18; CHECK-LABEL: i1_zext_add:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu21; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t22; CHECK-NEXT: ret23 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>24 %add = add <vscale x 2 x i32> %b, %zext25 ret <vscale x 2 x i32> %add26}27 28define <vscale x 2 x i32> @i1_zext_add_commuted(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {29; CHECK-LABEL: i1_zext_add_commuted:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu32; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t33; CHECK-NEXT: ret34 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>35 %add = add <vscale x 2 x i32> %zext, %b36 ret <vscale x 2 x i32> %add37}38 39define <vscale x 2 x i32> @i1_zext_sub(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {40; CHECK-LABEL: i1_zext_sub:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu43; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t44; CHECK-NEXT: ret45 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>46 %sub = sub <vscale x 2 x i32> %b, %zext47 ret <vscale x 2 x i32> %sub48}49 50define <vscale x 2 x i32> @i1_zext_or(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {51; CHECK-LABEL: i1_zext_or:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu54; CHECK-NEXT: vor.vi v8, v8, 1, v0.t55; CHECK-NEXT: ret56 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>57 %or = or <vscale x 2 x i32> %b, %zext58 ret <vscale x 2 x i32> %or59}60