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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s3 4; (fsub (fmul x, y), z)) -> (fma x, y, (fneg z))5define <vscale x 1 x double> @test1(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 zeroext %vl) {6; CHECK-LABEL: test1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma9; CHECK-NEXT: vfmsub.vv v9, v8, v10, v0.t10; CHECK-NEXT: vmv.v.v v8, v911; CHECK-NEXT: ret12 %1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)13 %2 = call fast <vscale x 1 x double> @llvm.vp.fsub.nxv1f64(<vscale x 1 x double> %1, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 %vl)14 ret <vscale x 1 x double> %215}16 17; (fsub z, (fmul x, y))) -> (fma (fneg y), x, z)18define <vscale x 1 x double> @test2(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 zeroext %vl) {19; CHECK-LABEL: test2:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma22; CHECK-NEXT: vfnmsub.vv v9, v8, v10, v0.t23; CHECK-NEXT: vmv.v.v v8, v924; CHECK-NEXT: ret25 %1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)26 %2 = call fast <vscale x 1 x double> @llvm.vp.fsub.nxv1f64(<vscale x 1 x double> %z, <vscale x 1 x double> %1, <vscale x 1 x i1> %m, i32 %vl)27 ret <vscale x 1 x double> %228}29 30; (fsub (fneg (fmul x, y))), z) -> (fma (fneg x), y, (fneg z))31define <vscale x 1 x double> @test3(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 zeroext %vl) {32; CHECK-LABEL: test3:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma35; CHECK-NEXT: vfmsub.vv v9, v8, v10, v0.t36; CHECK-NEXT: vmv.v.v v8, v937; CHECK-NEXT: ret38 %1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)39 %2 = call fast <vscale x 1 x double> @llvm.vp.fneg.nxv1f64(<vscale x 1 x double> %1, <vscale x 1 x i1> %m, i32 %vl)40 %3 = call fast <vscale x 1 x double> @llvm.vp.fsub.nxv1f64(<vscale x 1 x double> %1, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 %vl)41 ret <vscale x 1 x double> %342}43