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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s3 4; This test makes sure we match FrameIndex into the base address.5; Done as a MIR test because eliminateFrameIndex will likely turn it6; back into an addi.7 8define i64 @test(<vscale x 1 x i64> %0) nounwind {9 ; CHECK-LABEL: name: test10 ; CHECK: bb.0.entry:11 ; CHECK-NEXT: liveins: $v812 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v814 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.a, 015 ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], killed [[ADDI]], 1, 6 /* e64 */16 ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a)17 ; CHECK-NEXT: $x10 = COPY [[LD]]18 ; CHECK-NEXT: PseudoRET implicit $x1019entry:20 %a = alloca i6421 %b = bitcast ptr %a to ptr22 call void @llvm.riscv.vse.nxv1i64(23 <vscale x 1 x i64> %0,24 ptr %b,25 i64 1)26 %c = load i64, ptr %a27 ret i64 %c28}29