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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN14 15define <vscale x 1 x bfloat> @rint_nxv1bf16(<vscale x 1 x bfloat> %x) {16; CHECK-LABEL: rint_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma19; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v820; CHECK-NEXT: lui a0, 30720021; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma22; CHECK-NEXT: vfabs.v v8, v923; CHECK-NEXT: fmv.w.x fa5, a024; CHECK-NEXT: vmflt.vf v0, v8, fa525; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t26; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t27; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu28; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t29; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma30; CHECK-NEXT: vfncvtbf16.f.f.w v8, v931; CHECK-NEXT: ret32 %a = call <vscale x 1 x bfloat> @llvm.rint.nxv1bf16(<vscale x 1 x bfloat> %x)33 ret <vscale x 1 x bfloat> %a34}35 36define <vscale x 2 x bfloat> @rint_nxv2bf16(<vscale x 2 x bfloat> %x) {37; CHECK-LABEL: rint_nxv2bf16:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma40; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v841; CHECK-NEXT: lui a0, 30720042; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma43; CHECK-NEXT: vfabs.v v8, v944; CHECK-NEXT: fmv.w.x fa5, a045; CHECK-NEXT: vmflt.vf v0, v8, fa546; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t47; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t48; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu49; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t50; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma51; CHECK-NEXT: vfncvtbf16.f.f.w v8, v952; CHECK-NEXT: ret53 %a = call <vscale x 2 x bfloat> @llvm.rint.nxv2bf16(<vscale x 2 x bfloat> %x)54 ret <vscale x 2 x bfloat> %a55}56 57define <vscale x 4 x bfloat> @rint_nxv4bf16(<vscale x 4 x bfloat> %x) {58; CHECK-LABEL: rint_nxv4bf16:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma61; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v862; CHECK-NEXT: lui a0, 30720063; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma64; CHECK-NEXT: vfabs.v v8, v1065; CHECK-NEXT: fmv.w.x fa5, a066; CHECK-NEXT: vmflt.vf v0, v8, fa567; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t68; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t69; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu70; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t71; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma72; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1073; CHECK-NEXT: ret74 %a = call <vscale x 4 x bfloat> @llvm.rint.nxv4bf16(<vscale x 4 x bfloat> %x)75 ret <vscale x 4 x bfloat> %a76}77 78define <vscale x 8 x bfloat> @rint_nxv8bf16(<vscale x 8 x bfloat> %x) {79; CHECK-LABEL: rint_nxv8bf16:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma82; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v883; CHECK-NEXT: lui a0, 30720084; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma85; CHECK-NEXT: vfabs.v v8, v1286; CHECK-NEXT: fmv.w.x fa5, a087; CHECK-NEXT: vmflt.vf v0, v8, fa588; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t89; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t90; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu91; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t92; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma93; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1294; CHECK-NEXT: ret95 %a = call <vscale x 8 x bfloat> @llvm.rint.nxv8bf16(<vscale x 8 x bfloat> %x)96 ret <vscale x 8 x bfloat> %a97}98 99define <vscale x 16 x bfloat> @rint_nxv16bf16(<vscale x 16 x bfloat> %x) {100; CHECK-LABEL: rint_nxv16bf16:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma103; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8104; CHECK-NEXT: lui a0, 307200105; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma106; CHECK-NEXT: vfabs.v v8, v16107; CHECK-NEXT: fmv.w.x fa5, a0108; CHECK-NEXT: vmflt.vf v0, v8, fa5109; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t110; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t111; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu112; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t113; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma114; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16115; CHECK-NEXT: ret116 %a = call <vscale x 16 x bfloat> @llvm.rint.nxv16bf16(<vscale x 16 x bfloat> %x)117 ret <vscale x 16 x bfloat> %a118}119 120define <vscale x 32 x bfloat> @rint_nxv32bf16(<vscale x 32 x bfloat> %x) {121; CHECK-LABEL: rint_nxv32bf16:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma124; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8125; CHECK-NEXT: lui a0, 307200126; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma127; CHECK-NEXT: vfabs.v v24, v16128; CHECK-NEXT: fmv.w.x fa5, a0129; CHECK-NEXT: vmflt.vf v0, v24, fa5130; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t131; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t132; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu133; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t134; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma135; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12136; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma137; CHECK-NEXT: vfabs.v v8, v24138; CHECK-NEXT: vmflt.vf v0, v8, fa5139; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma140; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16141; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma142; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t143; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t144; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu145; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t146; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma147; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24148; CHECK-NEXT: ret149 %a = call <vscale x 32 x bfloat> @llvm.rint.nxv32bf16(<vscale x 32 x bfloat> %x)150 ret <vscale x 32 x bfloat> %a151}152 153define <vscale x 1 x half> @rint_nxv1f16(<vscale x 1 x half> %x) {154; ZVFH-LABEL: rint_nxv1f16:155; ZVFH: # %bb.0:156; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma157; ZVFH-NEXT: vfabs.v v9, v8158; ZVFH-NEXT: li a0, 25159; ZVFH-NEXT: slli a0, a0, 10160; ZVFH-NEXT: fmv.h.x fa5, a0161; ZVFH-NEXT: vmflt.vf v0, v9, fa5162; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t163; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t164; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu165; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t166; ZVFH-NEXT: ret167;168; ZVFHMIN-LABEL: rint_nxv1f16:169; ZVFHMIN: # %bb.0:170; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma171; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8172; ZVFHMIN-NEXT: lui a0, 307200173; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma174; ZVFHMIN-NEXT: vfabs.v v8, v9175; ZVFHMIN-NEXT: fmv.w.x fa5, a0176; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5177; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t178; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t179; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu180; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t181; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma182; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9183; ZVFHMIN-NEXT: ret184 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)185 ret <vscale x 1 x half> %a186}187 188define <vscale x 2 x half> @rint_nxv2f16(<vscale x 2 x half> %x) {189; ZVFH-LABEL: rint_nxv2f16:190; ZVFH: # %bb.0:191; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma192; ZVFH-NEXT: vfabs.v v9, v8193; ZVFH-NEXT: li a0, 25194; ZVFH-NEXT: slli a0, a0, 10195; ZVFH-NEXT: fmv.h.x fa5, a0196; ZVFH-NEXT: vmflt.vf v0, v9, fa5197; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t198; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t199; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu200; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t201; ZVFH-NEXT: ret202;203; ZVFHMIN-LABEL: rint_nxv2f16:204; ZVFHMIN: # %bb.0:205; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma206; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8207; ZVFHMIN-NEXT: lui a0, 307200208; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma209; ZVFHMIN-NEXT: vfabs.v v8, v9210; ZVFHMIN-NEXT: fmv.w.x fa5, a0211; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5212; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t213; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t214; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu215; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t216; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma217; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9218; ZVFHMIN-NEXT: ret219 %a = call <vscale x 2 x half> @llvm.rint.nxv2f16(<vscale x 2 x half> %x)220 ret <vscale x 2 x half> %a221}222 223define <vscale x 4 x half> @rint_nxv4f16(<vscale x 4 x half> %x) {224; ZVFH-LABEL: rint_nxv4f16:225; ZVFH: # %bb.0:226; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma227; ZVFH-NEXT: vfabs.v v9, v8228; ZVFH-NEXT: li a0, 25229; ZVFH-NEXT: slli a0, a0, 10230; ZVFH-NEXT: fmv.h.x fa5, a0231; ZVFH-NEXT: vmflt.vf v0, v9, fa5232; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t233; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t234; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu235; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t236; ZVFH-NEXT: ret237;238; ZVFHMIN-LABEL: rint_nxv4f16:239; ZVFHMIN: # %bb.0:240; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma241; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8242; ZVFHMIN-NEXT: lui a0, 307200243; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma244; ZVFHMIN-NEXT: vfabs.v v8, v10245; ZVFHMIN-NEXT: fmv.w.x fa5, a0246; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5247; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t248; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t249; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu250; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t251; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma252; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10253; ZVFHMIN-NEXT: ret254 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)255 ret <vscale x 4 x half> %a256}257 258define <vscale x 8 x half> @rint_nxv8f16(<vscale x 8 x half> %x) {259; ZVFH-LABEL: rint_nxv8f16:260; ZVFH: # %bb.0:261; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma262; ZVFH-NEXT: vfabs.v v10, v8263; ZVFH-NEXT: li a0, 25264; ZVFH-NEXT: slli a0, a0, 10265; ZVFH-NEXT: fmv.h.x fa5, a0266; ZVFH-NEXT: vmflt.vf v0, v10, fa5267; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t268; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t269; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu270; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t271; ZVFH-NEXT: ret272;273; ZVFHMIN-LABEL: rint_nxv8f16:274; ZVFHMIN: # %bb.0:275; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma276; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8277; ZVFHMIN-NEXT: lui a0, 307200278; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma279; ZVFHMIN-NEXT: vfabs.v v8, v12280; ZVFHMIN-NEXT: fmv.w.x fa5, a0281; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5282; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t283; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t284; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu285; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t286; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma287; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12288; ZVFHMIN-NEXT: ret289 %a = call <vscale x 8 x half> @llvm.rint.nxv8f16(<vscale x 8 x half> %x)290 ret <vscale x 8 x half> %a291}292 293define <vscale x 16 x half> @rint_nxv16f16(<vscale x 16 x half> %x) {294; ZVFH-LABEL: rint_nxv16f16:295; ZVFH: # %bb.0:296; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma297; ZVFH-NEXT: vfabs.v v12, v8298; ZVFH-NEXT: li a0, 25299; ZVFH-NEXT: slli a0, a0, 10300; ZVFH-NEXT: fmv.h.x fa5, a0301; ZVFH-NEXT: vmflt.vf v0, v12, fa5302; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t303; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t304; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu305; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t306; ZVFH-NEXT: ret307;308; ZVFHMIN-LABEL: rint_nxv16f16:309; ZVFHMIN: # %bb.0:310; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma311; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8312; ZVFHMIN-NEXT: lui a0, 307200313; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma314; ZVFHMIN-NEXT: vfabs.v v8, v16315; ZVFHMIN-NEXT: fmv.w.x fa5, a0316; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5317; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t318; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t319; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu320; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t321; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma322; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16323; ZVFHMIN-NEXT: ret324 %a = call <vscale x 16 x half> @llvm.rint.nxv16f16(<vscale x 16 x half> %x)325 ret <vscale x 16 x half> %a326}327 328define <vscale x 32 x half> @rint_nxv32f16(<vscale x 32 x half> %x) {329; ZVFH-LABEL: rint_nxv32f16:330; ZVFH: # %bb.0:331; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma332; ZVFH-NEXT: vfabs.v v16, v8333; ZVFH-NEXT: li a0, 25334; ZVFH-NEXT: slli a0, a0, 10335; ZVFH-NEXT: fmv.h.x fa5, a0336; ZVFH-NEXT: vmflt.vf v0, v16, fa5337; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t338; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t339; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu340; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t341; ZVFH-NEXT: ret342;343; ZVFHMIN-LABEL: rint_nxv32f16:344; ZVFHMIN: # %bb.0:345; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma346; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8347; ZVFHMIN-NEXT: lui a0, 307200348; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma349; ZVFHMIN-NEXT: vfabs.v v24, v16350; ZVFHMIN-NEXT: fmv.w.x fa5, a0351; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5352; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t353; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t354; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu355; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t356; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma357; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12358; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma359; ZVFHMIN-NEXT: vfabs.v v8, v24360; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5361; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma362; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16363; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma364; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t365; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t366; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu367; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t368; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma369; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24370; ZVFHMIN-NEXT: ret371 %a = call <vscale x 32 x half> @llvm.rint.nxv32f16(<vscale x 32 x half> %x)372 ret <vscale x 32 x half> %a373}374 375define <vscale x 1 x float> @rint_nxv1f32(<vscale x 1 x float> %x) {376; CHECK-LABEL: rint_nxv1f32:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma379; CHECK-NEXT: vfabs.v v9, v8380; CHECK-NEXT: lui a0, 307200381; CHECK-NEXT: fmv.w.x fa5, a0382; CHECK-NEXT: vmflt.vf v0, v9, fa5383; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t384; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t385; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu386; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t387; CHECK-NEXT: ret388 %a = call <vscale x 1 x float> @llvm.rint.nxv1f32(<vscale x 1 x float> %x)389 ret <vscale x 1 x float> %a390}391 392define <vscale x 2 x float> @rint_nxv2f32(<vscale x 2 x float> %x) {393; CHECK-LABEL: rint_nxv2f32:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma396; CHECK-NEXT: vfabs.v v9, v8397; CHECK-NEXT: lui a0, 307200398; CHECK-NEXT: fmv.w.x fa5, a0399; CHECK-NEXT: vmflt.vf v0, v9, fa5400; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t401; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t402; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu403; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t404; CHECK-NEXT: ret405 %a = call <vscale x 2 x float> @llvm.rint.nxv2f32(<vscale x 2 x float> %x)406 ret <vscale x 2 x float> %a407}408 409define <vscale x 4 x float> @rint_nxv4f32(<vscale x 4 x float> %x) {410; CHECK-LABEL: rint_nxv4f32:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma413; CHECK-NEXT: vfabs.v v10, v8414; CHECK-NEXT: lui a0, 307200415; CHECK-NEXT: fmv.w.x fa5, a0416; CHECK-NEXT: vmflt.vf v0, v10, fa5417; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t418; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t419; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu420; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t421; CHECK-NEXT: ret422 %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)423 ret <vscale x 4 x float> %a424}425 426define <vscale x 8 x float> @rint_nxv8f32(<vscale x 8 x float> %x) {427; CHECK-LABEL: rint_nxv8f32:428; CHECK: # %bb.0:429; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma430; CHECK-NEXT: vfabs.v v12, v8431; CHECK-NEXT: lui a0, 307200432; CHECK-NEXT: fmv.w.x fa5, a0433; CHECK-NEXT: vmflt.vf v0, v12, fa5434; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t435; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t436; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu437; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t438; CHECK-NEXT: ret439 %a = call <vscale x 8 x float> @llvm.rint.nxv8f32(<vscale x 8 x float> %x)440 ret <vscale x 8 x float> %a441}442 443define <vscale x 16 x float> @rint_nxv16f32(<vscale x 16 x float> %x) {444; CHECK-LABEL: rint_nxv16f32:445; CHECK: # %bb.0:446; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma447; CHECK-NEXT: vfabs.v v16, v8448; CHECK-NEXT: lui a0, 307200449; CHECK-NEXT: fmv.w.x fa5, a0450; CHECK-NEXT: vmflt.vf v0, v16, fa5451; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t452; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t453; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu454; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t455; CHECK-NEXT: ret456 %a = call <vscale x 16 x float> @llvm.rint.nxv16f32(<vscale x 16 x float> %x)457 ret <vscale x 16 x float> %a458}459 460define <vscale x 1 x double> @rint_nxv1f64(<vscale x 1 x double> %x) {461; RV32ZVFH-LABEL: rint_nxv1f64:462; RV32ZVFH: # %bb.0:463; RV32ZVFH-NEXT: lui a0, %hi(.LCPI17_0)464; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)465; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma466; RV32ZVFH-NEXT: vfabs.v v9, v8467; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5468; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t469; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t470; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu471; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t472; RV32ZVFH-NEXT: ret473;474; RV64ZVFH-LABEL: rint_nxv1f64:475; RV64ZVFH: # %bb.0:476; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma477; RV64ZVFH-NEXT: vfabs.v v9, v8478; RV64ZVFH-NEXT: li a0, 1075479; RV64ZVFH-NEXT: slli a0, a0, 52480; RV64ZVFH-NEXT: fmv.d.x fa5, a0481; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5482; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t483; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t484; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu485; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t486; RV64ZVFH-NEXT: ret487;488; RV32ZVFHMIN-LABEL: rint_nxv1f64:489; RV32ZVFHMIN: # %bb.0:490; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI17_0)491; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)492; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma493; RV32ZVFHMIN-NEXT: vfabs.v v9, v8494; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5495; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t496; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t497; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu498; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t499; RV32ZVFHMIN-NEXT: ret500;501; RV64ZVFHMIN-LABEL: rint_nxv1f64:502; RV64ZVFHMIN: # %bb.0:503; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma504; RV64ZVFHMIN-NEXT: vfabs.v v9, v8505; RV64ZVFHMIN-NEXT: li a0, 1075506; RV64ZVFHMIN-NEXT: slli a0, a0, 52507; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0508; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5509; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t510; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t511; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu512; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t513; RV64ZVFHMIN-NEXT: ret514 %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)515 ret <vscale x 1 x double> %a516}517 518define <vscale x 2 x double> @rint_nxv2f64(<vscale x 2 x double> %x) {519; RV32ZVFH-LABEL: rint_nxv2f64:520; RV32ZVFH: # %bb.0:521; RV32ZVFH-NEXT: lui a0, %hi(.LCPI18_0)522; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)523; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma524; RV32ZVFH-NEXT: vfabs.v v10, v8525; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5526; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t527; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t528; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu529; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t530; RV32ZVFH-NEXT: ret531;532; RV64ZVFH-LABEL: rint_nxv2f64:533; RV64ZVFH: # %bb.0:534; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma535; RV64ZVFH-NEXT: vfabs.v v10, v8536; RV64ZVFH-NEXT: li a0, 1075537; RV64ZVFH-NEXT: slli a0, a0, 52538; RV64ZVFH-NEXT: fmv.d.x fa5, a0539; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5540; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t541; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t542; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu543; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t544; RV64ZVFH-NEXT: ret545;546; RV32ZVFHMIN-LABEL: rint_nxv2f64:547; RV32ZVFHMIN: # %bb.0:548; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI18_0)549; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)550; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma551; RV32ZVFHMIN-NEXT: vfabs.v v10, v8552; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5553; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t554; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t555; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu556; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t557; RV32ZVFHMIN-NEXT: ret558;559; RV64ZVFHMIN-LABEL: rint_nxv2f64:560; RV64ZVFHMIN: # %bb.0:561; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma562; RV64ZVFHMIN-NEXT: vfabs.v v10, v8563; RV64ZVFHMIN-NEXT: li a0, 1075564; RV64ZVFHMIN-NEXT: slli a0, a0, 52565; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0566; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5567; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t568; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t569; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu570; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t571; RV64ZVFHMIN-NEXT: ret572 %a = call <vscale x 2 x double> @llvm.rint.nxv2f64(<vscale x 2 x double> %x)573 ret <vscale x 2 x double> %a574}575 576define <vscale x 4 x double> @rint_nxv4f64(<vscale x 4 x double> %x) {577; RV32ZVFH-LABEL: rint_nxv4f64:578; RV32ZVFH: # %bb.0:579; RV32ZVFH-NEXT: lui a0, %hi(.LCPI19_0)580; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)581; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma582; RV32ZVFH-NEXT: vfabs.v v12, v8583; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5584; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t585; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t586; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu587; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t588; RV32ZVFH-NEXT: ret589;590; RV64ZVFH-LABEL: rint_nxv4f64:591; RV64ZVFH: # %bb.0:592; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma593; RV64ZVFH-NEXT: vfabs.v v12, v8594; RV64ZVFH-NEXT: li a0, 1075595; RV64ZVFH-NEXT: slli a0, a0, 52596; RV64ZVFH-NEXT: fmv.d.x fa5, a0597; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5598; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t599; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t600; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu601; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t602; RV64ZVFH-NEXT: ret603;604; RV32ZVFHMIN-LABEL: rint_nxv4f64:605; RV32ZVFHMIN: # %bb.0:606; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI19_0)607; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)608; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma609; RV32ZVFHMIN-NEXT: vfabs.v v12, v8610; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5611; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t612; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t613; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu614; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t615; RV32ZVFHMIN-NEXT: ret616;617; RV64ZVFHMIN-LABEL: rint_nxv4f64:618; RV64ZVFHMIN: # %bb.0:619; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma620; RV64ZVFHMIN-NEXT: vfabs.v v12, v8621; RV64ZVFHMIN-NEXT: li a0, 1075622; RV64ZVFHMIN-NEXT: slli a0, a0, 52623; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0624; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5625; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t626; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t627; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu628; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t629; RV64ZVFHMIN-NEXT: ret630 %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)631 ret <vscale x 4 x double> %a632}633 634define <vscale x 8 x double> @rint_nxv8f64(<vscale x 8 x double> %x) {635; RV32ZVFH-LABEL: rint_nxv8f64:636; RV32ZVFH: # %bb.0:637; RV32ZVFH-NEXT: lui a0, %hi(.LCPI20_0)638; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)639; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma640; RV32ZVFH-NEXT: vfabs.v v16, v8641; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5642; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t643; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t644; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu645; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t646; RV32ZVFH-NEXT: ret647;648; RV64ZVFH-LABEL: rint_nxv8f64:649; RV64ZVFH: # %bb.0:650; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma651; RV64ZVFH-NEXT: vfabs.v v16, v8652; RV64ZVFH-NEXT: li a0, 1075653; RV64ZVFH-NEXT: slli a0, a0, 52654; RV64ZVFH-NEXT: fmv.d.x fa5, a0655; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5656; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t657; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t658; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu659; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t660; RV64ZVFH-NEXT: ret661;662; RV32ZVFHMIN-LABEL: rint_nxv8f64:663; RV32ZVFHMIN: # %bb.0:664; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI20_0)665; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)666; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma667; RV32ZVFHMIN-NEXT: vfabs.v v16, v8668; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5669; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t670; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t671; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu672; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t673; RV32ZVFHMIN-NEXT: ret674;675; RV64ZVFHMIN-LABEL: rint_nxv8f64:676; RV64ZVFHMIN: # %bb.0:677; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma678; RV64ZVFHMIN-NEXT: vfabs.v v16, v8679; RV64ZVFHMIN-NEXT: li a0, 1075680; RV64ZVFHMIN-NEXT: slli a0, a0, 52681; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0682; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5683; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t684; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t685; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu686; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t687; RV64ZVFHMIN-NEXT: ret688 %a = call <vscale x 8 x double> @llvm.rint.nxv8f64(<vscale x 8 x double> %x)689 ret <vscale x 8 x double> %a690}691