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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN14 15; This file tests the code generation for `llvm.round.*` on scalable vector type.16 17define <vscale x 1 x bfloat> @round_nxv1bf16(<vscale x 1 x bfloat> %x) {18; CHECK-LABEL: round_nxv1bf16:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma21; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v822; CHECK-NEXT: lui a0, 30720023; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; CHECK-NEXT: vfabs.v v8, v925; CHECK-NEXT: fmv.w.x fa5, a026; CHECK-NEXT: vmflt.vf v0, v8, fa527; CHECK-NEXT: fsrmi a0, 428; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t29; CHECK-NEXT: fsrm a030; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t31; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu32; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t33; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma34; CHECK-NEXT: vfncvtbf16.f.f.w v8, v935; CHECK-NEXT: ret36 %a = call <vscale x 1 x bfloat> @llvm.round.nxv1bf16(<vscale x 1 x bfloat> %x)37 ret <vscale x 1 x bfloat> %a38}39 40define <vscale x 2 x bfloat> @round_nxv2bf16(<vscale x 2 x bfloat> %x) {41; CHECK-LABEL: round_nxv2bf16:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma44; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v845; CHECK-NEXT: lui a0, 30720046; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma47; CHECK-NEXT: vfabs.v v8, v948; CHECK-NEXT: fmv.w.x fa5, a049; CHECK-NEXT: vmflt.vf v0, v8, fa550; CHECK-NEXT: fsrmi a0, 451; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t52; CHECK-NEXT: fsrm a053; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t54; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu55; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t56; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma57; CHECK-NEXT: vfncvtbf16.f.f.w v8, v958; CHECK-NEXT: ret59 %a = call <vscale x 2 x bfloat> @llvm.round.nxv2bf16(<vscale x 2 x bfloat> %x)60 ret <vscale x 2 x bfloat> %a61}62 63define <vscale x 4 x bfloat> @round_nxv4bf16(<vscale x 4 x bfloat> %x) {64; CHECK-LABEL: round_nxv4bf16:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma67; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v868; CHECK-NEXT: lui a0, 30720069; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma70; CHECK-NEXT: vfabs.v v8, v1071; CHECK-NEXT: fmv.w.x fa5, a072; CHECK-NEXT: vmflt.vf v0, v8, fa573; CHECK-NEXT: fsrmi a0, 474; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t75; CHECK-NEXT: fsrm a076; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t77; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu78; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t79; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma80; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1081; CHECK-NEXT: ret82 %a = call <vscale x 4 x bfloat> @llvm.round.nxv4bf16(<vscale x 4 x bfloat> %x)83 ret <vscale x 4 x bfloat> %a84}85 86define <vscale x 8 x bfloat> @round_nxv8bf16(<vscale x 8 x bfloat> %x) {87; CHECK-LABEL: round_nxv8bf16:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma90; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v891; CHECK-NEXT: lui a0, 30720092; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma93; CHECK-NEXT: vfabs.v v8, v1294; CHECK-NEXT: fmv.w.x fa5, a095; CHECK-NEXT: vmflt.vf v0, v8, fa596; CHECK-NEXT: fsrmi a0, 497; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t98; CHECK-NEXT: fsrm a099; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t100; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu101; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t102; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma103; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12104; CHECK-NEXT: ret105 %a = call <vscale x 8 x bfloat> @llvm.round.nxv8bf16(<vscale x 8 x bfloat> %x)106 ret <vscale x 8 x bfloat> %a107}108 109define <vscale x 16 x bfloat> @round_nxv16bf16(<vscale x 16 x bfloat> %x) {110; CHECK-LABEL: round_nxv16bf16:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma113; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8114; CHECK-NEXT: lui a0, 307200115; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma116; CHECK-NEXT: vfabs.v v8, v16117; CHECK-NEXT: fmv.w.x fa5, a0118; CHECK-NEXT: vmflt.vf v0, v8, fa5119; CHECK-NEXT: fsrmi a0, 4120; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t121; CHECK-NEXT: fsrm a0122; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t123; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu124; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t125; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma126; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16127; CHECK-NEXT: ret128 %a = call <vscale x 16 x bfloat> @llvm.round.nxv16bf16(<vscale x 16 x bfloat> %x)129 ret <vscale x 16 x bfloat> %a130}131 132define <vscale x 32 x bfloat> @round_nxv32bf16(<vscale x 32 x bfloat> %x) {133; CHECK-LABEL: round_nxv32bf16:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma136; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8137; CHECK-NEXT: lui a0, 307200138; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma139; CHECK-NEXT: vfabs.v v24, v16140; CHECK-NEXT: fmv.w.x fa5, a0141; CHECK-NEXT: vmflt.vf v0, v24, fa5142; CHECK-NEXT: fsrmi a0, 4143; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t144; CHECK-NEXT: fsrm a0145; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t146; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu147; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t148; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma149; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12150; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma151; CHECK-NEXT: vfabs.v v8, v24152; CHECK-NEXT: vmflt.vf v0, v8, fa5153; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma154; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16155; CHECK-NEXT: fsrmi a0, 4156; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma157; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t158; CHECK-NEXT: fsrm a0159; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t160; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu161; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t162; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma163; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24164; CHECK-NEXT: ret165 %a = call <vscale x 32 x bfloat> @llvm.round.nxv32bf16(<vscale x 32 x bfloat> %x)166 ret <vscale x 32 x bfloat> %a167}168 169define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) {170; ZVFH-LABEL: round_nxv1f16:171; ZVFH: # %bb.0:172; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma173; ZVFH-NEXT: vfabs.v v9, v8174; ZVFH-NEXT: li a0, 25175; ZVFH-NEXT: slli a0, a0, 10176; ZVFH-NEXT: fmv.h.x fa5, a0177; ZVFH-NEXT: vmflt.vf v0, v9, fa5178; ZVFH-NEXT: fsrmi a0, 4179; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t180; ZVFH-NEXT: fsrm a0181; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t182; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu183; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t184; ZVFH-NEXT: ret185;186; ZVFHMIN-LABEL: round_nxv1f16:187; ZVFHMIN: # %bb.0:188; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma189; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8190; ZVFHMIN-NEXT: lui a0, 307200191; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma192; ZVFHMIN-NEXT: vfabs.v v8, v9193; ZVFHMIN-NEXT: fmv.w.x fa5, a0194; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5195; ZVFHMIN-NEXT: fsrmi a0, 4196; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t197; ZVFHMIN-NEXT: fsrm a0198; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t199; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu200; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t201; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma202; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9203; ZVFHMIN-NEXT: ret204 %a = call <vscale x 1 x half> @llvm.round.nxv1f16(<vscale x 1 x half> %x)205 ret <vscale x 1 x half> %a206}207 208define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) {209; ZVFH-LABEL: round_nxv2f16:210; ZVFH: # %bb.0:211; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma212; ZVFH-NEXT: vfabs.v v9, v8213; ZVFH-NEXT: li a0, 25214; ZVFH-NEXT: slli a0, a0, 10215; ZVFH-NEXT: fmv.h.x fa5, a0216; ZVFH-NEXT: vmflt.vf v0, v9, fa5217; ZVFH-NEXT: fsrmi a0, 4218; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t219; ZVFH-NEXT: fsrm a0220; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t221; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu222; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t223; ZVFH-NEXT: ret224;225; ZVFHMIN-LABEL: round_nxv2f16:226; ZVFHMIN: # %bb.0:227; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma228; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8229; ZVFHMIN-NEXT: lui a0, 307200230; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma231; ZVFHMIN-NEXT: vfabs.v v8, v9232; ZVFHMIN-NEXT: fmv.w.x fa5, a0233; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5234; ZVFHMIN-NEXT: fsrmi a0, 4235; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t236; ZVFHMIN-NEXT: fsrm a0237; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t238; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu239; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t240; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma241; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9242; ZVFHMIN-NEXT: ret243 %a = call <vscale x 2 x half> @llvm.round.nxv2f16(<vscale x 2 x half> %x)244 ret <vscale x 2 x half> %a245}246 247define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) {248; ZVFH-LABEL: round_nxv4f16:249; ZVFH: # %bb.0:250; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma251; ZVFH-NEXT: vfabs.v v9, v8252; ZVFH-NEXT: li a0, 25253; ZVFH-NEXT: slli a0, a0, 10254; ZVFH-NEXT: fmv.h.x fa5, a0255; ZVFH-NEXT: vmflt.vf v0, v9, fa5256; ZVFH-NEXT: fsrmi a0, 4257; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t258; ZVFH-NEXT: fsrm a0259; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t260; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu261; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t262; ZVFH-NEXT: ret263;264; ZVFHMIN-LABEL: round_nxv4f16:265; ZVFHMIN: # %bb.0:266; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma267; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8268; ZVFHMIN-NEXT: lui a0, 307200269; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma270; ZVFHMIN-NEXT: vfabs.v v8, v10271; ZVFHMIN-NEXT: fmv.w.x fa5, a0272; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5273; ZVFHMIN-NEXT: fsrmi a0, 4274; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t275; ZVFHMIN-NEXT: fsrm a0276; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t277; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu278; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t279; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma280; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10281; ZVFHMIN-NEXT: ret282 %a = call <vscale x 4 x half> @llvm.round.nxv4f16(<vscale x 4 x half> %x)283 ret <vscale x 4 x half> %a284}285 286define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {287; ZVFH-LABEL: round_nxv8f16:288; ZVFH: # %bb.0:289; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma290; ZVFH-NEXT: vfabs.v v10, v8291; ZVFH-NEXT: li a0, 25292; ZVFH-NEXT: slli a0, a0, 10293; ZVFH-NEXT: fmv.h.x fa5, a0294; ZVFH-NEXT: vmflt.vf v0, v10, fa5295; ZVFH-NEXT: fsrmi a0, 4296; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t297; ZVFH-NEXT: fsrm a0298; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t299; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu300; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t301; ZVFH-NEXT: ret302;303; ZVFHMIN-LABEL: round_nxv8f16:304; ZVFHMIN: # %bb.0:305; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma306; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8307; ZVFHMIN-NEXT: lui a0, 307200308; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma309; ZVFHMIN-NEXT: vfabs.v v8, v12310; ZVFHMIN-NEXT: fmv.w.x fa5, a0311; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5312; ZVFHMIN-NEXT: fsrmi a0, 4313; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t314; ZVFHMIN-NEXT: fsrm a0315; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t316; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu317; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t318; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma319; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12320; ZVFHMIN-NEXT: ret321 %a = call <vscale x 8 x half> @llvm.round.nxv8f16(<vscale x 8 x half> %x)322 ret <vscale x 8 x half> %a323}324 325define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {326; ZVFH-LABEL: round_nxv16f16:327; ZVFH: # %bb.0:328; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma329; ZVFH-NEXT: vfabs.v v12, v8330; ZVFH-NEXT: li a0, 25331; ZVFH-NEXT: slli a0, a0, 10332; ZVFH-NEXT: fmv.h.x fa5, a0333; ZVFH-NEXT: vmflt.vf v0, v12, fa5334; ZVFH-NEXT: fsrmi a0, 4335; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t336; ZVFH-NEXT: fsrm a0337; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t338; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu339; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t340; ZVFH-NEXT: ret341;342; ZVFHMIN-LABEL: round_nxv16f16:343; ZVFHMIN: # %bb.0:344; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma345; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8346; ZVFHMIN-NEXT: lui a0, 307200347; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma348; ZVFHMIN-NEXT: vfabs.v v8, v16349; ZVFHMIN-NEXT: fmv.w.x fa5, a0350; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5351; ZVFHMIN-NEXT: fsrmi a0, 4352; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t353; ZVFHMIN-NEXT: fsrm a0354; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t355; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu356; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t357; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma358; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16359; ZVFHMIN-NEXT: ret360 %a = call <vscale x 16 x half> @llvm.round.nxv16f16(<vscale x 16 x half> %x)361 ret <vscale x 16 x half> %a362}363 364define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {365; ZVFH-LABEL: round_nxv32f16:366; ZVFH: # %bb.0:367; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma368; ZVFH-NEXT: vfabs.v v16, v8369; ZVFH-NEXT: li a0, 25370; ZVFH-NEXT: slli a0, a0, 10371; ZVFH-NEXT: fmv.h.x fa5, a0372; ZVFH-NEXT: vmflt.vf v0, v16, fa5373; ZVFH-NEXT: fsrmi a0, 4374; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t375; ZVFH-NEXT: fsrm a0376; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t377; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu378; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t379; ZVFH-NEXT: ret380;381; ZVFHMIN-LABEL: round_nxv32f16:382; ZVFHMIN: # %bb.0:383; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma384; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8385; ZVFHMIN-NEXT: lui a0, 307200386; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma387; ZVFHMIN-NEXT: vfabs.v v24, v16388; ZVFHMIN-NEXT: fmv.w.x fa5, a0389; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5390; ZVFHMIN-NEXT: fsrmi a0, 4391; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t392; ZVFHMIN-NEXT: fsrm a0393; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t394; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu395; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t396; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma397; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12398; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma399; ZVFHMIN-NEXT: vfabs.v v8, v24400; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5401; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma402; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16403; ZVFHMIN-NEXT: fsrmi a0, 4404; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma405; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t406; ZVFHMIN-NEXT: fsrm a0407; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t408; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu409; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t410; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma411; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24412; ZVFHMIN-NEXT: ret413 %a = call <vscale x 32 x half> @llvm.round.nxv32f16(<vscale x 32 x half> %x)414 ret <vscale x 32 x half> %a415}416 417define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) {418; CHECK-LABEL: round_nxv1f32:419; CHECK: # %bb.0:420; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma421; CHECK-NEXT: vfabs.v v9, v8422; CHECK-NEXT: lui a0, 307200423; CHECK-NEXT: fmv.w.x fa5, a0424; CHECK-NEXT: vmflt.vf v0, v9, fa5425; CHECK-NEXT: fsrmi a0, 4426; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t427; CHECK-NEXT: fsrm a0428; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t429; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu430; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t431; CHECK-NEXT: ret432 %a = call <vscale x 1 x float> @llvm.round.nxv1f32(<vscale x 1 x float> %x)433 ret <vscale x 1 x float> %a434}435 436define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) {437; CHECK-LABEL: round_nxv2f32:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma440; CHECK-NEXT: vfabs.v v9, v8441; CHECK-NEXT: lui a0, 307200442; CHECK-NEXT: fmv.w.x fa5, a0443; CHECK-NEXT: vmflt.vf v0, v9, fa5444; CHECK-NEXT: fsrmi a0, 4445; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t446; CHECK-NEXT: fsrm a0447; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t448; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu449; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t450; CHECK-NEXT: ret451 %a = call <vscale x 2 x float> @llvm.round.nxv2f32(<vscale x 2 x float> %x)452 ret <vscale x 2 x float> %a453}454 455define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) {456; CHECK-LABEL: round_nxv4f32:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma459; CHECK-NEXT: vfabs.v v10, v8460; CHECK-NEXT: lui a0, 307200461; CHECK-NEXT: fmv.w.x fa5, a0462; CHECK-NEXT: vmflt.vf v0, v10, fa5463; CHECK-NEXT: fsrmi a0, 4464; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t465; CHECK-NEXT: fsrm a0466; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t467; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu468; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t469; CHECK-NEXT: ret470 %a = call <vscale x 4 x float> @llvm.round.nxv4f32(<vscale x 4 x float> %x)471 ret <vscale x 4 x float> %a472}473 474define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) {475; CHECK-LABEL: round_nxv8f32:476; CHECK: # %bb.0:477; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma478; CHECK-NEXT: vfabs.v v12, v8479; CHECK-NEXT: lui a0, 307200480; CHECK-NEXT: fmv.w.x fa5, a0481; CHECK-NEXT: vmflt.vf v0, v12, fa5482; CHECK-NEXT: fsrmi a0, 4483; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t484; CHECK-NEXT: fsrm a0485; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t486; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu487; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t488; CHECK-NEXT: ret489 %a = call <vscale x 8 x float> @llvm.round.nxv8f32(<vscale x 8 x float> %x)490 ret <vscale x 8 x float> %a491}492 493define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) {494; CHECK-LABEL: round_nxv16f32:495; CHECK: # %bb.0:496; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma497; CHECK-NEXT: vfabs.v v16, v8498; CHECK-NEXT: lui a0, 307200499; CHECK-NEXT: fmv.w.x fa5, a0500; CHECK-NEXT: vmflt.vf v0, v16, fa5501; CHECK-NEXT: fsrmi a0, 4502; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t503; CHECK-NEXT: fsrm a0504; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t505; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu506; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t507; CHECK-NEXT: ret508 %a = call <vscale x 16 x float> @llvm.round.nxv16f32(<vscale x 16 x float> %x)509 ret <vscale x 16 x float> %a510}511 512define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {513; RV32ZVFH-LABEL: round_nxv1f64:514; RV32ZVFH: # %bb.0:515; RV32ZVFH-NEXT: lui a0, %hi(.LCPI17_0)516; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)517; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma518; RV32ZVFH-NEXT: vfabs.v v9, v8519; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5520; RV32ZVFH-NEXT: fsrmi a0, 4521; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t522; RV32ZVFH-NEXT: fsrm a0523; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t524; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu525; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t526; RV32ZVFH-NEXT: ret527;528; RV64ZVFH-LABEL: round_nxv1f64:529; RV64ZVFH: # %bb.0:530; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma531; RV64ZVFH-NEXT: vfabs.v v9, v8532; RV64ZVFH-NEXT: li a0, 1075533; RV64ZVFH-NEXT: slli a0, a0, 52534; RV64ZVFH-NEXT: fmv.d.x fa5, a0535; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5536; RV64ZVFH-NEXT: fsrmi a0, 4537; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t538; RV64ZVFH-NEXT: fsrm a0539; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t540; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu541; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t542; RV64ZVFH-NEXT: ret543;544; RV32ZVFHMIN-LABEL: round_nxv1f64:545; RV32ZVFHMIN: # %bb.0:546; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI17_0)547; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)548; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma549; RV32ZVFHMIN-NEXT: vfabs.v v9, v8550; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5551; RV32ZVFHMIN-NEXT: fsrmi a0, 4552; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t553; RV32ZVFHMIN-NEXT: fsrm a0554; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t555; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu556; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t557; RV32ZVFHMIN-NEXT: ret558;559; RV64ZVFHMIN-LABEL: round_nxv1f64:560; RV64ZVFHMIN: # %bb.0:561; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma562; RV64ZVFHMIN-NEXT: vfabs.v v9, v8563; RV64ZVFHMIN-NEXT: li a0, 1075564; RV64ZVFHMIN-NEXT: slli a0, a0, 52565; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0566; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5567; RV64ZVFHMIN-NEXT: fsrmi a0, 4568; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t569; RV64ZVFHMIN-NEXT: fsrm a0570; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t571; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu572; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t573; RV64ZVFHMIN-NEXT: ret574 %a = call <vscale x 1 x double> @llvm.round.nxv1f64(<vscale x 1 x double> %x)575 ret <vscale x 1 x double> %a576}577 578define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {579; RV32ZVFH-LABEL: round_nxv2f64:580; RV32ZVFH: # %bb.0:581; RV32ZVFH-NEXT: lui a0, %hi(.LCPI18_0)582; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)583; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma584; RV32ZVFH-NEXT: vfabs.v v10, v8585; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5586; RV32ZVFH-NEXT: fsrmi a0, 4587; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t588; RV32ZVFH-NEXT: fsrm a0589; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t590; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu591; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t592; RV32ZVFH-NEXT: ret593;594; RV64ZVFH-LABEL: round_nxv2f64:595; RV64ZVFH: # %bb.0:596; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma597; RV64ZVFH-NEXT: vfabs.v v10, v8598; RV64ZVFH-NEXT: li a0, 1075599; RV64ZVFH-NEXT: slli a0, a0, 52600; RV64ZVFH-NEXT: fmv.d.x fa5, a0601; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5602; RV64ZVFH-NEXT: fsrmi a0, 4603; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t604; RV64ZVFH-NEXT: fsrm a0605; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t606; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu607; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t608; RV64ZVFH-NEXT: ret609;610; RV32ZVFHMIN-LABEL: round_nxv2f64:611; RV32ZVFHMIN: # %bb.0:612; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI18_0)613; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)614; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma615; RV32ZVFHMIN-NEXT: vfabs.v v10, v8616; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5617; RV32ZVFHMIN-NEXT: fsrmi a0, 4618; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t619; RV32ZVFHMIN-NEXT: fsrm a0620; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t621; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu622; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t623; RV32ZVFHMIN-NEXT: ret624;625; RV64ZVFHMIN-LABEL: round_nxv2f64:626; RV64ZVFHMIN: # %bb.0:627; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma628; RV64ZVFHMIN-NEXT: vfabs.v v10, v8629; RV64ZVFHMIN-NEXT: li a0, 1075630; RV64ZVFHMIN-NEXT: slli a0, a0, 52631; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0632; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5633; RV64ZVFHMIN-NEXT: fsrmi a0, 4634; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t635; RV64ZVFHMIN-NEXT: fsrm a0636; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t637; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu638; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t639; RV64ZVFHMIN-NEXT: ret640 %a = call <vscale x 2 x double> @llvm.round.nxv2f64(<vscale x 2 x double> %x)641 ret <vscale x 2 x double> %a642}643 644define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {645; RV32ZVFH-LABEL: round_nxv4f64:646; RV32ZVFH: # %bb.0:647; RV32ZVFH-NEXT: lui a0, %hi(.LCPI19_0)648; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)649; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma650; RV32ZVFH-NEXT: vfabs.v v12, v8651; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5652; RV32ZVFH-NEXT: fsrmi a0, 4653; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t654; RV32ZVFH-NEXT: fsrm a0655; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t656; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu657; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t658; RV32ZVFH-NEXT: ret659;660; RV64ZVFH-LABEL: round_nxv4f64:661; RV64ZVFH: # %bb.0:662; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma663; RV64ZVFH-NEXT: vfabs.v v12, v8664; RV64ZVFH-NEXT: li a0, 1075665; RV64ZVFH-NEXT: slli a0, a0, 52666; RV64ZVFH-NEXT: fmv.d.x fa5, a0667; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5668; RV64ZVFH-NEXT: fsrmi a0, 4669; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t670; RV64ZVFH-NEXT: fsrm a0671; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t672; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu673; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t674; RV64ZVFH-NEXT: ret675;676; RV32ZVFHMIN-LABEL: round_nxv4f64:677; RV32ZVFHMIN: # %bb.0:678; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI19_0)679; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)680; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma681; RV32ZVFHMIN-NEXT: vfabs.v v12, v8682; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5683; RV32ZVFHMIN-NEXT: fsrmi a0, 4684; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t685; RV32ZVFHMIN-NEXT: fsrm a0686; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t687; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu688; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t689; RV32ZVFHMIN-NEXT: ret690;691; RV64ZVFHMIN-LABEL: round_nxv4f64:692; RV64ZVFHMIN: # %bb.0:693; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma694; RV64ZVFHMIN-NEXT: vfabs.v v12, v8695; RV64ZVFHMIN-NEXT: li a0, 1075696; RV64ZVFHMIN-NEXT: slli a0, a0, 52697; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0698; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5699; RV64ZVFHMIN-NEXT: fsrmi a0, 4700; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t701; RV64ZVFHMIN-NEXT: fsrm a0702; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t703; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu704; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t705; RV64ZVFHMIN-NEXT: ret706 %a = call <vscale x 4 x double> @llvm.round.nxv4f64(<vscale x 4 x double> %x)707 ret <vscale x 4 x double> %a708}709 710define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {711; RV32ZVFH-LABEL: round_nxv8f64:712; RV32ZVFH: # %bb.0:713; RV32ZVFH-NEXT: lui a0, %hi(.LCPI20_0)714; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)715; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma716; RV32ZVFH-NEXT: vfabs.v v16, v8717; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5718; RV32ZVFH-NEXT: fsrmi a0, 4719; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t720; RV32ZVFH-NEXT: fsrm a0721; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t722; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu723; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t724; RV32ZVFH-NEXT: ret725;726; RV64ZVFH-LABEL: round_nxv8f64:727; RV64ZVFH: # %bb.0:728; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma729; RV64ZVFH-NEXT: vfabs.v v16, v8730; RV64ZVFH-NEXT: li a0, 1075731; RV64ZVFH-NEXT: slli a0, a0, 52732; RV64ZVFH-NEXT: fmv.d.x fa5, a0733; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5734; RV64ZVFH-NEXT: fsrmi a0, 4735; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t736; RV64ZVFH-NEXT: fsrm a0737; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t738; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu739; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t740; RV64ZVFH-NEXT: ret741;742; RV32ZVFHMIN-LABEL: round_nxv8f64:743; RV32ZVFHMIN: # %bb.0:744; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI20_0)745; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)746; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma747; RV32ZVFHMIN-NEXT: vfabs.v v16, v8748; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5749; RV32ZVFHMIN-NEXT: fsrmi a0, 4750; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t751; RV32ZVFHMIN-NEXT: fsrm a0752; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t753; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu754; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t755; RV32ZVFHMIN-NEXT: ret756;757; RV64ZVFHMIN-LABEL: round_nxv8f64:758; RV64ZVFHMIN: # %bb.0:759; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma760; RV64ZVFHMIN-NEXT: vfabs.v v16, v8761; RV64ZVFHMIN-NEXT: li a0, 1075762; RV64ZVFHMIN-NEXT: slli a0, a0, 52763; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0764; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5765; RV64ZVFHMIN-NEXT: fsrmi a0, 4766; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t767; RV64ZVFHMIN-NEXT: fsrm a0768; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t769; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu770; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t771; RV64ZVFHMIN-NEXT: ret772 %a = call <vscale x 8 x double> @llvm.round.nxv8f64(<vscale x 8 x double> %x)773 ret <vscale x 8 x double> %a774}775