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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN14 15; This file tests the code generation for `llvm.roundeven.*` on scalable vector type.16define <vscale x 1 x bfloat> @roundeven_nxv1bf16(<vscale x 1 x bfloat> %x) {17; CHECK-LABEL: roundeven_nxv1bf16:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma20; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v821; CHECK-NEXT: lui a0, 30720022; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma23; CHECK-NEXT: vfabs.v v8, v924; CHECK-NEXT: fmv.w.x fa5, a025; CHECK-NEXT: vmflt.vf v0, v8, fa526; CHECK-NEXT: fsrmi a0, 027; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t28; CHECK-NEXT: fsrm a029; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t30; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu31; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t32; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma33; CHECK-NEXT: vfncvtbf16.f.f.w v8, v934; CHECK-NEXT: ret35 %a = call <vscale x 1 x bfloat> @llvm.roundeven.nxv1bf16(<vscale x 1 x bfloat> %x)36 ret <vscale x 1 x bfloat> %a37}38 39define <vscale x 2 x bfloat> @roundeven_nxv2bf16(<vscale x 2 x bfloat> %x) {40; CHECK-LABEL: roundeven_nxv2bf16:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma43; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v844; CHECK-NEXT: lui a0, 30720045; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma46; CHECK-NEXT: vfabs.v v8, v947; CHECK-NEXT: fmv.w.x fa5, a048; CHECK-NEXT: vmflt.vf v0, v8, fa549; CHECK-NEXT: fsrmi a0, 050; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t51; CHECK-NEXT: fsrm a052; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t53; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu54; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t55; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma56; CHECK-NEXT: vfncvtbf16.f.f.w v8, v957; CHECK-NEXT: ret58 %a = call <vscale x 2 x bfloat> @llvm.roundeven.nxv2bf16(<vscale x 2 x bfloat> %x)59 ret <vscale x 2 x bfloat> %a60}61 62define <vscale x 4 x bfloat> @roundeven_nxv4bf16(<vscale x 4 x bfloat> %x) {63; CHECK-LABEL: roundeven_nxv4bf16:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma66; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v867; CHECK-NEXT: lui a0, 30720068; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma69; CHECK-NEXT: vfabs.v v8, v1070; CHECK-NEXT: fmv.w.x fa5, a071; CHECK-NEXT: vmflt.vf v0, v8, fa572; CHECK-NEXT: fsrmi a0, 073; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t74; CHECK-NEXT: fsrm a075; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t76; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu77; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t78; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma79; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1080; CHECK-NEXT: ret81 %a = call <vscale x 4 x bfloat> @llvm.roundeven.nxv4bf16(<vscale x 4 x bfloat> %x)82 ret <vscale x 4 x bfloat> %a83}84 85define <vscale x 8 x bfloat> @roundeven_nxv8bf16(<vscale x 8 x bfloat> %x) {86; CHECK-LABEL: roundeven_nxv8bf16:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma89; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v890; CHECK-NEXT: lui a0, 30720091; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma92; CHECK-NEXT: vfabs.v v8, v1293; CHECK-NEXT: fmv.w.x fa5, a094; CHECK-NEXT: vmflt.vf v0, v8, fa595; CHECK-NEXT: fsrmi a0, 096; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t97; CHECK-NEXT: fsrm a098; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t99; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu100; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t101; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma102; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12103; CHECK-NEXT: ret104 %a = call <vscale x 8 x bfloat> @llvm.roundeven.nxv8bf16(<vscale x 8 x bfloat> %x)105 ret <vscale x 8 x bfloat> %a106}107 108define <vscale x 16 x bfloat> @roundeven_nxv16bf16(<vscale x 16 x bfloat> %x) {109; CHECK-LABEL: roundeven_nxv16bf16:110; CHECK: # %bb.0:111; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma112; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8113; CHECK-NEXT: lui a0, 307200114; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma115; CHECK-NEXT: vfabs.v v8, v16116; CHECK-NEXT: fmv.w.x fa5, a0117; CHECK-NEXT: vmflt.vf v0, v8, fa5118; CHECK-NEXT: fsrmi a0, 0119; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t120; CHECK-NEXT: fsrm a0121; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t122; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu123; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t124; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma125; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16126; CHECK-NEXT: ret127 %a = call <vscale x 16 x bfloat> @llvm.roundeven.nxv16bf16(<vscale x 16 x bfloat> %x)128 ret <vscale x 16 x bfloat> %a129}130 131define <vscale x 32 x bfloat> @roundeven_nxv32bf16(<vscale x 32 x bfloat> %x) {132; CHECK-LABEL: roundeven_nxv32bf16:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma135; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8136; CHECK-NEXT: lui a0, 307200137; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma138; CHECK-NEXT: vfabs.v v24, v16139; CHECK-NEXT: fmv.w.x fa5, a0140; CHECK-NEXT: vmflt.vf v0, v24, fa5141; CHECK-NEXT: fsrmi a0, 0142; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t143; CHECK-NEXT: fsrm a0144; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t145; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu146; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t147; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma148; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12149; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma150; CHECK-NEXT: vfabs.v v8, v24151; CHECK-NEXT: vmflt.vf v0, v8, fa5152; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma153; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16154; CHECK-NEXT: fsrmi a0, 0155; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma156; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t157; CHECK-NEXT: fsrm a0158; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t159; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu160; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t161; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma162; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24163; CHECK-NEXT: ret164 %a = call <vscale x 32 x bfloat> @llvm.roundeven.nxv32bf16(<vscale x 32 x bfloat> %x)165 ret <vscale x 32 x bfloat> %a166}167 168define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) {169; ZVFH-LABEL: roundeven_nxv1f16:170; ZVFH: # %bb.0:171; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma172; ZVFH-NEXT: vfabs.v v9, v8173; ZVFH-NEXT: li a0, 25174; ZVFH-NEXT: slli a0, a0, 10175; ZVFH-NEXT: fmv.h.x fa5, a0176; ZVFH-NEXT: vmflt.vf v0, v9, fa5177; ZVFH-NEXT: fsrmi a0, 0178; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t179; ZVFH-NEXT: fsrm a0180; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t181; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu182; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t183; ZVFH-NEXT: ret184;185; ZVFHMIN-LABEL: roundeven_nxv1f16:186; ZVFHMIN: # %bb.0:187; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma188; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8189; ZVFHMIN-NEXT: lui a0, 307200190; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma191; ZVFHMIN-NEXT: vfabs.v v8, v9192; ZVFHMIN-NEXT: fmv.w.x fa5, a0193; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5194; ZVFHMIN-NEXT: fsrmi a0, 0195; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t196; ZVFHMIN-NEXT: fsrm a0197; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t198; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu199; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t200; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma201; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9202; ZVFHMIN-NEXT: ret203 %a = call <vscale x 1 x half> @llvm.roundeven.nxv1f16(<vscale x 1 x half> %x)204 ret <vscale x 1 x half> %a205}206 207define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) {208; ZVFH-LABEL: roundeven_nxv2f16:209; ZVFH: # %bb.0:210; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma211; ZVFH-NEXT: vfabs.v v9, v8212; ZVFH-NEXT: li a0, 25213; ZVFH-NEXT: slli a0, a0, 10214; ZVFH-NEXT: fmv.h.x fa5, a0215; ZVFH-NEXT: vmflt.vf v0, v9, fa5216; ZVFH-NEXT: fsrmi a0, 0217; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t218; ZVFH-NEXT: fsrm a0219; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t220; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu221; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t222; ZVFH-NEXT: ret223;224; ZVFHMIN-LABEL: roundeven_nxv2f16:225; ZVFHMIN: # %bb.0:226; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma227; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8228; ZVFHMIN-NEXT: lui a0, 307200229; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma230; ZVFHMIN-NEXT: vfabs.v v8, v9231; ZVFHMIN-NEXT: fmv.w.x fa5, a0232; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5233; ZVFHMIN-NEXT: fsrmi a0, 0234; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t235; ZVFHMIN-NEXT: fsrm a0236; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t237; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu238; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t239; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma240; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9241; ZVFHMIN-NEXT: ret242 %a = call <vscale x 2 x half> @llvm.roundeven.nxv2f16(<vscale x 2 x half> %x)243 ret <vscale x 2 x half> %a244}245 246define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) {247; ZVFH-LABEL: roundeven_nxv4f16:248; ZVFH: # %bb.0:249; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma250; ZVFH-NEXT: vfabs.v v9, v8251; ZVFH-NEXT: li a0, 25252; ZVFH-NEXT: slli a0, a0, 10253; ZVFH-NEXT: fmv.h.x fa5, a0254; ZVFH-NEXT: vmflt.vf v0, v9, fa5255; ZVFH-NEXT: fsrmi a0, 0256; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t257; ZVFH-NEXT: fsrm a0258; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t259; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu260; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t261; ZVFH-NEXT: ret262;263; ZVFHMIN-LABEL: roundeven_nxv4f16:264; ZVFHMIN: # %bb.0:265; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma266; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8267; ZVFHMIN-NEXT: lui a0, 307200268; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma269; ZVFHMIN-NEXT: vfabs.v v8, v10270; ZVFHMIN-NEXT: fmv.w.x fa5, a0271; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5272; ZVFHMIN-NEXT: fsrmi a0, 0273; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t274; ZVFHMIN-NEXT: fsrm a0275; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t276; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu277; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t278; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma279; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10280; ZVFHMIN-NEXT: ret281 %a = call <vscale x 4 x half> @llvm.roundeven.nxv4f16(<vscale x 4 x half> %x)282 ret <vscale x 4 x half> %a283}284 285define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) {286; ZVFH-LABEL: roundeven_nxv8f16:287; ZVFH: # %bb.0:288; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma289; ZVFH-NEXT: vfabs.v v10, v8290; ZVFH-NEXT: li a0, 25291; ZVFH-NEXT: slli a0, a0, 10292; ZVFH-NEXT: fmv.h.x fa5, a0293; ZVFH-NEXT: vmflt.vf v0, v10, fa5294; ZVFH-NEXT: fsrmi a0, 0295; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t296; ZVFH-NEXT: fsrm a0297; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t298; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu299; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t300; ZVFH-NEXT: ret301;302; ZVFHMIN-LABEL: roundeven_nxv8f16:303; ZVFHMIN: # %bb.0:304; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma305; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8306; ZVFHMIN-NEXT: lui a0, 307200307; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma308; ZVFHMIN-NEXT: vfabs.v v8, v12309; ZVFHMIN-NEXT: fmv.w.x fa5, a0310; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5311; ZVFHMIN-NEXT: fsrmi a0, 0312; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t313; ZVFHMIN-NEXT: fsrm a0314; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t315; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu316; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t317; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma318; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12319; ZVFHMIN-NEXT: ret320 %a = call <vscale x 8 x half> @llvm.roundeven.nxv8f16(<vscale x 8 x half> %x)321 ret <vscale x 8 x half> %a322}323 324define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) {325; ZVFH-LABEL: roundeven_nxv16f16:326; ZVFH: # %bb.0:327; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma328; ZVFH-NEXT: vfabs.v v12, v8329; ZVFH-NEXT: li a0, 25330; ZVFH-NEXT: slli a0, a0, 10331; ZVFH-NEXT: fmv.h.x fa5, a0332; ZVFH-NEXT: vmflt.vf v0, v12, fa5333; ZVFH-NEXT: fsrmi a0, 0334; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t335; ZVFH-NEXT: fsrm a0336; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t337; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu338; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t339; ZVFH-NEXT: ret340;341; ZVFHMIN-LABEL: roundeven_nxv16f16:342; ZVFHMIN: # %bb.0:343; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma344; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8345; ZVFHMIN-NEXT: lui a0, 307200346; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma347; ZVFHMIN-NEXT: vfabs.v v8, v16348; ZVFHMIN-NEXT: fmv.w.x fa5, a0349; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5350; ZVFHMIN-NEXT: fsrmi a0, 0351; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t352; ZVFHMIN-NEXT: fsrm a0353; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t354; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu355; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t356; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma357; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16358; ZVFHMIN-NEXT: ret359 %a = call <vscale x 16 x half> @llvm.roundeven.nxv16f16(<vscale x 16 x half> %x)360 ret <vscale x 16 x half> %a361}362 363define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) {364; ZVFH-LABEL: roundeven_nxv32f16:365; ZVFH: # %bb.0:366; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma367; ZVFH-NEXT: vfabs.v v16, v8368; ZVFH-NEXT: li a0, 25369; ZVFH-NEXT: slli a0, a0, 10370; ZVFH-NEXT: fmv.h.x fa5, a0371; ZVFH-NEXT: vmflt.vf v0, v16, fa5372; ZVFH-NEXT: fsrmi a0, 0373; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t374; ZVFH-NEXT: fsrm a0375; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t376; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu377; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t378; ZVFH-NEXT: ret379;380; ZVFHMIN-LABEL: roundeven_nxv32f16:381; ZVFHMIN: # %bb.0:382; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma383; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8384; ZVFHMIN-NEXT: lui a0, 307200385; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma386; ZVFHMIN-NEXT: vfabs.v v24, v16387; ZVFHMIN-NEXT: fmv.w.x fa5, a0388; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5389; ZVFHMIN-NEXT: fsrmi a0, 0390; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t391; ZVFHMIN-NEXT: fsrm a0392; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t393; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu394; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t395; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma396; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12397; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma398; ZVFHMIN-NEXT: vfabs.v v8, v24399; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5400; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma401; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16402; ZVFHMIN-NEXT: fsrmi a0, 0403; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma404; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t405; ZVFHMIN-NEXT: fsrm a0406; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t407; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu408; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t409; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma410; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24411; ZVFHMIN-NEXT: ret412 %a = call <vscale x 32 x half> @llvm.roundeven.nxv32f16(<vscale x 32 x half> %x)413 ret <vscale x 32 x half> %a414}415 416define <vscale x 1 x float> @roundeven_nxv1f32(<vscale x 1 x float> %x) {417; CHECK-LABEL: roundeven_nxv1f32:418; CHECK: # %bb.0:419; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma420; CHECK-NEXT: vfabs.v v9, v8421; CHECK-NEXT: lui a0, 307200422; CHECK-NEXT: fmv.w.x fa5, a0423; CHECK-NEXT: vmflt.vf v0, v9, fa5424; CHECK-NEXT: fsrmi a0, 0425; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t426; CHECK-NEXT: fsrm a0427; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t428; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu429; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t430; CHECK-NEXT: ret431 %a = call <vscale x 1 x float> @llvm.roundeven.nxv1f32(<vscale x 1 x float> %x)432 ret <vscale x 1 x float> %a433}434 435define <vscale x 2 x float> @roundeven_nxv2f32(<vscale x 2 x float> %x) {436; CHECK-LABEL: roundeven_nxv2f32:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma439; CHECK-NEXT: vfabs.v v9, v8440; CHECK-NEXT: lui a0, 307200441; CHECK-NEXT: fmv.w.x fa5, a0442; CHECK-NEXT: vmflt.vf v0, v9, fa5443; CHECK-NEXT: fsrmi a0, 0444; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t445; CHECK-NEXT: fsrm a0446; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t447; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu448; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t449; CHECK-NEXT: ret450 %a = call <vscale x 2 x float> @llvm.roundeven.nxv2f32(<vscale x 2 x float> %x)451 ret <vscale x 2 x float> %a452}453 454define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) {455; CHECK-LABEL: roundeven_nxv4f32:456; CHECK: # %bb.0:457; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma458; CHECK-NEXT: vfabs.v v10, v8459; CHECK-NEXT: lui a0, 307200460; CHECK-NEXT: fmv.w.x fa5, a0461; CHECK-NEXT: vmflt.vf v0, v10, fa5462; CHECK-NEXT: fsrmi a0, 0463; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t464; CHECK-NEXT: fsrm a0465; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t466; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu467; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t468; CHECK-NEXT: ret469 %a = call <vscale x 4 x float> @llvm.roundeven.nxv4f32(<vscale x 4 x float> %x)470 ret <vscale x 4 x float> %a471}472 473define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) {474; CHECK-LABEL: roundeven_nxv8f32:475; CHECK: # %bb.0:476; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma477; CHECK-NEXT: vfabs.v v12, v8478; CHECK-NEXT: lui a0, 307200479; CHECK-NEXT: fmv.w.x fa5, a0480; CHECK-NEXT: vmflt.vf v0, v12, fa5481; CHECK-NEXT: fsrmi a0, 0482; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t483; CHECK-NEXT: fsrm a0484; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t485; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu486; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t487; CHECK-NEXT: ret488 %a = call <vscale x 8 x float> @llvm.roundeven.nxv8f32(<vscale x 8 x float> %x)489 ret <vscale x 8 x float> %a490}491 492define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) {493; CHECK-LABEL: roundeven_nxv16f32:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma496; CHECK-NEXT: vfabs.v v16, v8497; CHECK-NEXT: lui a0, 307200498; CHECK-NEXT: fmv.w.x fa5, a0499; CHECK-NEXT: vmflt.vf v0, v16, fa5500; CHECK-NEXT: fsrmi a0, 0501; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t502; CHECK-NEXT: fsrm a0503; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t504; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu505; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t506; CHECK-NEXT: ret507 %a = call <vscale x 16 x float> @llvm.roundeven.nxv16f32(<vscale x 16 x float> %x)508 ret <vscale x 16 x float> %a509}510 511define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {512; RV32ZVFH-LABEL: roundeven_nxv1f64:513; RV32ZVFH: # %bb.0:514; RV32ZVFH-NEXT: lui a0, %hi(.LCPI17_0)515; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)516; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma517; RV32ZVFH-NEXT: vfabs.v v9, v8518; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5519; RV32ZVFH-NEXT: fsrmi a0, 0520; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t521; RV32ZVFH-NEXT: fsrm a0522; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t523; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu524; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t525; RV32ZVFH-NEXT: ret526;527; RV64ZVFH-LABEL: roundeven_nxv1f64:528; RV64ZVFH: # %bb.0:529; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma530; RV64ZVFH-NEXT: vfabs.v v9, v8531; RV64ZVFH-NEXT: li a0, 1075532; RV64ZVFH-NEXT: slli a0, a0, 52533; RV64ZVFH-NEXT: fmv.d.x fa5, a0534; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5535; RV64ZVFH-NEXT: fsrmi a0, 0536; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t537; RV64ZVFH-NEXT: fsrm a0538; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t539; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu540; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t541; RV64ZVFH-NEXT: ret542;543; RV32ZVFHMIN-LABEL: roundeven_nxv1f64:544; RV32ZVFHMIN: # %bb.0:545; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI17_0)546; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)547; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma548; RV32ZVFHMIN-NEXT: vfabs.v v9, v8549; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5550; RV32ZVFHMIN-NEXT: fsrmi a0, 0551; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t552; RV32ZVFHMIN-NEXT: fsrm a0553; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t554; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu555; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t556; RV32ZVFHMIN-NEXT: ret557;558; RV64ZVFHMIN-LABEL: roundeven_nxv1f64:559; RV64ZVFHMIN: # %bb.0:560; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma561; RV64ZVFHMIN-NEXT: vfabs.v v9, v8562; RV64ZVFHMIN-NEXT: li a0, 1075563; RV64ZVFHMIN-NEXT: slli a0, a0, 52564; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0565; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5566; RV64ZVFHMIN-NEXT: fsrmi a0, 0567; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t568; RV64ZVFHMIN-NEXT: fsrm a0569; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t570; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu571; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t572; RV64ZVFHMIN-NEXT: ret573 %a = call <vscale x 1 x double> @llvm.roundeven.nxv1f64(<vscale x 1 x double> %x)574 ret <vscale x 1 x double> %a575}576 577define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {578; RV32ZVFH-LABEL: roundeven_nxv2f64:579; RV32ZVFH: # %bb.0:580; RV32ZVFH-NEXT: lui a0, %hi(.LCPI18_0)581; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)582; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma583; RV32ZVFH-NEXT: vfabs.v v10, v8584; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5585; RV32ZVFH-NEXT: fsrmi a0, 0586; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t587; RV32ZVFH-NEXT: fsrm a0588; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t589; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu590; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t591; RV32ZVFH-NEXT: ret592;593; RV64ZVFH-LABEL: roundeven_nxv2f64:594; RV64ZVFH: # %bb.0:595; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma596; RV64ZVFH-NEXT: vfabs.v v10, v8597; RV64ZVFH-NEXT: li a0, 1075598; RV64ZVFH-NEXT: slli a0, a0, 52599; RV64ZVFH-NEXT: fmv.d.x fa5, a0600; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5601; RV64ZVFH-NEXT: fsrmi a0, 0602; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t603; RV64ZVFH-NEXT: fsrm a0604; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t605; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu606; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t607; RV64ZVFH-NEXT: ret608;609; RV32ZVFHMIN-LABEL: roundeven_nxv2f64:610; RV32ZVFHMIN: # %bb.0:611; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI18_0)612; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)613; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma614; RV32ZVFHMIN-NEXT: vfabs.v v10, v8615; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5616; RV32ZVFHMIN-NEXT: fsrmi a0, 0617; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t618; RV32ZVFHMIN-NEXT: fsrm a0619; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t620; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu621; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t622; RV32ZVFHMIN-NEXT: ret623;624; RV64ZVFHMIN-LABEL: roundeven_nxv2f64:625; RV64ZVFHMIN: # %bb.0:626; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma627; RV64ZVFHMIN-NEXT: vfabs.v v10, v8628; RV64ZVFHMIN-NEXT: li a0, 1075629; RV64ZVFHMIN-NEXT: slli a0, a0, 52630; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0631; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5632; RV64ZVFHMIN-NEXT: fsrmi a0, 0633; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t634; RV64ZVFHMIN-NEXT: fsrm a0635; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t636; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu637; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t638; RV64ZVFHMIN-NEXT: ret639 %a = call <vscale x 2 x double> @llvm.roundeven.nxv2f64(<vscale x 2 x double> %x)640 ret <vscale x 2 x double> %a641}642 643define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {644; RV32ZVFH-LABEL: roundeven_nxv4f64:645; RV32ZVFH: # %bb.0:646; RV32ZVFH-NEXT: lui a0, %hi(.LCPI19_0)647; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)648; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma649; RV32ZVFH-NEXT: vfabs.v v12, v8650; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5651; RV32ZVFH-NEXT: fsrmi a0, 0652; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t653; RV32ZVFH-NEXT: fsrm a0654; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t655; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu656; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t657; RV32ZVFH-NEXT: ret658;659; RV64ZVFH-LABEL: roundeven_nxv4f64:660; RV64ZVFH: # %bb.0:661; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma662; RV64ZVFH-NEXT: vfabs.v v12, v8663; RV64ZVFH-NEXT: li a0, 1075664; RV64ZVFH-NEXT: slli a0, a0, 52665; RV64ZVFH-NEXT: fmv.d.x fa5, a0666; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5667; RV64ZVFH-NEXT: fsrmi a0, 0668; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t669; RV64ZVFH-NEXT: fsrm a0670; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t671; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu672; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t673; RV64ZVFH-NEXT: ret674;675; RV32ZVFHMIN-LABEL: roundeven_nxv4f64:676; RV32ZVFHMIN: # %bb.0:677; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI19_0)678; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)679; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma680; RV32ZVFHMIN-NEXT: vfabs.v v12, v8681; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5682; RV32ZVFHMIN-NEXT: fsrmi a0, 0683; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t684; RV32ZVFHMIN-NEXT: fsrm a0685; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t686; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu687; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t688; RV32ZVFHMIN-NEXT: ret689;690; RV64ZVFHMIN-LABEL: roundeven_nxv4f64:691; RV64ZVFHMIN: # %bb.0:692; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma693; RV64ZVFHMIN-NEXT: vfabs.v v12, v8694; RV64ZVFHMIN-NEXT: li a0, 1075695; RV64ZVFHMIN-NEXT: slli a0, a0, 52696; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0697; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5698; RV64ZVFHMIN-NEXT: fsrmi a0, 0699; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t700; RV64ZVFHMIN-NEXT: fsrm a0701; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t702; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu703; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t704; RV64ZVFHMIN-NEXT: ret705 %a = call <vscale x 4 x double> @llvm.roundeven.nxv4f64(<vscale x 4 x double> %x)706 ret <vscale x 4 x double> %a707}708 709define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {710; RV32ZVFH-LABEL: roundeven_nxv8f64:711; RV32ZVFH: # %bb.0:712; RV32ZVFH-NEXT: lui a0, %hi(.LCPI20_0)713; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)714; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma715; RV32ZVFH-NEXT: vfabs.v v16, v8716; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5717; RV32ZVFH-NEXT: fsrmi a0, 0718; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t719; RV32ZVFH-NEXT: fsrm a0720; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t721; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu722; RV32ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t723; RV32ZVFH-NEXT: ret724;725; RV64ZVFH-LABEL: roundeven_nxv8f64:726; RV64ZVFH: # %bb.0:727; RV64ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma728; RV64ZVFH-NEXT: vfabs.v v16, v8729; RV64ZVFH-NEXT: li a0, 1075730; RV64ZVFH-NEXT: slli a0, a0, 52731; RV64ZVFH-NEXT: fmv.d.x fa5, a0732; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5733; RV64ZVFH-NEXT: fsrmi a0, 0734; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t735; RV64ZVFH-NEXT: fsrm a0736; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t737; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu738; RV64ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t739; RV64ZVFH-NEXT: ret740;741; RV32ZVFHMIN-LABEL: roundeven_nxv8f64:742; RV32ZVFHMIN: # %bb.0:743; RV32ZVFHMIN-NEXT: lui a0, %hi(.LCPI20_0)744; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)745; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma746; RV32ZVFHMIN-NEXT: vfabs.v v16, v8747; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5748; RV32ZVFHMIN-NEXT: fsrmi a0, 0749; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t750; RV32ZVFHMIN-NEXT: fsrm a0751; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t752; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu753; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t754; RV32ZVFHMIN-NEXT: ret755;756; RV64ZVFHMIN-LABEL: roundeven_nxv8f64:757; RV64ZVFHMIN: # %bb.0:758; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma759; RV64ZVFHMIN-NEXT: vfabs.v v16, v8760; RV64ZVFHMIN-NEXT: li a0, 1075761; RV64ZVFHMIN-NEXT: slli a0, a0, 52762; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0763; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5764; RV64ZVFHMIN-NEXT: fsrmi a0, 0765; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t766; RV64ZVFHMIN-NEXT: fsrm a0767; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t768; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu769; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v16, v8, v0.t770; RV64ZVFHMIN-NEXT: ret771 %a = call <vscale x 8 x double> @llvm.roundeven.nxv8f64(<vscale x 8 x double> %x)772 ret <vscale x 8 x double> %a773}774