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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @fshr_v1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {6; CHECK-LABEL: fshr_v1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma9; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t10; CHECK-NEXT: vnot.v v11, v10, v0.t11; CHECK-NEXT: vand.vi v11, v11, 7, v0.t12; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t13; CHECK-NEXT: vand.vi v10, v10, 7, v0.t14; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t15; CHECK-NEXT: vor.vv v8, v8, v9, v0.t16; CHECK-NEXT: ret17 %res = call <vscale x 1 x i8> @llvm.vp.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 %evl)18 ret <vscale x 1 x i8> %res19}20 21define <vscale x 1 x i8> @fshl_v1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: fshl_v1i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma25; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t26; CHECK-NEXT: vnot.v v11, v10, v0.t27; CHECK-NEXT: vand.vi v11, v11, 7, v0.t28; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t29; CHECK-NEXT: vand.vi v10, v10, 7, v0.t30; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t31; CHECK-NEXT: vor.vv v8, v8, v9, v0.t32; CHECK-NEXT: ret33 %res = call <vscale x 1 x i8> @llvm.vp.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 %evl)34 ret <vscale x 1 x i8> %res35}36 37define <vscale x 2 x i8> @fshr_v2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: fshr_v2i8:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma41; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t42; CHECK-NEXT: vnot.v v11, v10, v0.t43; CHECK-NEXT: vand.vi v11, v11, 7, v0.t44; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t45; CHECK-NEXT: vand.vi v10, v10, 7, v0.t46; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t47; CHECK-NEXT: vor.vv v8, v8, v9, v0.t48; CHECK-NEXT: ret49 %res = call <vscale x 2 x i8> @llvm.vp.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 %evl)50 ret <vscale x 2 x i8> %res51}52 53define <vscale x 2 x i8> @fshl_v2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {54; CHECK-LABEL: fshl_v2i8:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma57; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t58; CHECK-NEXT: vnot.v v11, v10, v0.t59; CHECK-NEXT: vand.vi v11, v11, 7, v0.t60; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t61; CHECK-NEXT: vand.vi v10, v10, 7, v0.t62; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t63; CHECK-NEXT: vor.vv v8, v8, v9, v0.t64; CHECK-NEXT: ret65 %res = call <vscale x 2 x i8> @llvm.vp.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 %evl)66 ret <vscale x 2 x i8> %res67}68 69define <vscale x 4 x i8> @fshr_v4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {70; CHECK-LABEL: fshr_v4i8:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma73; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t74; CHECK-NEXT: vnot.v v11, v10, v0.t75; CHECK-NEXT: vand.vi v11, v11, 7, v0.t76; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t77; CHECK-NEXT: vand.vi v10, v10, 7, v0.t78; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t79; CHECK-NEXT: vor.vv v8, v8, v9, v0.t80; CHECK-NEXT: ret81 %res = call <vscale x 4 x i8> @llvm.vp.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 %evl)82 ret <vscale x 4 x i8> %res83}84 85define <vscale x 4 x i8> @fshl_v4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: fshl_v4i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma89; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t90; CHECK-NEXT: vnot.v v11, v10, v0.t91; CHECK-NEXT: vand.vi v11, v11, 7, v0.t92; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t93; CHECK-NEXT: vand.vi v10, v10, 7, v0.t94; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t95; CHECK-NEXT: vor.vv v8, v8, v9, v0.t96; CHECK-NEXT: ret97 %res = call <vscale x 4 x i8> @llvm.vp.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 %evl)98 ret <vscale x 4 x i8> %res99}100 101define <vscale x 8 x i8> @fshr_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: fshr_v8i8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma105; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t106; CHECK-NEXT: vnot.v v11, v10, v0.t107; CHECK-NEXT: vand.vi v11, v11, 7, v0.t108; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t109; CHECK-NEXT: vand.vi v10, v10, 7, v0.t110; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t111; CHECK-NEXT: vor.vv v8, v8, v9, v0.t112; CHECK-NEXT: ret113 %res = call <vscale x 8 x i8> @llvm.vp.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 %evl)114 ret <vscale x 8 x i8> %res115}116 117define <vscale x 8 x i8> @fshl_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: fshl_v8i8:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma121; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t122; CHECK-NEXT: vnot.v v11, v10, v0.t123; CHECK-NEXT: vand.vi v11, v11, 7, v0.t124; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t125; CHECK-NEXT: vand.vi v10, v10, 7, v0.t126; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t127; CHECK-NEXT: vor.vv v8, v8, v9, v0.t128; CHECK-NEXT: ret129 %res = call <vscale x 8 x i8> @llvm.vp.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 %evl)130 ret <vscale x 8 x i8> %res131}132 133define <vscale x 16 x i8> @fshr_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {134; CHECK-LABEL: fshr_v16i8:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma137; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t138; CHECK-NEXT: vnot.v v14, v12, v0.t139; CHECK-NEXT: vand.vi v14, v14, 7, v0.t140; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t141; CHECK-NEXT: vand.vi v12, v12, 7, v0.t142; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t143; CHECK-NEXT: vor.vv v8, v8, v10, v0.t144; CHECK-NEXT: ret145 %res = call <vscale x 16 x i8> @llvm.vp.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 %evl)146 ret <vscale x 16 x i8> %res147}148 149define <vscale x 16 x i8> @fshl_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {150; CHECK-LABEL: fshl_v16i8:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma153; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t154; CHECK-NEXT: vnot.v v14, v12, v0.t155; CHECK-NEXT: vand.vi v14, v14, 7, v0.t156; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t157; CHECK-NEXT: vand.vi v12, v12, 7, v0.t158; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t159; CHECK-NEXT: vor.vv v8, v8, v10, v0.t160; CHECK-NEXT: ret161 %res = call <vscale x 16 x i8> @llvm.vp.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 %evl)162 ret <vscale x 16 x i8> %res163}164 165define <vscale x 32 x i8> @fshr_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {166; CHECK-LABEL: fshr_v32i8:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma169; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t170; CHECK-NEXT: vnot.v v20, v16, v0.t171; CHECK-NEXT: vand.vi v20, v20, 7, v0.t172; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t173; CHECK-NEXT: vand.vi v16, v16, 7, v0.t174; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t175; CHECK-NEXT: vor.vv v8, v8, v12, v0.t176; CHECK-NEXT: ret177 %res = call <vscale x 32 x i8> @llvm.vp.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 %evl)178 ret <vscale x 32 x i8> %res179}180 181define <vscale x 32 x i8> @fshl_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {182; CHECK-LABEL: fshl_v32i8:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma185; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t186; CHECK-NEXT: vnot.v v20, v16, v0.t187; CHECK-NEXT: vand.vi v20, v20, 7, v0.t188; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t189; CHECK-NEXT: vand.vi v16, v16, 7, v0.t190; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t191; CHECK-NEXT: vor.vv v8, v8, v12, v0.t192; CHECK-NEXT: ret193 %res = call <vscale x 32 x i8> @llvm.vp.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 %evl)194 ret <vscale x 32 x i8> %res195}196 197define <vscale x 64 x i8> @fshr_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 zeroext %evl) {198; CHECK-LABEL: fshr_v64i8:199; CHECK: # %bb.0:200; CHECK-NEXT: addi sp, sp, -16201; CHECK-NEXT: .cfi_def_cfa_offset 16202; CHECK-NEXT: csrr a2, vlenb203; CHECK-NEXT: slli a2, a2, 3204; CHECK-NEXT: sub sp, sp, a2205; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb206; CHECK-NEXT: addi a2, sp, 16207; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill208; CHECK-NEXT: vl8r.v v24, (a0)209; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma210; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t211; CHECK-NEXT: vnot.v v8, v24, v0.t212; CHECK-NEXT: vand.vi v8, v8, 7, v0.t213; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t214; CHECK-NEXT: vand.vi v16, v24, 7, v0.t215; CHECK-NEXT: addi a0, sp, 16216; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload217; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t218; CHECK-NEXT: vor.vv v8, v8, v16, v0.t219; CHECK-NEXT: csrr a0, vlenb220; CHECK-NEXT: slli a0, a0, 3221; CHECK-NEXT: add sp, sp, a0222; CHECK-NEXT: .cfi_def_cfa sp, 16223; CHECK-NEXT: addi sp, sp, 16224; CHECK-NEXT: .cfi_def_cfa_offset 0225; CHECK-NEXT: ret226 %res = call <vscale x 64 x i8> @llvm.vp.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 %evl)227 ret <vscale x 64 x i8> %res228}229 230define <vscale x 64 x i8> @fshl_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 zeroext %evl) {231; CHECK-LABEL: fshl_v64i8:232; CHECK: # %bb.0:233; CHECK-NEXT: addi sp, sp, -16234; CHECK-NEXT: .cfi_def_cfa_offset 16235; CHECK-NEXT: csrr a2, vlenb236; CHECK-NEXT: slli a2, a2, 3237; CHECK-NEXT: sub sp, sp, a2238; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb239; CHECK-NEXT: addi a2, sp, 16240; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill241; CHECK-NEXT: vl8r.v v24, (a0)242; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma243; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t244; CHECK-NEXT: vnot.v v8, v24, v0.t245; CHECK-NEXT: vand.vi v8, v8, 7, v0.t246; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t247; CHECK-NEXT: vand.vi v16, v24, 7, v0.t248; CHECK-NEXT: addi a0, sp, 16249; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload250; CHECK-NEXT: vsll.vv v16, v24, v16, v0.t251; CHECK-NEXT: vor.vv v8, v16, v8, v0.t252; CHECK-NEXT: csrr a0, vlenb253; CHECK-NEXT: slli a0, a0, 3254; CHECK-NEXT: add sp, sp, a0255; CHECK-NEXT: .cfi_def_cfa sp, 16256; CHECK-NEXT: addi sp, sp, 16257; CHECK-NEXT: .cfi_def_cfa_offset 0258; CHECK-NEXT: ret259 %res = call <vscale x 64 x i8> @llvm.vp.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 %evl)260 ret <vscale x 64 x i8> %res261}262 263define <vscale x 1 x i16> @fshr_v1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {264; CHECK-LABEL: fshr_v1i16:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma267; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t268; CHECK-NEXT: vnot.v v11, v10, v0.t269; CHECK-NEXT: vand.vi v11, v11, 15, v0.t270; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t271; CHECK-NEXT: vand.vi v10, v10, 15, v0.t272; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t273; CHECK-NEXT: vor.vv v8, v8, v9, v0.t274; CHECK-NEXT: ret275 %res = call <vscale x 1 x i16> @llvm.vp.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 %evl)276 ret <vscale x 1 x i16> %res277}278 279define <vscale x 1 x i16> @fshl_v1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {280; CHECK-LABEL: fshl_v1i16:281; CHECK: # %bb.0:282; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma283; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t284; CHECK-NEXT: vnot.v v11, v10, v0.t285; CHECK-NEXT: vand.vi v11, v11, 15, v0.t286; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t287; CHECK-NEXT: vand.vi v10, v10, 15, v0.t288; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t289; CHECK-NEXT: vor.vv v8, v8, v9, v0.t290; CHECK-NEXT: ret291 %res = call <vscale x 1 x i16> @llvm.vp.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 %evl)292 ret <vscale x 1 x i16> %res293}294 295define <vscale x 2 x i16> @fshr_v2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {296; CHECK-LABEL: fshr_v2i16:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma299; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t300; CHECK-NEXT: vnot.v v11, v10, v0.t301; CHECK-NEXT: vand.vi v11, v11, 15, v0.t302; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t303; CHECK-NEXT: vand.vi v10, v10, 15, v0.t304; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t305; CHECK-NEXT: vor.vv v8, v8, v9, v0.t306; CHECK-NEXT: ret307 %res = call <vscale x 2 x i16> @llvm.vp.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 %evl)308 ret <vscale x 2 x i16> %res309}310 311define <vscale x 2 x i16> @fshl_v2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {312; CHECK-LABEL: fshl_v2i16:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma315; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t316; CHECK-NEXT: vnot.v v11, v10, v0.t317; CHECK-NEXT: vand.vi v11, v11, 15, v0.t318; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t319; CHECK-NEXT: vand.vi v10, v10, 15, v0.t320; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t321; CHECK-NEXT: vor.vv v8, v8, v9, v0.t322; CHECK-NEXT: ret323 %res = call <vscale x 2 x i16> @llvm.vp.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 %evl)324 ret <vscale x 2 x i16> %res325}326 327define <vscale x 4 x i16> @fshr_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {328; CHECK-LABEL: fshr_v4i16:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma331; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t332; CHECK-NEXT: vnot.v v11, v10, v0.t333; CHECK-NEXT: vand.vi v11, v11, 15, v0.t334; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t335; CHECK-NEXT: vand.vi v10, v10, 15, v0.t336; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t337; CHECK-NEXT: vor.vv v8, v8, v9, v0.t338; CHECK-NEXT: ret339 %res = call <vscale x 4 x i16> @llvm.vp.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 %evl)340 ret <vscale x 4 x i16> %res341}342 343define <vscale x 4 x i16> @fshl_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {344; CHECK-LABEL: fshl_v4i16:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma347; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t348; CHECK-NEXT: vnot.v v11, v10, v0.t349; CHECK-NEXT: vand.vi v11, v11, 15, v0.t350; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t351; CHECK-NEXT: vand.vi v10, v10, 15, v0.t352; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t353; CHECK-NEXT: vor.vv v8, v8, v9, v0.t354; CHECK-NEXT: ret355 %res = call <vscale x 4 x i16> @llvm.vp.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 %evl)356 ret <vscale x 4 x i16> %res357}358 359define <vscale x 8 x i16> @fshr_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: fshr_v8i16:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma363; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t364; CHECK-NEXT: vnot.v v14, v12, v0.t365; CHECK-NEXT: vand.vi v14, v14, 15, v0.t366; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t367; CHECK-NEXT: vand.vi v12, v12, 15, v0.t368; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t369; CHECK-NEXT: vor.vv v8, v8, v10, v0.t370; CHECK-NEXT: ret371 %res = call <vscale x 8 x i16> @llvm.vp.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 %evl)372 ret <vscale x 8 x i16> %res373}374 375define <vscale x 8 x i16> @fshl_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {376; CHECK-LABEL: fshl_v8i16:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma379; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t380; CHECK-NEXT: vnot.v v14, v12, v0.t381; CHECK-NEXT: vand.vi v14, v14, 15, v0.t382; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t383; CHECK-NEXT: vand.vi v12, v12, 15, v0.t384; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t385; CHECK-NEXT: vor.vv v8, v8, v10, v0.t386; CHECK-NEXT: ret387 %res = call <vscale x 8 x i16> @llvm.vp.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 %evl)388 ret <vscale x 8 x i16> %res389}390 391define <vscale x 16 x i16> @fshr_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {392; CHECK-LABEL: fshr_v16i16:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma395; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t396; CHECK-NEXT: vnot.v v20, v16, v0.t397; CHECK-NEXT: vand.vi v20, v20, 15, v0.t398; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t399; CHECK-NEXT: vand.vi v16, v16, 15, v0.t400; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t401; CHECK-NEXT: vor.vv v8, v8, v12, v0.t402; CHECK-NEXT: ret403 %res = call <vscale x 16 x i16> @llvm.vp.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 %evl)404 ret <vscale x 16 x i16> %res405}406 407define <vscale x 16 x i16> @fshl_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {408; CHECK-LABEL: fshl_v16i16:409; CHECK: # %bb.0:410; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma411; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t412; CHECK-NEXT: vnot.v v20, v16, v0.t413; CHECK-NEXT: vand.vi v20, v20, 15, v0.t414; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t415; CHECK-NEXT: vand.vi v16, v16, 15, v0.t416; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t417; CHECK-NEXT: vor.vv v8, v8, v12, v0.t418; CHECK-NEXT: ret419 %res = call <vscale x 16 x i16> @llvm.vp.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 %evl)420 ret <vscale x 16 x i16> %res421}422 423define <vscale x 32 x i16> @fshr_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {424; CHECK-LABEL: fshr_v32i16:425; CHECK: # %bb.0:426; CHECK-NEXT: addi sp, sp, -16427; CHECK-NEXT: .cfi_def_cfa_offset 16428; CHECK-NEXT: csrr a2, vlenb429; CHECK-NEXT: slli a2, a2, 3430; CHECK-NEXT: sub sp, sp, a2431; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb432; CHECK-NEXT: addi a2, sp, 16433; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill434; CHECK-NEXT: vl8re16.v v24, (a0)435; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma436; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t437; CHECK-NEXT: vnot.v v8, v24, v0.t438; CHECK-NEXT: vand.vi v8, v8, 15, v0.t439; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t440; CHECK-NEXT: vand.vi v16, v24, 15, v0.t441; CHECK-NEXT: addi a0, sp, 16442; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload443; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t444; CHECK-NEXT: vor.vv v8, v8, v16, v0.t445; CHECK-NEXT: csrr a0, vlenb446; CHECK-NEXT: slli a0, a0, 3447; CHECK-NEXT: add sp, sp, a0448; CHECK-NEXT: .cfi_def_cfa sp, 16449; CHECK-NEXT: addi sp, sp, 16450; CHECK-NEXT: .cfi_def_cfa_offset 0451; CHECK-NEXT: ret452 %res = call <vscale x 32 x i16> @llvm.vp.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 %evl)453 ret <vscale x 32 x i16> %res454}455 456define <vscale x 32 x i16> @fshl_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {457; CHECK-LABEL: fshl_v32i16:458; CHECK: # %bb.0:459; CHECK-NEXT: addi sp, sp, -16460; CHECK-NEXT: .cfi_def_cfa_offset 16461; CHECK-NEXT: csrr a2, vlenb462; CHECK-NEXT: slli a2, a2, 3463; CHECK-NEXT: sub sp, sp, a2464; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb465; CHECK-NEXT: addi a2, sp, 16466; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill467; CHECK-NEXT: vl8re16.v v24, (a0)468; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma469; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t470; CHECK-NEXT: vnot.v v8, v24, v0.t471; CHECK-NEXT: vand.vi v8, v8, 15, v0.t472; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t473; CHECK-NEXT: vand.vi v16, v24, 15, v0.t474; CHECK-NEXT: addi a0, sp, 16475; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload476; CHECK-NEXT: vsll.vv v16, v24, v16, v0.t477; CHECK-NEXT: vor.vv v8, v16, v8, v0.t478; CHECK-NEXT: csrr a0, vlenb479; CHECK-NEXT: slli a0, a0, 3480; CHECK-NEXT: add sp, sp, a0481; CHECK-NEXT: .cfi_def_cfa sp, 16482; CHECK-NEXT: addi sp, sp, 16483; CHECK-NEXT: .cfi_def_cfa_offset 0484; CHECK-NEXT: ret485 %res = call <vscale x 32 x i16> @llvm.vp.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 %evl)486 ret <vscale x 32 x i16> %res487}488 489define <vscale x 1 x i32> @fshr_v1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {490; CHECK-LABEL: fshr_v1i32:491; CHECK: # %bb.0:492; CHECK-NEXT: li a1, 31493; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma494; CHECK-NEXT: vand.vx v11, v10, a1, v0.t495; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t496; CHECK-NEXT: vnot.v v10, v10, v0.t497; CHECK-NEXT: vand.vx v10, v10, a1, v0.t498; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t499; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t500; CHECK-NEXT: vor.vv v8, v8, v9, v0.t501; CHECK-NEXT: ret502 %res = call <vscale x 1 x i32> @llvm.vp.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 %evl)503 ret <vscale x 1 x i32> %res504}505 506define <vscale x 1 x i32> @fshl_v1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {507; CHECK-LABEL: fshl_v1i32:508; CHECK: # %bb.0:509; CHECK-NEXT: li a1, 31510; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma511; CHECK-NEXT: vand.vx v11, v10, a1, v0.t512; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t513; CHECK-NEXT: vnot.v v10, v10, v0.t514; CHECK-NEXT: vand.vx v10, v10, a1, v0.t515; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t516; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t517; CHECK-NEXT: vor.vv v8, v8, v9, v0.t518; CHECK-NEXT: ret519 %res = call <vscale x 1 x i32> @llvm.vp.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 %evl)520 ret <vscale x 1 x i32> %res521}522 523define <vscale x 2 x i32> @fshr_v2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {524; CHECK-LABEL: fshr_v2i32:525; CHECK: # %bb.0:526; CHECK-NEXT: li a1, 31527; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma528; CHECK-NEXT: vand.vx v11, v10, a1, v0.t529; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t530; CHECK-NEXT: vnot.v v10, v10, v0.t531; CHECK-NEXT: vand.vx v10, v10, a1, v0.t532; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t533; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t534; CHECK-NEXT: vor.vv v8, v8, v9, v0.t535; CHECK-NEXT: ret536 %res = call <vscale x 2 x i32> @llvm.vp.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 %evl)537 ret <vscale x 2 x i32> %res538}539 540define <vscale x 2 x i32> @fshl_v2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {541; CHECK-LABEL: fshl_v2i32:542; CHECK: # %bb.0:543; CHECK-NEXT: li a1, 31544; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma545; CHECK-NEXT: vand.vx v11, v10, a1, v0.t546; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t547; CHECK-NEXT: vnot.v v10, v10, v0.t548; CHECK-NEXT: vand.vx v10, v10, a1, v0.t549; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t550; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t551; CHECK-NEXT: vor.vv v8, v8, v9, v0.t552; CHECK-NEXT: ret553 %res = call <vscale x 2 x i32> @llvm.vp.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 %evl)554 ret <vscale x 2 x i32> %res555}556 557define <vscale x 4 x i32> @fshr_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {558; CHECK-LABEL: fshr_v4i32:559; CHECK: # %bb.0:560; CHECK-NEXT: li a1, 31561; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma562; CHECK-NEXT: vand.vx v14, v12, a1, v0.t563; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t564; CHECK-NEXT: vnot.v v12, v12, v0.t565; CHECK-NEXT: vand.vx v12, v12, a1, v0.t566; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t567; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t568; CHECK-NEXT: vor.vv v8, v8, v10, v0.t569; CHECK-NEXT: ret570 %res = call <vscale x 4 x i32> @llvm.vp.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 %evl)571 ret <vscale x 4 x i32> %res572}573 574define <vscale x 4 x i32> @fshl_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {575; CHECK-LABEL: fshl_v4i32:576; CHECK: # %bb.0:577; CHECK-NEXT: li a1, 31578; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma579; CHECK-NEXT: vand.vx v14, v12, a1, v0.t580; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t581; CHECK-NEXT: vnot.v v12, v12, v0.t582; CHECK-NEXT: vand.vx v12, v12, a1, v0.t583; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t584; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t585; CHECK-NEXT: vor.vv v8, v8, v10, v0.t586; CHECK-NEXT: ret587 %res = call <vscale x 4 x i32> @llvm.vp.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 %evl)588 ret <vscale x 4 x i32> %res589}590 591define <vscale x 8 x i32> @fshr_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {592; CHECK-LABEL: fshr_v8i32:593; CHECK: # %bb.0:594; CHECK-NEXT: li a1, 31595; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma596; CHECK-NEXT: vand.vx v20, v16, a1, v0.t597; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t598; CHECK-NEXT: vnot.v v16, v16, v0.t599; CHECK-NEXT: vand.vx v16, v16, a1, v0.t600; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t601; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t602; CHECK-NEXT: vor.vv v8, v8, v12, v0.t603; CHECK-NEXT: ret604 %res = call <vscale x 8 x i32> @llvm.vp.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 %evl)605 ret <vscale x 8 x i32> %res606}607 608define <vscale x 8 x i32> @fshl_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {609; CHECK-LABEL: fshl_v8i32:610; CHECK: # %bb.0:611; CHECK-NEXT: li a1, 31612; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma613; CHECK-NEXT: vand.vx v20, v16, a1, v0.t614; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t615; CHECK-NEXT: vnot.v v16, v16, v0.t616; CHECK-NEXT: vand.vx v16, v16, a1, v0.t617; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t618; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t619; CHECK-NEXT: vor.vv v8, v8, v12, v0.t620; CHECK-NEXT: ret621 %res = call <vscale x 8 x i32> @llvm.vp.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 %evl)622 ret <vscale x 8 x i32> %res623}624 625define <vscale x 16 x i32> @fshr_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {626; CHECK-LABEL: fshr_v16i32:627; CHECK: # %bb.0:628; CHECK-NEXT: addi sp, sp, -16629; CHECK-NEXT: .cfi_def_cfa_offset 16630; CHECK-NEXT: csrr a2, vlenb631; CHECK-NEXT: slli a2, a2, 3632; CHECK-NEXT: sub sp, sp, a2633; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb634; CHECK-NEXT: addi a2, sp, 16635; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill636; CHECK-NEXT: vl8re32.v v24, (a0)637; CHECK-NEXT: li a0, 31638; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma639; CHECK-NEXT: vand.vx v8, v24, a0, v0.t640; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t641; CHECK-NEXT: vnot.v v8, v24, v0.t642; CHECK-NEXT: vand.vx v8, v8, a0, v0.t643; CHECK-NEXT: addi a0, sp, 16644; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload645; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t646; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t647; CHECK-NEXT: vor.vv v8, v8, v16, v0.t648; CHECK-NEXT: csrr a0, vlenb649; CHECK-NEXT: slli a0, a0, 3650; CHECK-NEXT: add sp, sp, a0651; CHECK-NEXT: .cfi_def_cfa sp, 16652; CHECK-NEXT: addi sp, sp, 16653; CHECK-NEXT: .cfi_def_cfa_offset 0654; CHECK-NEXT: ret655 %res = call <vscale x 16 x i32> @llvm.vp.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 %evl)656 ret <vscale x 16 x i32> %res657}658 659define <vscale x 16 x i32> @fshl_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {660; CHECK-LABEL: fshl_v16i32:661; CHECK: # %bb.0:662; CHECK-NEXT: addi sp, sp, -16663; CHECK-NEXT: .cfi_def_cfa_offset 16664; CHECK-NEXT: csrr a2, vlenb665; CHECK-NEXT: slli a2, a2, 3666; CHECK-NEXT: sub sp, sp, a2667; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb668; CHECK-NEXT: addi a2, sp, 16669; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill670; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma671; CHECK-NEXT: vmv8r.v v16, v8672; CHECK-NEXT: vl8re32.v v24, (a0)673; CHECK-NEXT: li a0, 31674; CHECK-NEXT: vand.vx v8, v24, a0, v0.t675; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t676; CHECK-NEXT: vnot.v v16, v24, v0.t677; CHECK-NEXT: vand.vx v16, v16, a0, v0.t678; CHECK-NEXT: addi a0, sp, 16679; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload680; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t681; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t682; CHECK-NEXT: vor.vv v8, v8, v16, v0.t683; CHECK-NEXT: csrr a0, vlenb684; CHECK-NEXT: slli a0, a0, 3685; CHECK-NEXT: add sp, sp, a0686; CHECK-NEXT: .cfi_def_cfa sp, 16687; CHECK-NEXT: addi sp, sp, 16688; CHECK-NEXT: .cfi_def_cfa_offset 0689; CHECK-NEXT: ret690 %res = call <vscale x 16 x i32> @llvm.vp.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 %evl)691 ret <vscale x 16 x i32> %res692}693 694define <vscale x 1 x i64> @fshr_v1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {695; CHECK-LABEL: fshr_v1i64:696; CHECK: # %bb.0:697; CHECK-NEXT: li a1, 63698; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma699; CHECK-NEXT: vand.vx v11, v10, a1, v0.t700; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t701; CHECK-NEXT: vnot.v v10, v10, v0.t702; CHECK-NEXT: vand.vx v10, v10, a1, v0.t703; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t704; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t705; CHECK-NEXT: vor.vv v8, v8, v9, v0.t706; CHECK-NEXT: ret707 %res = call <vscale x 1 x i64> @llvm.vp.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 %evl)708 ret <vscale x 1 x i64> %res709}710 711define <vscale x 1 x i64> @fshl_v1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {712; CHECK-LABEL: fshl_v1i64:713; CHECK: # %bb.0:714; CHECK-NEXT: li a1, 63715; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma716; CHECK-NEXT: vand.vx v11, v10, a1, v0.t717; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t718; CHECK-NEXT: vnot.v v10, v10, v0.t719; CHECK-NEXT: vand.vx v10, v10, a1, v0.t720; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t721; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t722; CHECK-NEXT: vor.vv v8, v8, v9, v0.t723; CHECK-NEXT: ret724 %res = call <vscale x 1 x i64> @llvm.vp.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 %evl)725 ret <vscale x 1 x i64> %res726}727 728define <vscale x 2 x i64> @fshr_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {729; CHECK-LABEL: fshr_v2i64:730; CHECK: # %bb.0:731; CHECK-NEXT: li a1, 63732; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma733; CHECK-NEXT: vand.vx v14, v12, a1, v0.t734; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t735; CHECK-NEXT: vnot.v v12, v12, v0.t736; CHECK-NEXT: vand.vx v12, v12, a1, v0.t737; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t738; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t739; CHECK-NEXT: vor.vv v8, v8, v10, v0.t740; CHECK-NEXT: ret741 %res = call <vscale x 2 x i64> @llvm.vp.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 %evl)742 ret <vscale x 2 x i64> %res743}744 745define <vscale x 2 x i64> @fshl_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {746; CHECK-LABEL: fshl_v2i64:747; CHECK: # %bb.0:748; CHECK-NEXT: li a1, 63749; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma750; CHECK-NEXT: vand.vx v14, v12, a1, v0.t751; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t752; CHECK-NEXT: vnot.v v12, v12, v0.t753; CHECK-NEXT: vand.vx v12, v12, a1, v0.t754; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t755; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t756; CHECK-NEXT: vor.vv v8, v8, v10, v0.t757; CHECK-NEXT: ret758 %res = call <vscale x 2 x i64> @llvm.vp.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 %evl)759 ret <vscale x 2 x i64> %res760}761 762define <vscale x 4 x i64> @fshr_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {763; CHECK-LABEL: fshr_v4i64:764; CHECK: # %bb.0:765; CHECK-NEXT: li a1, 63766; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma767; CHECK-NEXT: vand.vx v20, v16, a1, v0.t768; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t769; CHECK-NEXT: vnot.v v16, v16, v0.t770; CHECK-NEXT: vand.vx v16, v16, a1, v0.t771; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t772; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t773; CHECK-NEXT: vor.vv v8, v8, v12, v0.t774; CHECK-NEXT: ret775 %res = call <vscale x 4 x i64> @llvm.vp.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 %evl)776 ret <vscale x 4 x i64> %res777}778 779define <vscale x 4 x i64> @fshl_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {780; CHECK-LABEL: fshl_v4i64:781; CHECK: # %bb.0:782; CHECK-NEXT: li a1, 63783; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma784; CHECK-NEXT: vand.vx v20, v16, a1, v0.t785; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t786; CHECK-NEXT: vnot.v v16, v16, v0.t787; CHECK-NEXT: vand.vx v16, v16, a1, v0.t788; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t789; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t790; CHECK-NEXT: vor.vv v8, v8, v12, v0.t791; CHECK-NEXT: ret792 %res = call <vscale x 4 x i64> @llvm.vp.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 %evl)793 ret <vscale x 4 x i64> %res794}795 796define <vscale x 7 x i64> @fshr_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 zeroext %evl) {797; CHECK-LABEL: fshr_v7i64:798; CHECK: # %bb.0:799; CHECK-NEXT: addi sp, sp, -16800; CHECK-NEXT: .cfi_def_cfa_offset 16801; CHECK-NEXT: csrr a2, vlenb802; CHECK-NEXT: slli a2, a2, 3803; CHECK-NEXT: sub sp, sp, a2804; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb805; CHECK-NEXT: addi a2, sp, 16806; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill807; CHECK-NEXT: vl8re64.v v24, (a0)808; CHECK-NEXT: li a0, 63809; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma810; CHECK-NEXT: vand.vx v8, v24, a0, v0.t811; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t812; CHECK-NEXT: vnot.v v8, v24, v0.t813; CHECK-NEXT: vand.vx v8, v8, a0, v0.t814; CHECK-NEXT: addi a0, sp, 16815; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload816; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t817; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t818; CHECK-NEXT: vor.vv v8, v8, v16, v0.t819; CHECK-NEXT: csrr a0, vlenb820; CHECK-NEXT: slli a0, a0, 3821; CHECK-NEXT: add sp, sp, a0822; CHECK-NEXT: .cfi_def_cfa sp, 16823; CHECK-NEXT: addi sp, sp, 16824; CHECK-NEXT: .cfi_def_cfa_offset 0825; CHECK-NEXT: ret826 %res = call <vscale x 7 x i64> @llvm.vp.fshr.nxv7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 %evl)827 ret <vscale x 7 x i64> %res828}829 830define <vscale x 7 x i64> @fshl_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 zeroext %evl) {831; CHECK-LABEL: fshl_v7i64:832; CHECK: # %bb.0:833; CHECK-NEXT: addi sp, sp, -16834; CHECK-NEXT: .cfi_def_cfa_offset 16835; CHECK-NEXT: csrr a2, vlenb836; CHECK-NEXT: slli a2, a2, 3837; CHECK-NEXT: sub sp, sp, a2838; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb839; CHECK-NEXT: addi a2, sp, 16840; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill841; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma842; CHECK-NEXT: vmv8r.v v16, v8843; CHECK-NEXT: vl8re64.v v24, (a0)844; CHECK-NEXT: li a0, 63845; CHECK-NEXT: vand.vx v8, v24, a0, v0.t846; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t847; CHECK-NEXT: vnot.v v16, v24, v0.t848; CHECK-NEXT: vand.vx v16, v16, a0, v0.t849; CHECK-NEXT: addi a0, sp, 16850; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload851; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t852; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t853; CHECK-NEXT: vor.vv v8, v8, v16, v0.t854; CHECK-NEXT: csrr a0, vlenb855; CHECK-NEXT: slli a0, a0, 3856; CHECK-NEXT: add sp, sp, a0857; CHECK-NEXT: .cfi_def_cfa sp, 16858; CHECK-NEXT: addi sp, sp, 16859; CHECK-NEXT: .cfi_def_cfa_offset 0860; CHECK-NEXT: ret861 %res = call <vscale x 7 x i64> @llvm.vp.fshl.nxv7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 %evl)862 ret <vscale x 7 x i64> %res863}864 865define <vscale x 8 x i64> @fshr_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {866; CHECK-LABEL: fshr_v8i64:867; CHECK: # %bb.0:868; CHECK-NEXT: addi sp, sp, -16869; CHECK-NEXT: .cfi_def_cfa_offset 16870; CHECK-NEXT: csrr a2, vlenb871; CHECK-NEXT: slli a2, a2, 3872; CHECK-NEXT: sub sp, sp, a2873; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb874; CHECK-NEXT: addi a2, sp, 16875; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill876; CHECK-NEXT: vl8re64.v v24, (a0)877; CHECK-NEXT: li a0, 63878; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma879; CHECK-NEXT: vand.vx v8, v24, a0, v0.t880; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t881; CHECK-NEXT: vnot.v v8, v24, v0.t882; CHECK-NEXT: vand.vx v8, v8, a0, v0.t883; CHECK-NEXT: addi a0, sp, 16884; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload885; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t886; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t887; CHECK-NEXT: vor.vv v8, v8, v16, v0.t888; CHECK-NEXT: csrr a0, vlenb889; CHECK-NEXT: slli a0, a0, 3890; CHECK-NEXT: add sp, sp, a0891; CHECK-NEXT: .cfi_def_cfa sp, 16892; CHECK-NEXT: addi sp, sp, 16893; CHECK-NEXT: .cfi_def_cfa_offset 0894; CHECK-NEXT: ret895 %res = call <vscale x 8 x i64> @llvm.vp.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 %evl)896 ret <vscale x 8 x i64> %res897}898 899define <vscale x 8 x i64> @fshl_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {900; CHECK-LABEL: fshl_v8i64:901; CHECK: # %bb.0:902; CHECK-NEXT: addi sp, sp, -16903; CHECK-NEXT: .cfi_def_cfa_offset 16904; CHECK-NEXT: csrr a2, vlenb905; CHECK-NEXT: slli a2, a2, 3906; CHECK-NEXT: sub sp, sp, a2907; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb908; CHECK-NEXT: addi a2, sp, 16909; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill910; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma911; CHECK-NEXT: vmv8r.v v16, v8912; CHECK-NEXT: vl8re64.v v24, (a0)913; CHECK-NEXT: li a0, 63914; CHECK-NEXT: vand.vx v8, v24, a0, v0.t915; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t916; CHECK-NEXT: vnot.v v16, v24, v0.t917; CHECK-NEXT: vand.vx v16, v16, a0, v0.t918; CHECK-NEXT: addi a0, sp, 16919; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload920; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t921; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t922; CHECK-NEXT: vor.vv v8, v8, v16, v0.t923; CHECK-NEXT: csrr a0, vlenb924; CHECK-NEXT: slli a0, a0, 3925; CHECK-NEXT: add sp, sp, a0926; CHECK-NEXT: .cfi_def_cfa sp, 16927; CHECK-NEXT: addi sp, sp, 16928; CHECK-NEXT: .cfi_def_cfa_offset 0929; CHECK-NEXT: ret930 %res = call <vscale x 8 x i64> @llvm.vp.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 %evl)931 ret <vscale x 8 x i64> %res932}933 934define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {935; CHECK-LABEL: fshr_v16i64:936; CHECK: # %bb.0:937; CHECK-NEXT: addi sp, sp, -16938; CHECK-NEXT: .cfi_def_cfa_offset 16939; CHECK-NEXT: csrr a1, vlenb940; CHECK-NEXT: slli a1, a1, 5941; CHECK-NEXT: sub sp, sp, a1942; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb943; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma944; CHECK-NEXT: vmv1r.v v7, v0945; CHECK-NEXT: csrr a1, vlenb946; CHECK-NEXT: slli a1, a1, 4947; CHECK-NEXT: add a1, sp, a1948; CHECK-NEXT: addi a1, a1, 16949; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill950; CHECK-NEXT: csrr a1, vlenb951; CHECK-NEXT: li a3, 24952; CHECK-NEXT: mul a1, a1, a3953; CHECK-NEXT: add a1, sp, a1954; CHECK-NEXT: addi a1, a1, 16955; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill956; CHECK-NEXT: csrr a1, vlenb957; CHECK-NEXT: slli a3, a1, 3958; CHECK-NEXT: sub a5, a4, a1959; CHECK-NEXT: add a6, a2, a3960; CHECK-NEXT: vl8re64.v v8, (a6)961; CHECK-NEXT: sltu a6, a4, a5962; CHECK-NEXT: addi a6, a6, -1963; CHECK-NEXT: and a5, a6, a5964; CHECK-NEXT: srli a6, a1, 3965; CHECK-NEXT: add a3, a0, a3966; CHECK-NEXT: vl8re64.v v16, (a3)967; CHECK-NEXT: vslidedown.vx v0, v0, a6968; CHECK-NEXT: li a3, 63969; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma970; CHECK-NEXT: vand.vx v24, v8, a3, v0.t971; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t972; CHECK-NEXT: addi a5, sp, 16973; CHECK-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill974; CHECK-NEXT: vnot.v v8, v8, v0.t975; CHECK-NEXT: vand.vx v16, v8, a3, v0.t976; CHECK-NEXT: vl8re64.v v8, (a0)977; CHECK-NEXT: csrr a0, vlenb978; CHECK-NEXT: slli a0, a0, 3979; CHECK-NEXT: add a0, sp, a0980; CHECK-NEXT: addi a0, a0, 16981; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill982; CHECK-NEXT: vl8re64.v v24, (a2)983; CHECK-NEXT: csrr a0, vlenb984; CHECK-NEXT: slli a0, a0, 4985; CHECK-NEXT: add a0, sp, a0986; CHECK-NEXT: addi a0, a0, 16987; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload988; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t989; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t990; CHECK-NEXT: addi a0, sp, 16991; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload992; CHECK-NEXT: vor.vv v8, v8, v16, v0.t993; CHECK-NEXT: csrr a0, vlenb994; CHECK-NEXT: slli a0, a0, 4995; CHECK-NEXT: add a0, sp, a0996; CHECK-NEXT: addi a0, a0, 16997; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill998; CHECK-NEXT: bltu a4, a1, .LBB46_2999; CHECK-NEXT: # %bb.1:1000; CHECK-NEXT: mv a4, a11001; CHECK-NEXT: .LBB46_2:1002; CHECK-NEXT: vmv1r.v v0, v71003; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma1004; CHECK-NEXT: vand.vx v8, v24, a3, v0.t1005; CHECK-NEXT: csrr a0, vlenb1006; CHECK-NEXT: slli a0, a0, 31007; CHECK-NEXT: add a0, sp, a01008; CHECK-NEXT: addi a0, a0, 161009; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1010; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t1011; CHECK-NEXT: vnot.v v24, v24, v0.t1012; CHECK-NEXT: vand.vx v24, v24, a3, v0.t1013; CHECK-NEXT: csrr a0, vlenb1014; CHECK-NEXT: li a1, 241015; CHECK-NEXT: mul a0, a0, a11016; CHECK-NEXT: add a0, sp, a01017; CHECK-NEXT: addi a0, a0, 161018; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1019; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t1020; CHECK-NEXT: vsll.vv v8, v8, v24, v0.t1021; CHECK-NEXT: vor.vv v8, v8, v16, v0.t1022; CHECK-NEXT: csrr a0, vlenb1023; CHECK-NEXT: slli a0, a0, 41024; CHECK-NEXT: add a0, sp, a01025; CHECK-NEXT: addi a0, a0, 161026; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1027; CHECK-NEXT: csrr a0, vlenb1028; CHECK-NEXT: slli a0, a0, 51029; CHECK-NEXT: add sp, sp, a01030; CHECK-NEXT: .cfi_def_cfa sp, 161031; CHECK-NEXT: addi sp, sp, 161032; CHECK-NEXT: .cfi_def_cfa_offset 01033; CHECK-NEXT: ret1034 %res = call <vscale x 16 x i64> @llvm.vp.fshr.nxv16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 %evl)1035 ret <vscale x 16 x i64> %res1036}1037 1038define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {1039; CHECK-LABEL: fshl_v16i64:1040; CHECK: # %bb.0:1041; CHECK-NEXT: addi sp, sp, -161042; CHECK-NEXT: .cfi_def_cfa_offset 161043; CHECK-NEXT: csrr a1, vlenb1044; CHECK-NEXT: li a3, 241045; CHECK-NEXT: mul a1, a1, a31046; CHECK-NEXT: sub sp, sp, a11047; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1048; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1049; CHECK-NEXT: vmv1r.v v7, v01050; CHECK-NEXT: csrr a1, vlenb1051; CHECK-NEXT: slli a1, a1, 41052; CHECK-NEXT: add a1, sp, a11053; CHECK-NEXT: addi a1, a1, 161054; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1055; CHECK-NEXT: csrr a1, vlenb1056; CHECK-NEXT: slli a5, a1, 31057; CHECK-NEXT: srli a3, a1, 31058; CHECK-NEXT: sub a6, a4, a11059; CHECK-NEXT: vslidedown.vx v0, v0, a31060; CHECK-NEXT: add a3, a2, a51061; CHECK-NEXT: vl8re64.v v8, (a3)1062; CHECK-NEXT: sltu a3, a4, a61063; CHECK-NEXT: addi a3, a3, -11064; CHECK-NEXT: and a6, a3, a61065; CHECK-NEXT: li a3, 631066; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma1067; CHECK-NEXT: vand.vx v24, v8, a3, v0.t1068; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t1069; CHECK-NEXT: addi a6, sp, 161070; CHECK-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill1071; CHECK-NEXT: add a5, a0, a51072; CHECK-NEXT: vnot.v v8, v8, v0.t1073; CHECK-NEXT: vl8re64.v v16, (a5)1074; CHECK-NEXT: vand.vx v8, v8, a3, v0.t1075; CHECK-NEXT: vl8re64.v v24, (a0)1076; CHECK-NEXT: csrr a0, vlenb1077; CHECK-NEXT: slli a0, a0, 31078; CHECK-NEXT: add a0, sp, a01079; CHECK-NEXT: addi a0, a0, 161080; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill1081; CHECK-NEXT: vl8re64.v v24, (a2)1082; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t1083; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t1084; CHECK-NEXT: addi a0, sp, 161085; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1086; CHECK-NEXT: vor.vv v8, v16, v8, v0.t1087; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1088; CHECK-NEXT: bltu a4, a1, .LBB47_21089; CHECK-NEXT: # %bb.1:1090; CHECK-NEXT: mv a4, a11091; CHECK-NEXT: .LBB47_2:1092; CHECK-NEXT: vmv1r.v v0, v71093; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma1094; CHECK-NEXT: vand.vx v8, v24, a3, v0.t1095; CHECK-NEXT: csrr a0, vlenb1096; CHECK-NEXT: slli a0, a0, 41097; CHECK-NEXT: add a0, sp, a01098; CHECK-NEXT: addi a0, a0, 161099; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1100; CHECK-NEXT: vsll.vv v16, v16, v8, v0.t1101; CHECK-NEXT: vnot.v v24, v24, v0.t1102; CHECK-NEXT: vand.vx v24, v24, a3, v0.t1103; CHECK-NEXT: csrr a0, vlenb1104; CHECK-NEXT: slli a0, a0, 31105; CHECK-NEXT: add a0, sp, a01106; CHECK-NEXT: addi a0, a0, 161107; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1108; CHECK-NEXT: vsrl.vi v8, v8, 1, v0.t1109; CHECK-NEXT: vsrl.vv v8, v8, v24, v0.t1110; CHECK-NEXT: vor.vv v8, v16, v8, v0.t1111; CHECK-NEXT: addi a0, sp, 161112; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1113; CHECK-NEXT: csrr a0, vlenb1114; CHECK-NEXT: li a1, 241115; CHECK-NEXT: mul a0, a0, a11116; CHECK-NEXT: add sp, sp, a01117; CHECK-NEXT: .cfi_def_cfa sp, 161118; CHECK-NEXT: addi sp, sp, 161119; CHECK-NEXT: .cfi_def_cfa_offset 01120; CHECK-NEXT: ret1121 %res = call <vscale x 16 x i64> @llvm.vp.fshl.nxv16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 %evl)1122 ret <vscale x 16 x i64> %res1123}1124 1125; Test promotion.1126define <vscale x 1 x i9> @fshr_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {1127; CHECK-LABEL: fshr_v1i9:1128; CHECK: # %bb.0:1129; CHECK-NEXT: li a1, 5111130; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1131; CHECK-NEXT: vand.vx v10, v10, a1, v0.t1132; CHECK-NEXT: li a0, 91133; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t1134; CHECK-NEXT: vadd.vi v10, v10, 7, v0.t1135; CHECK-NEXT: vand.vi v11, v10, 15, v0.t1136; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t1137; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t1138; CHECK-NEXT: vnot.v v10, v10, v0.t1139; CHECK-NEXT: vand.vi v10, v10, 15, v0.t1140; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t1141; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t1142; CHECK-NEXT: vor.vv v8, v8, v9, v0.t1143; CHECK-NEXT: ret1144 %res = call <vscale x 1 x i9> @llvm.vp.fshr.nxv1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 %evl)1145 ret <vscale x 1 x i9> %res1146}1147 1148define <vscale x 1 x i9> @fshl_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {1149; CHECK-LABEL: fshl_v1i9:1150; CHECK: # %bb.0:1151; CHECK-NEXT: li a1, 5111152; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1153; CHECK-NEXT: vand.vx v10, v10, a1, v0.t1154; CHECK-NEXT: li a0, 91155; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t1156; CHECK-NEXT: vand.vi v11, v10, 15, v0.t1157; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t1158; CHECK-NEXT: vnot.v v10, v10, v0.t1159; CHECK-NEXT: vand.vi v10, v10, 15, v0.t1160; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t1161; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t1162; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t1163; CHECK-NEXT: vor.vv v8, v8, v9, v0.t1164; CHECK-NEXT: ret1165 %res = call <vscale x 1 x i9> @llvm.vp.fshl.nxv1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 %evl)1166 ret <vscale x 1 x i9> %res1167}1168 1169define <vscale x 1 x i8> @fshr_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {1170; CHECK-LABEL: fshr_v1i4:1171; CHECK: # %bb.0:1172; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1173; CHECK-NEXT: vand.vi v10, v10, 15, v0.t1174; CHECK-NEXT: li a0, 41175; CHECK-NEXT: vand.vi v9, v9, 15, v0.t1176; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t1177; CHECK-NEXT: vor.vv v8, v8, v9, v0.t1178; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t1179; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t1180; CHECK-NEXT: vand.vi v8, v8, 15, v0.t1181; CHECK-NEXT: ret1182 %trunca = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i1> %m, i32 zeroext %evl)1183 %truncb = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl)1184 %truncc = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl)1185 %fshr = call <vscale x 1 x i4> @llvm.vp.fshr.nxv1i4(<vscale x 1 x i4> %trunca, <vscale x 1 x i4> %truncb, <vscale x 1 x i4> %truncc, <vscale x 1 x i1> %m, i32 %evl)1186 %res = call <vscale x 1 x i8> @llvm.vp.zext.nxv1i8.nxv1i4(<vscale x 1 x i4> %fshr, <vscale x 1 x i1> %m, i32 zeroext %evl)1187 ret <vscale x 1 x i8> %res1188}1189 1190define <vscale x 1 x i8> @fshl_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {1191; CHECK-LABEL: fshl_v1i4:1192; CHECK: # %bb.0:1193; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1194; CHECK-NEXT: vand.vi v10, v10, 15, v0.t1195; CHECK-NEXT: li a0, 41196; CHECK-NEXT: vand.vi v9, v9, 15, v0.t1197; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t1198; CHECK-NEXT: vor.vv v8, v8, v9, v0.t1199; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t1200; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t1201; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t1202; CHECK-NEXT: vand.vi v8, v8, 15, v0.t1203; CHECK-NEXT: ret1204 %trunca = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i1> %m, i32 zeroext %evl)1205 %truncb = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl)1206 %truncc = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl)1207 %fshl = call <vscale x 1 x i4> @llvm.vp.fshl.nxv1i4(<vscale x 1 x i4> %trunca, <vscale x 1 x i4> %truncb, <vscale x 1 x i4> %truncc, <vscale x 1 x i1> %m, i32 %evl)1208 %res = call <vscale x 1 x i8> @llvm.vp.zext.nxv1i8.nxv1i4(<vscale x 1 x i4> %fshl, <vscale x 1 x i1> %m, i32 zeroext %evl)1209 ret <vscale x 1 x i8> %res1210}1211