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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i32> @fshr(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c) {6; CHECK-LABEL: fshr:7; CHECK: # %bb.0:8; CHECK-NEXT: li a0, 319; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma10; CHECK-NEXT: vnot.v v11, v1011; CHECK-NEXT: vadd.vv v8, v8, v812; CHECK-NEXT: vand.vx v10, v10, a013; CHECK-NEXT: vand.vx v11, v11, a014; CHECK-NEXT: vsrl.vv v9, v9, v1015; CHECK-NEXT: vsll.vv v8, v8, v1116; CHECK-NEXT: vor.vv v8, v8, v917; CHECK-NEXT: ret18 %res = call <vscale x 1 x i32> @llvm.fshr.v4i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c)19 ret <vscale x 1 x i32> %res20}21 22define <vscale x 1 x i32> @fshl(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c) {23; CHECK-LABEL: fshl:24; CHECK: # %bb.0:25; CHECK-NEXT: li a0, 3126; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma27; CHECK-NEXT: vnot.v v11, v1028; CHECK-NEXT: vsrl.vi v9, v9, 129; CHECK-NEXT: vand.vx v10, v10, a030; CHECK-NEXT: vand.vx v11, v11, a031; CHECK-NEXT: vsll.vv v8, v8, v1032; CHECK-NEXT: vsrl.vv v9, v9, v1133; CHECK-NEXT: vor.vv v8, v8, v934; CHECK-NEXT: ret35 %res = call <vscale x 1 x i32> @llvm.fshl.v4i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c)36 ret <vscale x 1 x i32> %res37}38 39