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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV323; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV644 5define i32 @vector_length_i16(i16 zeroext %tc) {6; CHECK-LABEL: vector_length_i16:7; CHECK: # %bb.0:8; CHECK-NEXT: csrr a1, vlenb9; CHECK-NEXT: srli a1, a1, 210; CHECK-NEXT: bltu a0, a1, .LBB0_211; CHECK-NEXT: # %bb.1:12; CHECK-NEXT: mv a0, a113; CHECK-NEXT: .LBB0_2:14; CHECK-NEXT: ret15 %a = call i32 @llvm.experimental.get.vector.length.i16(i16 %tc, i32 2, i1 true)16 ret i32 %a17}18 19define i32 @vector_length_i32(i32 zeroext %tc) {20; CHECK-LABEL: vector_length_i32:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli a0, a0, e8, mf4, ta, ma23; CHECK-NEXT: ret24 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 true)25 ret i32 %a26}27 28define i32 @vector_length_XLen(iXLen zeroext %tc) {29; CHECK-LABEL: vector_length_XLen:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetvli a0, a0, e8, mf4, ta, ma32; CHECK-NEXT: ret33 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 true)34 ret i32 %a35}36 37define i32 @vector_length_i16_fixed(i16 zeroext %tc) {38; CHECK-LABEL: vector_length_i16_fixed:39; CHECK: # %bb.0:40; CHECK-NEXT: li a1, 241; CHECK-NEXT: bltu a0, a1, .LBB3_242; CHECK-NEXT: # %bb.1:43; CHECK-NEXT: li a0, 244; CHECK-NEXT: .LBB3_2:45; CHECK-NEXT: ret46 %a = call i32 @llvm.experimental.get.vector.length.i16(i16 %tc, i32 2, i1 false)47 ret i32 %a48}49 50define i32 @vector_length_i32_fixed(i32 zeroext %tc) {51; CHECK-LABEL: vector_length_i32_fixed:52; CHECK: # %bb.0:53; CHECK-NEXT: li a1, 254; CHECK-NEXT: bltu a0, a1, .LBB4_255; CHECK-NEXT: # %bb.1:56; CHECK-NEXT: li a0, 257; CHECK-NEXT: .LBB4_2:58; CHECK-NEXT: ret59 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 false)60 ret i32 %a61}62 63define i32 @vector_length_XLen_fixed(iXLen zeroext %tc) {64; CHECK-LABEL: vector_length_XLen_fixed:65; CHECK: # %bb.0:66; CHECK-NEXT: li a1, 267; CHECK-NEXT: bltu a0, a1, .LBB5_268; CHECK-NEXT: # %bb.1:69; CHECK-NEXT: li a0, 270; CHECK-NEXT: .LBB5_2:71; CHECK-NEXT: ret72 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 false)73 ret i32 %a74}75 76define i32 @vector_length_vf1_i32(i32 zeroext %tc) {77; CHECK-LABEL: vector_length_vf1_i32:78; CHECK: # %bb.0:79; CHECK-NEXT: vsetvli a0, a0, e8, mf8, ta, ma80; CHECK-NEXT: ret81 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 1, i1 true)82 ret i32 %a83}84 85define i32 @vector_length_vf1_XLen(iXLen zeroext %tc) {86; CHECK-LABEL: vector_length_vf1_XLen:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, a0, e8, mf8, ta, ma89; CHECK-NEXT: ret90 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 1, i1 true)91 ret i32 %a92}93 94define i32 @vector_length_vf2_i32(i32 zeroext %tc) {95; CHECK-LABEL: vector_length_vf2_i32:96; CHECK: # %bb.0:97; CHECK-NEXT: vsetvli a0, a0, e8, mf4, ta, ma98; CHECK-NEXT: ret99 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 true)100 ret i32 %a101}102 103define i32 @vector_length_vf2_XLen(iXLen zeroext %tc) {104; CHECK-LABEL: vector_length_vf2_XLen:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, a0, e8, mf4, ta, ma107; CHECK-NEXT: ret108 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 true)109 ret i32 %a110}111 112define i32 @vector_length_vf4_i32(i32 zeroext %tc) {113; CHECK-LABEL: vector_length_vf4_i32:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli a0, a0, e8, mf2, ta, ma116; CHECK-NEXT: ret117 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 4, i1 true)118 ret i32 %a119}120 121define i32 @vector_length_vf4_XLen(iXLen zeroext %tc) {122; CHECK-LABEL: vector_length_vf4_XLen:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli a0, a0, e8, mf2, ta, ma125; CHECK-NEXT: ret126 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 4, i1 true)127 ret i32 %a128}129 130define i32 @vector_length_vf8_i32(i32 zeroext %tc) {131; CHECK-LABEL: vector_length_vf8_i32:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetvli a0, a0, e8, m1, ta, ma134; CHECK-NEXT: ret135 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 8, i1 true)136 ret i32 %a137}138 139define i32 @vector_length_vf8_XLen(iXLen zeroext %tc) {140; CHECK-LABEL: vector_length_vf8_XLen:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli a0, a0, e8, m1, ta, ma143; CHECK-NEXT: ret144 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 8, i1 true)145 ret i32 %a146}147 148define i32 @vector_length_vf16_i32(i32 zeroext %tc) {149; CHECK-LABEL: vector_length_vf16_i32:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a0, a0, e8, m2, ta, ma152; CHECK-NEXT: ret153 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 16, i1 true)154 ret i32 %a155}156 157define i32 @vector_length_vf16_XLen(iXLen zeroext %tc) {158; CHECK-LABEL: vector_length_vf16_XLen:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a0, a0, e8, m2, ta, ma161; CHECK-NEXT: ret162 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 16, i1 true)163 ret i32 %a164}165 166define i32 @vector_length_vf32_i32(i32 zeroext %tc) {167; CHECK-LABEL: vector_length_vf32_i32:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli a0, a0, e8, m4, ta, ma170; CHECK-NEXT: ret171 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 32, i1 true)172 ret i32 %a173}174 175define i32 @vector_length_vf32_XLen(iXLen zeroext %tc) {176; CHECK-LABEL: vector_length_vf32_XLen:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli a0, a0, e8, m4, ta, ma179; CHECK-NEXT: ret180 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 32, i1 true)181 ret i32 %a182}183 184define i32 @vector_length_vf64_i32(i32 zeroext %tc) {185; CHECK-LABEL: vector_length_vf64_i32:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli a0, a0, e8, m8, ta, ma188; CHECK-NEXT: ret189 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 64, i1 true)190 ret i32 %a191}192 193define i32 @vector_length_vf64_XLen(iXLen zeroext %tc) {194; CHECK-LABEL: vector_length_vf64_XLen:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a0, a0, e8, m8, ta, ma197; CHECK-NEXT: ret198 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 64, i1 true)199 ret i32 %a200}201 202define i32 @vector_length_vf128_i32(i32 zeroext %tc) {203; RV32-LABEL: vector_length_vf128_i32:204; RV32: # %bb.0:205; RV32-NEXT: csrr a1, vlenb206; RV32-NEXT: slli a1, a1, 4207; RV32-NEXT: bltu a0, a1, .LBB20_2208; RV32-NEXT: # %bb.1:209; RV32-NEXT: mv a0, a1210; RV32-NEXT: .LBB20_2:211; RV32-NEXT: ret212;213; RV64-LABEL: vector_length_vf128_i32:214; RV64: # %bb.0:215; RV64-NEXT: sext.w a0, a0216; RV64-NEXT: csrr a1, vlenb217; RV64-NEXT: slli a1, a1, 4218; RV64-NEXT: bltu a0, a1, .LBB20_2219; RV64-NEXT: # %bb.1:220; RV64-NEXT: mv a0, a1221; RV64-NEXT: .LBB20_2:222; RV64-NEXT: ret223 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 128, i1 true)224 ret i32 %a225}226 227define i32 @vector_length_vf128_XLen(iXLen zeroext %tc) {228; RV32-LABEL: vector_length_vf128_XLen:229; RV32: # %bb.0:230; RV32-NEXT: csrr a1, vlenb231; RV32-NEXT: slli a1, a1, 4232; RV32-NEXT: bltu a0, a1, .LBB21_2233; RV32-NEXT: # %bb.1:234; RV32-NEXT: mv a0, a1235; RV32-NEXT: .LBB21_2:236; RV32-NEXT: ret237;238; RV64-LABEL: vector_length_vf128_XLen:239; RV64: # %bb.0:240; RV64-NEXT: sext.w a0, a0241; RV64-NEXT: csrr a1, vlenb242; RV64-NEXT: slli a1, a1, 4243; RV64-NEXT: bltu a0, a1, .LBB21_2244; RV64-NEXT: # %bb.1:245; RV64-NEXT: mv a0, a1246; RV64-NEXT: .LBB21_2:247; RV64-NEXT: ret248 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 128, i1 true)249 ret i32 %a250}251 252define i32 @vector_length_vf3_i32(i32 zeroext %tc) {253; RV32-LABEL: vector_length_vf3_i32:254; RV32: # %bb.0:255; RV32-NEXT: csrr a1, vlenb256; RV32-NEXT: srli a2, a1, 3257; RV32-NEXT: srli a1, a1, 2258; RV32-NEXT: add a1, a1, a2259; RV32-NEXT: bltu a0, a1, .LBB22_2260; RV32-NEXT: # %bb.1:261; RV32-NEXT: mv a0, a1262; RV32-NEXT: .LBB22_2:263; RV32-NEXT: ret264;265; RV64-LABEL: vector_length_vf3_i32:266; RV64: # %bb.0:267; RV64-NEXT: sext.w a0, a0268; RV64-NEXT: csrr a1, vlenb269; RV64-NEXT: srli a2, a1, 3270; RV64-NEXT: srli a1, a1, 2271; RV64-NEXT: add a1, a1, a2272; RV64-NEXT: bltu a0, a1, .LBB22_2273; RV64-NEXT: # %bb.1:274; RV64-NEXT: mv a0, a1275; RV64-NEXT: .LBB22_2:276; RV64-NEXT: ret277 %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 3, i1 true)278 ret i32 %a279}280 281define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {282; RV32-LABEL: vector_length_vf3_XLen:283; RV32: # %bb.0:284; RV32-NEXT: csrr a1, vlenb285; RV32-NEXT: srli a2, a1, 3286; RV32-NEXT: srli a1, a1, 2287; RV32-NEXT: add a1, a1, a2288; RV32-NEXT: bltu a0, a1, .LBB23_2289; RV32-NEXT: # %bb.1:290; RV32-NEXT: mv a0, a1291; RV32-NEXT: .LBB23_2:292; RV32-NEXT: ret293;294; RV64-LABEL: vector_length_vf3_XLen:295; RV64: # %bb.0:296; RV64-NEXT: sext.w a0, a0297; RV64-NEXT: csrr a1, vlenb298; RV64-NEXT: srli a2, a1, 3299; RV64-NEXT: srli a1, a1, 2300; RV64-NEXT: add a1, a1, a2301; RV64-NEXT: bltu a0, a1, .LBB23_2302; RV64-NEXT: # %bb.1:303; RV64-NEXT: mv a0, a1304; RV64-NEXT: .LBB23_2:305; RV64-NEXT: ret306 %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 3, i1 true)307 ret i32 %a308}309