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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+zvfh,+v -verify-machineinstrs < %s | \3; RUN: FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+zvfh,+v -verify-machineinstrs < %s | \5; RUN: FileCheck %s6 7; ================================================================================8; trunc <vscale x 1 x half>9; ================================================================================10 11define <vscale x 1 x i8> @trunc_nxv1f16_to_si8(<vscale x 1 x half> %x) {12; CHECK-LABEL: trunc_nxv1f16_to_si8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma15; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v816; CHECK-NEXT: vmv1r.v v8, v917; CHECK-NEXT: ret18 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)19 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>20 ret <vscale x 1 x i8> %b21}22 23define <vscale x 1 x i8> @trunc_nxv1f16_to_ui8(<vscale x 1 x half> %x) {24; CHECK-LABEL: trunc_nxv1f16_to_ui8:25; CHECK: # %bb.0:26; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma27; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v828; CHECK-NEXT: vmv1r.v v8, v929; CHECK-NEXT: ret30 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)31 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>32 ret <vscale x 1 x i8> %b33}34 35define <vscale x 1 x i16> @trunc_nxv1f16_to_si16(<vscale x 1 x half> %x) {36; CHECK-LABEL: trunc_nxv1f16_to_si16:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma39; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v840; CHECK-NEXT: ret41 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)42 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>43 ret <vscale x 1 x i16> %b44}45 46define <vscale x 1 x i16> @trunc_nxv1f16_to_ui16(<vscale x 1 x half> %x) {47; CHECK-LABEL: trunc_nxv1f16_to_ui16:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma50; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v851; CHECK-NEXT: ret52 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)53 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>54 ret <vscale x 1 x i16> %b55}56 57define <vscale x 1 x i32> @trunc_nxv1f16_to_si32(<vscale x 1 x half> %x) {58; CHECK-LABEL: trunc_nxv1f16_to_si32:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma61; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v862; CHECK-NEXT: vmv1r.v v8, v963; CHECK-NEXT: ret64 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)65 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>66 ret <vscale x 1 x i32> %b67}68 69define <vscale x 1 x i32> @trunc_nxv1f16_to_ui32(<vscale x 1 x half> %x) {70; CHECK-LABEL: trunc_nxv1f16_to_ui32:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma73; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v874; CHECK-NEXT: vmv1r.v v8, v975; CHECK-NEXT: ret76 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)77 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>78 ret <vscale x 1 x i32> %b79}80 81define <vscale x 1 x i64> @trunc_nxv1f16_to_si64(<vscale x 1 x half> %x) {82; CHECK-LABEL: trunc_nxv1f16_to_si64:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma85; CHECK-NEXT: vfabs.v v9, v886; CHECK-NEXT: li a0, 2587; CHECK-NEXT: slli a0, a0, 1088; CHECK-NEXT: fmv.h.x fa5, a089; CHECK-NEXT: vmflt.vf v0, v9, fa590; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t91; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t92; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu93; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t94; CHECK-NEXT: vfwcvt.f.f.v v9, v895; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma96; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v997; CHECK-NEXT: ret98 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)99 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>100 ret <vscale x 1 x i64> %b101}102 103define <vscale x 1 x i64> @trunc_nxv1f16_to_ui64(<vscale x 1 x half> %x) {104; CHECK-LABEL: trunc_nxv1f16_to_ui64:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma107; CHECK-NEXT: vfabs.v v9, v8108; CHECK-NEXT: li a0, 25109; CHECK-NEXT: slli a0, a0, 10110; CHECK-NEXT: fmv.h.x fa5, a0111; CHECK-NEXT: vmflt.vf v0, v9, fa5112; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t113; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t114; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu115; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t116; CHECK-NEXT: vfwcvt.f.f.v v9, v8117; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma118; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9119; CHECK-NEXT: ret120 %a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)121 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>122 ret <vscale x 1 x i64> %b123}124 125; ================================================================================126; trunc <vscale x 4 x half>127; ================================================================================128 129define <vscale x 4 x i8> @trunc_nxv4f16_to_si8(<vscale x 4 x half> %x) {130; CHECK-LABEL: trunc_nxv4f16_to_si8:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma133; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8134; CHECK-NEXT: vmv1r.v v8, v9135; CHECK-NEXT: ret136 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)137 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>138 ret <vscale x 4 x i8> %b139}140 141define <vscale x 4 x i8> @trunc_nxv4f16_to_ui8(<vscale x 4 x half> %x) {142; CHECK-LABEL: trunc_nxv4f16_to_ui8:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma145; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8146; CHECK-NEXT: vmv1r.v v8, v9147; CHECK-NEXT: ret148 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)149 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>150 ret <vscale x 4 x i8> %b151}152 153define <vscale x 4 x i16> @trunc_nxv4f16_to_si16(<vscale x 4 x half> %x) {154; CHECK-LABEL: trunc_nxv4f16_to_si16:155; CHECK: # %bb.0:156; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma157; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8158; CHECK-NEXT: ret159 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)160 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>161 ret <vscale x 4 x i16> %b162}163 164define <vscale x 4 x i16> @trunc_nxv4f16_to_ui16(<vscale x 4 x half> %x) {165; CHECK-LABEL: trunc_nxv4f16_to_ui16:166; CHECK: # %bb.0:167; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma168; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8169; CHECK-NEXT: ret170 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)171 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>172 ret <vscale x 4 x i16> %b173}174 175define <vscale x 4 x i32> @trunc_nxv4f16_to_si32(<vscale x 4 x half> %x) {176; CHECK-LABEL: trunc_nxv4f16_to_si32:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma179; CHECK-NEXT: vmv1r.v v10, v8180; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10181; CHECK-NEXT: ret182 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)183 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>184 ret <vscale x 4 x i32> %b185}186 187define <vscale x 4 x i32> @trunc_nxv4f16_to_ui32(<vscale x 4 x half> %x) {188; CHECK-LABEL: trunc_nxv4f16_to_ui32:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma191; CHECK-NEXT: vmv1r.v v10, v8192; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10193; CHECK-NEXT: ret194 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)195 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>196 ret <vscale x 4 x i32> %b197}198 199define <vscale x 4 x i64> @trunc_nxv4f16_to_si64(<vscale x 4 x half> %x) {200; CHECK-LABEL: trunc_nxv4f16_to_si64:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma203; CHECK-NEXT: vfabs.v v9, v8204; CHECK-NEXT: li a0, 25205; CHECK-NEXT: slli a0, a0, 10206; CHECK-NEXT: fmv.h.x fa5, a0207; CHECK-NEXT: vmflt.vf v0, v9, fa5208; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t209; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t210; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu211; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t212; CHECK-NEXT: vfwcvt.f.f.v v12, v8213; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma214; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12215; CHECK-NEXT: ret216 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)217 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>218 ret <vscale x 4 x i64> %b219}220 221define <vscale x 4 x i64> @trunc_nxv4f16_to_ui64(<vscale x 4 x half> %x) {222; CHECK-LABEL: trunc_nxv4f16_to_ui64:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma225; CHECK-NEXT: vfabs.v v9, v8226; CHECK-NEXT: li a0, 25227; CHECK-NEXT: slli a0, a0, 10228; CHECK-NEXT: fmv.h.x fa5, a0229; CHECK-NEXT: vmflt.vf v0, v9, fa5230; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t231; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t232; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu233; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t234; CHECK-NEXT: vfwcvt.f.f.v v12, v8235; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma236; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12237; CHECK-NEXT: ret238 %a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)239 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>240 ret <vscale x 4 x i64> %b241}242 243; ================================================================================244; ceil <vscale x 1 x half>245; ================================================================================246 247define <vscale x 1 x i8> @ceil_nxv1f16_to_si8(<vscale x 1 x half> %x) {248; CHECK-LABEL: ceil_nxv1f16_to_si8:249; CHECK: # %bb.0:250; CHECK-NEXT: fsrmi a0, 3251; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma252; CHECK-NEXT: vfncvt.x.f.w v9, v8253; CHECK-NEXT: fsrm a0254; CHECK-NEXT: vmv1r.v v8, v9255; CHECK-NEXT: ret256 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)257 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>258 ret <vscale x 1 x i8> %b259}260 261define <vscale x 1 x i8> @ceil_nxv1f16_to_ui8(<vscale x 1 x half> %x) {262; CHECK-LABEL: ceil_nxv1f16_to_ui8:263; CHECK: # %bb.0:264; CHECK-NEXT: fsrmi a0, 3265; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma266; CHECK-NEXT: vfncvt.xu.f.w v9, v8267; CHECK-NEXT: fsrm a0268; CHECK-NEXT: vmv1r.v v8, v9269; CHECK-NEXT: ret270 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)271 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>272 ret <vscale x 1 x i8> %b273}274 275define <vscale x 1 x i16> @ceil_nxv1f16_to_si16(<vscale x 1 x half> %x) {276; CHECK-LABEL: ceil_nxv1f16_to_si16:277; CHECK: # %bb.0:278; CHECK-NEXT: fsrmi a0, 3279; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma280; CHECK-NEXT: vfcvt.x.f.v v8, v8281; CHECK-NEXT: fsrm a0282; CHECK-NEXT: ret283 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)284 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>285 ret <vscale x 1 x i16> %b286}287 288define <vscale x 1 x i16> @ceil_nxv1f16_to_ui16(<vscale x 1 x half> %x) {289; CHECK-LABEL: ceil_nxv1f16_to_ui16:290; CHECK: # %bb.0:291; CHECK-NEXT: fsrmi a0, 3292; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma293; CHECK-NEXT: vfcvt.xu.f.v v8, v8294; CHECK-NEXT: fsrm a0295; CHECK-NEXT: ret296 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)297 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>298 ret <vscale x 1 x i16> %b299}300 301define <vscale x 1 x i32> @ceil_nxv1f16_to_si32(<vscale x 1 x half> %x) {302; CHECK-LABEL: ceil_nxv1f16_to_si32:303; CHECK: # %bb.0:304; CHECK-NEXT: fsrmi a0, 3305; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma306; CHECK-NEXT: vfwcvt.x.f.v v9, v8307; CHECK-NEXT: fsrm a0308; CHECK-NEXT: vmv1r.v v8, v9309; CHECK-NEXT: ret310 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)311 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>312 ret <vscale x 1 x i32> %b313}314 315define <vscale x 1 x i32> @ceil_nxv1f16_to_ui32(<vscale x 1 x half> %x) {316; CHECK-LABEL: ceil_nxv1f16_to_ui32:317; CHECK: # %bb.0:318; CHECK-NEXT: fsrmi a0, 3319; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma320; CHECK-NEXT: vfwcvt.xu.f.v v9, v8321; CHECK-NEXT: fsrm a0322; CHECK-NEXT: vmv1r.v v8, v9323; CHECK-NEXT: ret324 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)325 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>326 ret <vscale x 1 x i32> %b327}328 329define <vscale x 1 x i64> @ceil_nxv1f16_to_si64(<vscale x 1 x half> %x) {330; CHECK-LABEL: ceil_nxv1f16_to_si64:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma333; CHECK-NEXT: vfabs.v v9, v8334; CHECK-NEXT: li a0, 25335; CHECK-NEXT: slli a0, a0, 10336; CHECK-NEXT: fmv.h.x fa5, a0337; CHECK-NEXT: vmflt.vf v0, v9, fa5338; CHECK-NEXT: fsrmi a0, 3339; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t340; CHECK-NEXT: fsrm a0341; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t342; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu343; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t344; CHECK-NEXT: vfwcvt.f.f.v v9, v8345; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma346; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9347; CHECK-NEXT: ret348; RV32-LABEL: ceil_nxv1f16_to_si64:349; RV32: # %bb.0:350; RV32-NEXT: lui a0, %hi(.LCPI22_0)351; RV32-NEXT: flh fa5, %lo(.LCPI22_0)(a0)352; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma353; RV32-NEXT: vfabs.v v9, v8354; RV32-NEXT: vmflt.vf v0, v9, fa5355; RV32-NEXT: fsrmi a0, 3356; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t357; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t358; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu359; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t360; RV32-NEXT: vfwcvt.f.f.v v9, v8361; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma362; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v9363; RV32-NEXT: fsrm a0364; RV32-NEXT: ret365; RV64-LABEL: ceil_nxv1f16_to_si64:366; RV64: # %bb.0:367; RV64-NEXT: lui a0, %hi(.LCPI22_0)368; RV64-NEXT: flh fa5, %lo(.LCPI22_0)(a0)369; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma370; RV64-NEXT: vfabs.v v9, v8371; RV64-NEXT: vmflt.vf v0, v9, fa5372; RV64-NEXT: fsrmi a0, 3373; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t374; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t375; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu376; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t377; RV64-NEXT: vfwcvt.f.f.v v9, v8378; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma379; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v9380; RV64-NEXT: fsrm a0381; RV64-NEXT: ret382 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)383 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>384 ret <vscale x 1 x i64> %b385}386 387define <vscale x 1 x i64> @ceil_nxv1f16_to_ui64(<vscale x 1 x half> %x) {388; CHECK-LABEL: ceil_nxv1f16_to_ui64:389; CHECK: # %bb.0:390; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma391; CHECK-NEXT: vfabs.v v9, v8392; CHECK-NEXT: li a0, 25393; CHECK-NEXT: slli a0, a0, 10394; CHECK-NEXT: fmv.h.x fa5, a0395; CHECK-NEXT: vmflt.vf v0, v9, fa5396; CHECK-NEXT: fsrmi a0, 3397; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t398; CHECK-NEXT: fsrm a0399; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t400; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu401; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t402; CHECK-NEXT: vfwcvt.f.f.v v9, v8403; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma404; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9405; CHECK-NEXT: ret406; RV32-LABEL: ceil_nxv1f16_to_ui64:407; RV32: # %bb.0:408; RV32-NEXT: lui a0, %hi(.LCPI23_0)409; RV32-NEXT: flh fa5, %lo(.LCPI23_0)(a0)410; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma411; RV32-NEXT: vfabs.v v9, v8412; RV32-NEXT: vmflt.vf v0, v9, fa5413; RV32-NEXT: fsrmi a0, 3414; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t415; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t416; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu417; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t418; RV32-NEXT: vfwcvt.f.f.v v9, v8419; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma420; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v9421; RV32-NEXT: fsrm a0422; RV32-NEXT: ret423; RV64-LABEL: ceil_nxv1f16_to_ui64:424; RV64: # %bb.0:425; RV64-NEXT: lui a0, %hi(.LCPI23_0)426; RV64-NEXT: flh fa5, %lo(.LCPI23_0)(a0)427; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma428; RV64-NEXT: vfabs.v v9, v8429; RV64-NEXT: vmflt.vf v0, v9, fa5430; RV64-NEXT: fsrmi a0, 3431; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t432; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t433; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu434; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t435; RV64-NEXT: vfwcvt.f.f.v v9, v8436; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma437; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v9438; RV64-NEXT: fsrm a0439; RV64-NEXT: ret440 %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)441 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>442 ret <vscale x 1 x i64> %b443}444 445; ================================================================================446; ceil <vscale x 4 x half>447; ================================================================================448 449define <vscale x 4 x i8> @ceil_nxv4f16_to_si8(<vscale x 4 x half> %x) {450; CHECK-LABEL: ceil_nxv4f16_to_si8:451; CHECK: # %bb.0:452; CHECK-NEXT: fsrmi a0, 3453; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma454; CHECK-NEXT: vfncvt.x.f.w v9, v8455; CHECK-NEXT: fsrm a0456; CHECK-NEXT: vmv1r.v v8, v9457; CHECK-NEXT: ret458 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)459 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>460 ret <vscale x 4 x i8> %b461}462 463define <vscale x 4 x i8> @ceil_nxv4f16_to_ui8(<vscale x 4 x half> %x) {464; CHECK-LABEL: ceil_nxv4f16_to_ui8:465; CHECK: # %bb.0:466; CHECK-NEXT: fsrmi a0, 3467; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma468; CHECK-NEXT: vfncvt.xu.f.w v9, v8469; CHECK-NEXT: fsrm a0470; CHECK-NEXT: vmv1r.v v8, v9471; CHECK-NEXT: ret472 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)473 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>474 ret <vscale x 4 x i8> %b475}476 477define <vscale x 4 x i16> @ceil_nxv4f16_to_si16(<vscale x 4 x half> %x) {478; CHECK-LABEL: ceil_nxv4f16_to_si16:479; CHECK: # %bb.0:480; CHECK-NEXT: fsrmi a0, 3481; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma482; CHECK-NEXT: vfcvt.x.f.v v8, v8483; CHECK-NEXT: fsrm a0484; CHECK-NEXT: ret485 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)486 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>487 ret <vscale x 4 x i16> %b488}489 490define <vscale x 4 x i16> @ceil_nxv4f16_to_ui16(<vscale x 4 x half> %x) {491; CHECK-LABEL: ceil_nxv4f16_to_ui16:492; CHECK: # %bb.0:493; CHECK-NEXT: fsrmi a0, 3494; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma495; CHECK-NEXT: vfcvt.xu.f.v v8, v8496; CHECK-NEXT: fsrm a0497; CHECK-NEXT: ret498 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)499 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>500 ret <vscale x 4 x i16> %b501}502 503define <vscale x 4 x i32> @ceil_nxv4f16_to_si32(<vscale x 4 x half> %x) {504; CHECK-LABEL: ceil_nxv4f16_to_si32:505; CHECK: # %bb.0:506; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma507; CHECK-NEXT: vmv1r.v v10, v8508; CHECK-NEXT: fsrmi a0, 3509; CHECK-NEXT: vfwcvt.x.f.v v8, v10510; CHECK-NEXT: fsrm a0511; CHECK-NEXT: ret512 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)513 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>514 ret <vscale x 4 x i32> %b515}516 517define <vscale x 4 x i32> @ceil_nxv4f16_to_ui32(<vscale x 4 x half> %x) {518; CHECK-LABEL: ceil_nxv4f16_to_ui32:519; CHECK: # %bb.0:520; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma521; CHECK-NEXT: vmv1r.v v10, v8522; CHECK-NEXT: fsrmi a0, 3523; CHECK-NEXT: vfwcvt.xu.f.v v8, v10524; CHECK-NEXT: fsrm a0525; CHECK-NEXT: ret526 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)527 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>528 ret <vscale x 4 x i32> %b529}530 531define <vscale x 4 x i64> @ceil_nxv4f16_to_si64(<vscale x 4 x half> %x) {532; CHECK-LABEL: ceil_nxv4f16_to_si64:533; CHECK: # %bb.0:534; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma535; CHECK-NEXT: vfabs.v v9, v8536; CHECK-NEXT: li a0, 25537; CHECK-NEXT: slli a0, a0, 10538; CHECK-NEXT: fmv.h.x fa5, a0539; CHECK-NEXT: vmflt.vf v0, v9, fa5540; CHECK-NEXT: fsrmi a0, 3541; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t542; CHECK-NEXT: fsrm a0543; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t544; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu545; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t546; CHECK-NEXT: vfwcvt.f.f.v v12, v8547; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma548; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12549; CHECK-NEXT: ret550; RV32-LABEL: ceil_nxv4f16_to_si64:551; RV32: # %bb.0:552; RV32-NEXT: lui a0, %hi(.LCPI30_0)553; RV32-NEXT: flh fa5, %lo(.LCPI30_0)(a0)554; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma555; RV32-NEXT: vfabs.v v9, v8556; RV32-NEXT: vmflt.vf v0, v9, fa5557; RV32-NEXT: fsrmi a0, 3558; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t559; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t560; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu561; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t562; RV32-NEXT: vfwcvt.f.f.v v12, v8563; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma564; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v12565; RV32-NEXT: fsrm a0566; RV32-NEXT: ret567; RV64-LABEL: ceil_nxv4f16_to_si64:568; RV64: # %bb.0:569; RV64-NEXT: lui a0, %hi(.LCPI30_0)570; RV64-NEXT: flh fa5, %lo(.LCPI30_0)(a0)571; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma572; RV64-NEXT: vfabs.v v9, v8573; RV64-NEXT: vmflt.vf v0, v9, fa5574; RV64-NEXT: fsrmi a0, 3575; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t576; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t577; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu578; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t579; RV64-NEXT: vfwcvt.f.f.v v12, v8580; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma581; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v12582; RV64-NEXT: fsrm a0583; RV64-NEXT: ret584 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)585 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>586 ret <vscale x 4 x i64> %b587}588 589define <vscale x 4 x i64> @ceil_nxv4f16_to_ui64(<vscale x 4 x half> %x) {590; CHECK-LABEL: ceil_nxv4f16_to_ui64:591; CHECK: # %bb.0:592; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma593; CHECK-NEXT: vfabs.v v9, v8594; CHECK-NEXT: li a0, 25595; CHECK-NEXT: slli a0, a0, 10596; CHECK-NEXT: fmv.h.x fa5, a0597; CHECK-NEXT: vmflt.vf v0, v9, fa5598; CHECK-NEXT: fsrmi a0, 3599; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t600; CHECK-NEXT: fsrm a0601; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t602; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu603; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t604; CHECK-NEXT: vfwcvt.f.f.v v12, v8605; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma606; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12607; CHECK-NEXT: ret608; RV32-LABEL: ceil_nxv4f16_to_ui64:609; RV32: # %bb.0:610; RV32-NEXT: lui a0, %hi(.LCPI31_0)611; RV32-NEXT: flh fa5, %lo(.LCPI31_0)(a0)612; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma613; RV32-NEXT: vfabs.v v9, v8614; RV32-NEXT: vmflt.vf v0, v9, fa5615; RV32-NEXT: fsrmi a0, 3616; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t617; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t618; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu619; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t620; RV32-NEXT: vfwcvt.f.f.v v12, v8621; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma622; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v12623; RV32-NEXT: fsrm a0624; RV32-NEXT: ret625; RV64-LABEL: ceil_nxv4f16_to_ui64:626; RV64: # %bb.0:627; RV64-NEXT: lui a0, %hi(.LCPI31_0)628; RV64-NEXT: flh fa5, %lo(.LCPI31_0)(a0)629; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma630; RV64-NEXT: vfabs.v v9, v8631; RV64-NEXT: vmflt.vf v0, v9, fa5632; RV64-NEXT: fsrmi a0, 3633; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t634; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t635; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu636; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t637; RV64-NEXT: vfwcvt.f.f.v v12, v8638; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma639; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v12640; RV64-NEXT: fsrm a0641; RV64-NEXT: ret642 %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)643 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>644 ret <vscale x 4 x i64> %b645}646 647; ================================================================================648; rint <vscale x 1 x half>649; ================================================================================650 651define <vscale x 1 x i8> @rint_nxv1f16_to_si8(<vscale x 1 x half> %x) {652; CHECK-LABEL: rint_nxv1f16_to_si8:653; CHECK: # %bb.0:654; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma655; CHECK-NEXT: vfncvt.x.f.w v9, v8656; CHECK-NEXT: vmv1r.v v8, v9657; CHECK-NEXT: ret658 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)659 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>660 ret <vscale x 1 x i8> %b661}662 663define <vscale x 1 x i8> @rint_nxv1f16_to_ui8(<vscale x 1 x half> %x) {664; CHECK-LABEL: rint_nxv1f16_to_ui8:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma667; CHECK-NEXT: vfncvt.xu.f.w v9, v8668; CHECK-NEXT: vmv1r.v v8, v9669; CHECK-NEXT: ret670 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)671 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>672 ret <vscale x 1 x i8> %b673}674 675define <vscale x 1 x i16> @rint_nxv1f16_to_si16(<vscale x 1 x half> %x) {676; CHECK-LABEL: rint_nxv1f16_to_si16:677; CHECK: # %bb.0:678; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma679; CHECK-NEXT: vfcvt.x.f.v v8, v8680; CHECK-NEXT: ret681 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)682 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>683 ret <vscale x 1 x i16> %b684}685 686define <vscale x 1 x i16> @rint_nxv1f16_to_ui16(<vscale x 1 x half> %x) {687; CHECK-LABEL: rint_nxv1f16_to_ui16:688; CHECK: # %bb.0:689; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma690; CHECK-NEXT: vfcvt.xu.f.v v8, v8691; CHECK-NEXT: ret692 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)693 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>694 ret <vscale x 1 x i16> %b695}696 697define <vscale x 1 x i32> @rint_nxv1f16_to_si32(<vscale x 1 x half> %x) {698; CHECK-LABEL: rint_nxv1f16_to_si32:699; CHECK: # %bb.0:700; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma701; CHECK-NEXT: vfwcvt.x.f.v v9, v8702; CHECK-NEXT: vmv1r.v v8, v9703; CHECK-NEXT: ret704 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)705 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>706 ret <vscale x 1 x i32> %b707}708 709define <vscale x 1 x i32> @rint_nxv1f16_to_ui32(<vscale x 1 x half> %x) {710; CHECK-LABEL: rint_nxv1f16_to_ui32:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma713; CHECK-NEXT: vfwcvt.xu.f.v v9, v8714; CHECK-NEXT: vmv1r.v v8, v9715; CHECK-NEXT: ret716 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)717 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>718 ret <vscale x 1 x i32> %b719}720 721define <vscale x 1 x i64> @rint_nxv1f16_to_si64(<vscale x 1 x half> %x) {722; CHECK-LABEL: rint_nxv1f16_to_si64:723; CHECK: # %bb.0:724; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma725; CHECK-NEXT: vfabs.v v9, v8726; CHECK-NEXT: li a0, 25727; CHECK-NEXT: slli a0, a0, 10728; CHECK-NEXT: fmv.h.x fa5, a0729; CHECK-NEXT: vmflt.vf v0, v9, fa5730; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t731; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t732; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu733; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t734; CHECK-NEXT: vfwcvt.f.f.v v9, v8735; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma736; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9737; CHECK-NEXT: ret738; RV32-LABEL: rint_nxv1f16_to_si64:739; RV32: # %bb.0:740; RV32-NEXT: lui a0, %hi(.LCPI22_0)741; RV32-NEXT: flh fa5, %lo(.LCPI22_0)(a0)742; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma743; RV32-NEXT: vfabs.v v9, v8744; RV32-NEXT: vmflt.vf v0, v9, fa5745; RV32-NEXT: fsrmi a0, 3746; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t747; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t748; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu749; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t750; RV32-NEXT: vfwcvt.f.f.v v9, v8751; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma752; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v9753; RV32-NEXT: fsrm a0754; RV32-NEXT: ret755; RV64-LABEL: rint_nxv1f16_to_si64:756; RV64: # %bb.0:757; RV64-NEXT: lui a0, %hi(.LCPI22_0)758; RV64-NEXT: flh fa5, %lo(.LCPI22_0)(a0)759; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma760; RV64-NEXT: vfabs.v v9, v8761; RV64-NEXT: vmflt.vf v0, v9, fa5762; RV64-NEXT: fsrmi a0, 3763; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t764; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t765; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu766; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t767; RV64-NEXT: vfwcvt.f.f.v v9, v8768; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma769; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v9770; RV64-NEXT: fsrm a0771; RV64-NEXT: ret772 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)773 %b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>774 ret <vscale x 1 x i64> %b775}776 777define <vscale x 1 x i64> @rint_nxv1f16_to_ui64(<vscale x 1 x half> %x) {778; CHECK-LABEL: rint_nxv1f16_to_ui64:779; CHECK: # %bb.0:780; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma781; CHECK-NEXT: vfabs.v v9, v8782; CHECK-NEXT: li a0, 25783; CHECK-NEXT: slli a0, a0, 10784; CHECK-NEXT: fmv.h.x fa5, a0785; CHECK-NEXT: vmflt.vf v0, v9, fa5786; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t787; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t788; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu789; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t790; CHECK-NEXT: vfwcvt.f.f.v v9, v8791; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma792; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9793; CHECK-NEXT: ret794; RV32-LABEL: rint_nxv1f16_to_ui64:795; RV32: # %bb.0:796; RV32-NEXT: lui a0, %hi(.LCPI23_0)797; RV32-NEXT: flh fa5, %lo(.LCPI23_0)(a0)798; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma799; RV32-NEXT: vfabs.v v9, v8800; RV32-NEXT: vmflt.vf v0, v9, fa5801; RV32-NEXT: fsrmi a0, 3802; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t803; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t804; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu805; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t806; RV32-NEXT: vfwcvt.f.f.v v9, v8807; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma808; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v9809; RV32-NEXT: fsrm a0810; RV32-NEXT: ret811; RV64-LABEL: rint_nxv1f16_to_ui64:812; RV64: # %bb.0:813; RV64-NEXT: lui a0, %hi(.LCPI23_0)814; RV64-NEXT: flh fa5, %lo(.LCPI23_0)(a0)815; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma816; RV64-NEXT: vfabs.v v9, v8817; RV64-NEXT: vmflt.vf v0, v9, fa5818; RV64-NEXT: fsrmi a0, 3819; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t820; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t821; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu822; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t823; RV64-NEXT: vfwcvt.f.f.v v9, v8824; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma825; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v9826; RV64-NEXT: fsrm a0827; RV64-NEXT: ret828 %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)829 %b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>830 ret <vscale x 1 x i64> %b831}832 833; ================================================================================834; rint <vscale x 4 x half>835; ================================================================================836 837define <vscale x 4 x i8> @rint_nxv4f16_to_si8(<vscale x 4 x half> %x) {838; CHECK-LABEL: rint_nxv4f16_to_si8:839; CHECK: # %bb.0:840; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma841; CHECK-NEXT: vfncvt.x.f.w v9, v8842; CHECK-NEXT: vmv1r.v v8, v9843; CHECK-NEXT: ret844 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)845 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>846 ret <vscale x 4 x i8> %b847}848 849define <vscale x 4 x i8> @rint_nxv4f16_to_ui8(<vscale x 4 x half> %x) {850; CHECK-LABEL: rint_nxv4f16_to_ui8:851; CHECK: # %bb.0:852; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma853; CHECK-NEXT: vfncvt.xu.f.w v9, v8854; CHECK-NEXT: vmv1r.v v8, v9855; CHECK-NEXT: ret856 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)857 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>858 ret <vscale x 4 x i8> %b859}860 861define <vscale x 4 x i16> @rint_nxv4f16_to_si16(<vscale x 4 x half> %x) {862; CHECK-LABEL: rint_nxv4f16_to_si16:863; CHECK: # %bb.0:864; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma865; CHECK-NEXT: vfcvt.x.f.v v8, v8866; CHECK-NEXT: ret867 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)868 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>869 ret <vscale x 4 x i16> %b870}871 872define <vscale x 4 x i16> @rint_nxv4f16_to_ui16(<vscale x 4 x half> %x) {873; CHECK-LABEL: rint_nxv4f16_to_ui16:874; CHECK: # %bb.0:875; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma876; CHECK-NEXT: vfcvt.xu.f.v v8, v8877; CHECK-NEXT: ret878 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)879 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>880 ret <vscale x 4 x i16> %b881}882 883define <vscale x 4 x i32> @rint_nxv4f16_to_si32(<vscale x 4 x half> %x) {884; CHECK-LABEL: rint_nxv4f16_to_si32:885; CHECK: # %bb.0:886; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma887; CHECK-NEXT: vmv1r.v v10, v8888; CHECK-NEXT: vfwcvt.x.f.v v8, v10889; CHECK-NEXT: ret890 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)891 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>892 ret <vscale x 4 x i32> %b893}894 895define <vscale x 4 x i32> @rint_nxv4f16_to_ui32(<vscale x 4 x half> %x) {896; CHECK-LABEL: rint_nxv4f16_to_ui32:897; CHECK: # %bb.0:898; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma899; CHECK-NEXT: vmv1r.v v10, v8900; CHECK-NEXT: vfwcvt.xu.f.v v8, v10901; CHECK-NEXT: ret902 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)903 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>904 ret <vscale x 4 x i32> %b905}906 907define <vscale x 4 x i64> @rint_nxv4f16_to_si64(<vscale x 4 x half> %x) {908; CHECK-LABEL: rint_nxv4f16_to_si64:909; CHECK: # %bb.0:910; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma911; CHECK-NEXT: vfabs.v v9, v8912; CHECK-NEXT: li a0, 25913; CHECK-NEXT: slli a0, a0, 10914; CHECK-NEXT: fmv.h.x fa5, a0915; CHECK-NEXT: vmflt.vf v0, v9, fa5916; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t917; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t918; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu919; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t920; CHECK-NEXT: vfwcvt.f.f.v v12, v8921; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma922; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12923; CHECK-NEXT: ret924; RV32-LABEL: rint_nxv4f16_to_si64:925; RV32: # %bb.0:926; RV32-NEXT: lui a0, %hi(.LCPI30_0)927; RV32-NEXT: flh fa5, %lo(.LCPI30_0)(a0)928; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma929; RV32-NEXT: vfabs.v v9, v8930; RV32-NEXT: vmflt.vf v0, v9, fa5931; RV32-NEXT: fsrmi a0, 3932; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t933; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t934; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu935; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t936; RV32-NEXT: vfwcvt.f.f.v v12, v8937; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma938; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v12939; RV32-NEXT: fsrm a0940; RV32-NEXT: ret941; RV64-LABEL: rint_nxv4f16_to_si64:942; RV64: # %bb.0:943; RV64-NEXT: lui a0, %hi(.LCPI30_0)944; RV64-NEXT: flh fa5, %lo(.LCPI30_0)(a0)945; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma946; RV64-NEXT: vfabs.v v9, v8947; RV64-NEXT: vmflt.vf v0, v9, fa5948; RV64-NEXT: fsrmi a0, 3949; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t950; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t951; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu952; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t953; RV64-NEXT: vfwcvt.f.f.v v12, v8954; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma955; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v12956; RV64-NEXT: fsrm a0957; RV64-NEXT: ret958 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)959 %b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>960 ret <vscale x 4 x i64> %b961}962 963define <vscale x 4 x i64> @rint_nxv4f16_to_ui64(<vscale x 4 x half> %x) {964; CHECK-LABEL: rint_nxv4f16_to_ui64:965; CHECK: # %bb.0:966; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma967; CHECK-NEXT: vfabs.v v9, v8968; CHECK-NEXT: li a0, 25969; CHECK-NEXT: slli a0, a0, 10970; CHECK-NEXT: fmv.h.x fa5, a0971; CHECK-NEXT: vmflt.vf v0, v9, fa5972; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t973; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t974; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu975; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t976; CHECK-NEXT: vfwcvt.f.f.v v12, v8977; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma978; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12979; CHECK-NEXT: ret980; RV32-LABEL: rint_nxv4f16_to_ui64:981; RV32: # %bb.0:982; RV32-NEXT: lui a0, %hi(.LCPI31_0)983; RV32-NEXT: flh fa5, %lo(.LCPI31_0)(a0)984; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma985; RV32-NEXT: vfabs.v v9, v8986; RV32-NEXT: vmflt.vf v0, v9, fa5987; RV32-NEXT: fsrmi a0, 3988; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t989; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t990; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu991; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t992; RV32-NEXT: vfwcvt.f.f.v v12, v8993; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma994; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v12995; RV32-NEXT: fsrm a0996; RV32-NEXT: ret997; RV64-LABEL: rint_nxv4f16_to_ui64:998; RV64: # %bb.0:999; RV64-NEXT: lui a0, %hi(.LCPI31_0)1000; RV64-NEXT: flh fa5, %lo(.LCPI31_0)(a0)1001; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma1002; RV64-NEXT: vfabs.v v9, v81003; RV64-NEXT: vmflt.vf v0, v9, fa51004; RV64-NEXT: fsrmi a0, 31005; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t1006; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t1007; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu1008; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t1009; RV64-NEXT: vfwcvt.f.f.v v12, v81010; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma1011; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v121012; RV64-NEXT: fsrm a01013; RV64-NEXT: ret1014 %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)1015 %b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>1016 ret <vscale x 4 x i64> %b1017}1018