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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v < %s \3; RUN: --verify-machineinstrs | FileCheck %s4 5define <vscale x 1 x i1> @test_1xi1(<vscale x 1 x i1> %in, <vscale x 1 x i1> %in2) nounwind {6; CHECK-LABEL: test_1xi1:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: #APP9; CHECK-NEXT: vmand.mm v0, v0, v810; CHECK-NEXT: #NO_APP11; CHECK-NEXT: ret12entry:13 %0 = tail call <vscale x 1 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i1> %in, <vscale x 1 x i1> %in2)14 ret <vscale x 1 x i1> %015}16 17define <vscale x 2 x i1> @test_2xi1(<vscale x 2 x i1> %in, <vscale x 2 x i1> %in2) nounwind {18; CHECK-LABEL: test_2xi1:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: #APP21; CHECK-NEXT: vmand.mm v0, v0, v822; CHECK-NEXT: #NO_APP23; CHECK-NEXT: ret24entry:25 %0 = tail call <vscale x 2 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i1> %in, <vscale x 2 x i1> %in2)26 ret <vscale x 2 x i1> %027}28 29define <vscale x 4 x i1> @test_4xi1(<vscale x 4 x i1> %in, <vscale x 4 x i1> %in2) nounwind {30; CHECK-LABEL: test_4xi1:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: #APP33; CHECK-NEXT: vmand.mm v0, v0, v834; CHECK-NEXT: #NO_APP35; CHECK-NEXT: ret36entry:37 %0 = tail call <vscale x 4 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i1> %in, <vscale x 4 x i1> %in2)38 ret <vscale x 4 x i1> %039}40 41define <vscale x 8 x i1> @test_8xi1(<vscale x 8 x i1> %in, <vscale x 8 x i1> %in2) nounwind {42; CHECK-LABEL: test_8xi1:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: #APP45; CHECK-NEXT: vmand.mm v0, v0, v846; CHECK-NEXT: #NO_APP47; CHECK-NEXT: ret48entry:49 %0 = tail call <vscale x 8 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 8 x i1> %in, <vscale x 8 x i1> %in2)50 ret <vscale x 8 x i1> %051}52 53define <vscale x 16 x i1> @test_16xi1(<vscale x 16 x i1> %in, <vscale x 16 x i1> %in2) nounwind {54; CHECK-LABEL: test_16xi1:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: #APP57; CHECK-NEXT: vmand.mm v0, v0, v858; CHECK-NEXT: #NO_APP59; CHECK-NEXT: ret60entry:61 %0 = tail call <vscale x 16 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 16 x i1> %in, <vscale x 16 x i1> %in2)62 ret <vscale x 16 x i1> %063}64 65define <vscale x 32 x i1> @test_32xi1(<vscale x 32 x i1> %in, <vscale x 32 x i1> %in2) nounwind {66; CHECK-LABEL: test_32xi1:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: #APP69; CHECK-NEXT: vmand.mm v0, v0, v870; CHECK-NEXT: #NO_APP71; CHECK-NEXT: ret72entry:73 %0 = tail call <vscale x 32 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 32 x i1> %in, <vscale x 32 x i1> %in2)74 ret <vscale x 32 x i1> %075}76 77define <vscale x 64 x i1> @test_64xi1(<vscale x 64 x i1> %in, <vscale x 64 x i1> %in2) nounwind {78; CHECK-LABEL: test_64xi1:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: #APP81; CHECK-NEXT: vmand.mm v0, v0, v882; CHECK-NEXT: #NO_APP83; CHECK-NEXT: ret84entry:85 %0 = tail call <vscale x 64 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 64 x i1> %in, <vscale x 64 x i1> %in2)86 ret <vscale x 64 x i1> %087}88 89define <vscale x 1 x i64> @test_1xi64(<vscale x 1 x i64> %in, <vscale x 1 x i64> %in2) nounwind {90; CHECK-LABEL: test_1xi64:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: #APP93; CHECK-NEXT: vadd.vv v8, v8, v994; CHECK-NEXT: #NO_APP95; CHECK-NEXT: ret96entry:97 %0 = tail call <vscale x 1 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i64> %in, <vscale x 1 x i64> %in2)98 ret <vscale x 1 x i64> %099}100 101define <vscale x 2 x i64> @test_2xi64(<vscale x 2 x i64> %in, <vscale x 2 x i64> %in2) nounwind {102; CHECK-LABEL: test_2xi64:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: #APP105; CHECK-NEXT: vadd.vv v8, v8, v10106; CHECK-NEXT: #NO_APP107; CHECK-NEXT: ret108entry:109 %0 = tail call <vscale x 2 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i64> %in, <vscale x 2 x i64> %in2)110 ret <vscale x 2 x i64> %0111}112 113define <vscale x 4 x i64> @test_4xi64(<vscale x 4 x i64> %in, <vscale x 4 x i64> %in2) nounwind {114; CHECK-LABEL: test_4xi64:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: #APP117; CHECK-NEXT: vadd.vv v8, v8, v12118; CHECK-NEXT: #NO_APP119; CHECK-NEXT: ret120entry:121 %0 = tail call <vscale x 4 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i64> %in, <vscale x 4 x i64> %in2)122 ret <vscale x 4 x i64> %0123}124 125define <vscale x 8 x i64> @test_8xi64(<vscale x 8 x i64> %in, <vscale x 8 x i64> %in2) nounwind {126; CHECK-LABEL: test_8xi64:127; CHECK: # %bb.0: # %entry128; CHECK-NEXT: #APP129; CHECK-NEXT: vadd.vv v8, v8, v16130; CHECK-NEXT: #NO_APP131; CHECK-NEXT: ret132entry:133 %0 = tail call <vscale x 8 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 8 x i64> %in, <vscale x 8 x i64> %in2)134 ret <vscale x 8 x i64> %0135}136 137define <vscale x 1 x i32> @test_1xi32(<vscale x 1 x i32> %in, <vscale x 1 x i32> %in2) nounwind {138; CHECK-LABEL: test_1xi32:139; CHECK: # %bb.0: # %entry140; CHECK-NEXT: #APP141; CHECK-NEXT: vadd.vv v8, v8, v9142; CHECK-NEXT: #NO_APP143; CHECK-NEXT: ret144entry:145 %0 = tail call <vscale x 1 x i32> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i32> %in, <vscale x 1 x i32> %in2)146 ret <vscale x 1 x i32> %0147}148 149define <vscale x 2 x i32> @test_2xi32(<vscale x 2 x i32> %in, <vscale x 2 x i32> %in2) nounwind {150; CHECK-LABEL: test_2xi32:151; CHECK: # %bb.0: # %entry152; CHECK-NEXT: #APP153; CHECK-NEXT: vadd.vv v8, v8, v9154; CHECK-NEXT: #NO_APP155; CHECK-NEXT: ret156entry:157 %0 = tail call <vscale x 2 x i32> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i32> %in, <vscale x 2 x i32> %in2)158 ret <vscale x 2 x i32> %0159}160 161define <vscale x 4 x i32> @test_4xi32(<vscale x 4 x i32> %in, <vscale x 4 x i32> %in2) nounwind {162; CHECK-LABEL: test_4xi32:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: #APP165; CHECK-NEXT: vadd.vv v8, v8, v10166; CHECK-NEXT: #NO_APP167; CHECK-NEXT: ret168entry:169 %0 = tail call <vscale x 4 x i32> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i32> %in, <vscale x 4 x i32> %in2)170 ret <vscale x 4 x i32> %0171}172 173define <vscale x 8 x i32> @test_8xi32(<vscale x 8 x i32> %in, <vscale x 8 x i32> %in2) nounwind {174; CHECK-LABEL: test_8xi32:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: #APP177; CHECK-NEXT: vadd.vv v8, v8, v12178; CHECK-NEXT: #NO_APP179; CHECK-NEXT: ret180entry:181 %0 = tail call <vscale x 8 x i32> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 8 x i32> %in, <vscale x 8 x i32> %in2)182 ret <vscale x 8 x i32> %0183}184 185define <vscale x 16 x i32> @test_16xi32(<vscale x 16 x i32> %in, <vscale x 16 x i32> %in2) nounwind {186; CHECK-LABEL: test_16xi32:187; CHECK: # %bb.0: # %entry188; CHECK-NEXT: #APP189; CHECK-NEXT: vadd.vv v8, v8, v16190; CHECK-NEXT: #NO_APP191; CHECK-NEXT: ret192entry:193 %0 = tail call <vscale x 16 x i32> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 16 x i32> %in, <vscale x 16 x i32> %in2)194 ret <vscale x 16 x i32> %0195}196 197define <vscale x 1 x i16> @test_1xi16(<vscale x 1 x i16> %in, <vscale x 1 x i16> %in2) nounwind {198; CHECK-LABEL: test_1xi16:199; CHECK: # %bb.0: # %entry200; CHECK-NEXT: #APP201; CHECK-NEXT: vadd.vv v8, v8, v9202; CHECK-NEXT: #NO_APP203; CHECK-NEXT: ret204entry:205 %0 = tail call <vscale x 1 x i16> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i16> %in, <vscale x 1 x i16> %in2)206 ret <vscale x 1 x i16> %0207}208 209define <vscale x 2 x i16> @test_2xi16(<vscale x 2 x i16> %in, <vscale x 2 x i16> %in2) nounwind {210; CHECK-LABEL: test_2xi16:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: #APP213; CHECK-NEXT: vadd.vv v8, v8, v9214; CHECK-NEXT: #NO_APP215; CHECK-NEXT: ret216entry:217 %0 = tail call <vscale x 2 x i16> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i16> %in, <vscale x 2 x i16> %in2)218 ret <vscale x 2 x i16> %0219}220 221define <vscale x 4 x i16> @test_4xi16(<vscale x 4 x i16> %in, <vscale x 4 x i16> %in2) nounwind {222; CHECK-LABEL: test_4xi16:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: #APP225; CHECK-NEXT: vadd.vv v8, v8, v9226; CHECK-NEXT: #NO_APP227; CHECK-NEXT: ret228entry:229 %0 = tail call <vscale x 4 x i16> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i16> %in, <vscale x 4 x i16> %in2)230 ret <vscale x 4 x i16> %0231}232 233define <vscale x 8 x i16> @test_8xi16(<vscale x 8 x i16> %in, <vscale x 8 x i16> %in2) nounwind {234; CHECK-LABEL: test_8xi16:235; CHECK: # %bb.0: # %entry236; CHECK-NEXT: #APP237; CHECK-NEXT: vadd.vv v8, v8, v10238; CHECK-NEXT: #NO_APP239; CHECK-NEXT: ret240entry:241 %0 = tail call <vscale x 8 x i16> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 8 x i16> %in, <vscale x 8 x i16> %in2)242 ret <vscale x 8 x i16> %0243}244 245define <vscale x 16 x i16> @test_16xi16(<vscale x 16 x i16> %in, <vscale x 16 x i16> %in2) nounwind {246; CHECK-LABEL: test_16xi16:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: #APP249; CHECK-NEXT: vadd.vv v8, v8, v12250; CHECK-NEXT: #NO_APP251; CHECK-NEXT: ret252entry:253 %0 = tail call <vscale x 16 x i16> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 16 x i16> %in, <vscale x 16 x i16> %in2)254 ret <vscale x 16 x i16> %0255}256 257define <vscale x 32 x i16> @test_32xi16(<vscale x 32 x i16> %in, <vscale x 32 x i16> %in2) nounwind {258; CHECK-LABEL: test_32xi16:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: #APP261; CHECK-NEXT: vadd.vv v8, v8, v16262; CHECK-NEXT: #NO_APP263; CHECK-NEXT: ret264entry:265 %0 = tail call <vscale x 32 x i16> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 32 x i16> %in, <vscale x 32 x i16> %in2)266 ret <vscale x 32 x i16> %0267}268 269define <vscale x 1 x i8> @test_1xi8(<vscale x 1 x i8> %in, <vscale x 1 x i8> %in2) nounwind {270; CHECK-LABEL: test_1xi8:271; CHECK: # %bb.0: # %entry272; CHECK-NEXT: #APP273; CHECK-NEXT: vadd.vv v8, v8, v9274; CHECK-NEXT: #NO_APP275; CHECK-NEXT: ret276entry:277 %0 = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i8> %in, <vscale x 1 x i8> %in2)278 ret <vscale x 1 x i8> %0279}280 281define <vscale x 2 x i8> @test_2xi8(<vscale x 2 x i8> %in, <vscale x 2 x i8> %in2) nounwind {282; CHECK-LABEL: test_2xi8:283; CHECK: # %bb.0: # %entry284; CHECK-NEXT: #APP285; CHECK-NEXT: vadd.vv v8, v8, v9286; CHECK-NEXT: #NO_APP287; CHECK-NEXT: ret288entry:289 %0 = tail call <vscale x 2 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i8> %in, <vscale x 2 x i8> %in2)290 ret <vscale x 2 x i8> %0291}292 293define <vscale x 4 x i8> @test_4xi8(<vscale x 4 x i8> %in, <vscale x 4 x i8> %in2) nounwind {294; CHECK-LABEL: test_4xi8:295; CHECK: # %bb.0: # %entry296; CHECK-NEXT: #APP297; CHECK-NEXT: vadd.vv v8, v8, v9298; CHECK-NEXT: #NO_APP299; CHECK-NEXT: ret300entry:301 %0 = tail call <vscale x 4 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i8> %in, <vscale x 4 x i8> %in2)302 ret <vscale x 4 x i8> %0303}304 305define <vscale x 8 x i8> @test_8xi8(<vscale x 8 x i8> %in, <vscale x 8 x i8> %in2) nounwind {306; CHECK-LABEL: test_8xi8:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: #APP309; CHECK-NEXT: vadd.vv v8, v8, v9310; CHECK-NEXT: #NO_APP311; CHECK-NEXT: ret312entry:313 %0 = tail call <vscale x 8 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 8 x i8> %in, <vscale x 8 x i8> %in2)314 ret <vscale x 8 x i8> %0315}316 317define <vscale x 16 x i8> @test_16xi8(<vscale x 16 x i8> %in, <vscale x 16 x i8> %in2) nounwind {318; CHECK-LABEL: test_16xi8:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: #APP321; CHECK-NEXT: vadd.vv v8, v8, v10322; CHECK-NEXT: #NO_APP323; CHECK-NEXT: ret324entry:325 %0 = tail call <vscale x 16 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 16 x i8> %in, <vscale x 16 x i8> %in2)326 ret <vscale x 16 x i8> %0327}328 329define <vscale x 32 x i8> @test_32xi8(<vscale x 32 x i8> %in, <vscale x 32 x i8> %in2) nounwind {330; CHECK-LABEL: test_32xi8:331; CHECK: # %bb.0: # %entry332; CHECK-NEXT: #APP333; CHECK-NEXT: vadd.vv v8, v8, v12334; CHECK-NEXT: #NO_APP335; CHECK-NEXT: ret336entry:337 %0 = tail call <vscale x 32 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 32 x i8> %in, <vscale x 32 x i8> %in2)338 ret <vscale x 32 x i8> %0339}340 341define <vscale x 64 x i8> @test_64xi8(<vscale x 64 x i8> %in, <vscale x 64 x i8> %in2) nounwind {342; CHECK-LABEL: test_64xi8:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: #APP345; CHECK-NEXT: vadd.vv v8, v8, v16346; CHECK-NEXT: #NO_APP347; CHECK-NEXT: ret348entry:349 %0 = tail call <vscale x 64 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 64 x i8> %in, <vscale x 64 x i8> %in2)350 ret <vscale x 64 x i8> %0351}352 353define <vscale x 64 x i8> @test_64xi8_with_mask(<vscale x 64 x i8> %in, <vscale x 64 x i8> %in2, <vscale x 64 x i1> %mask) nounwind {354; CHECK-LABEL: test_64xi8_with_mask:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: #APP357; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t358; CHECK-NEXT: #NO_APP359; CHECK-NEXT: ret360entry:361 %0 = tail call <vscale x 64 x i8> asm "vadd.vv $0, $1, $2, $3.t", "=^vr,^vr,^vr,^vm"(<vscale x 64 x i8> %in, <vscale x 64 x i8> %in2, <vscale x 64 x i1> %mask)362 ret <vscale x 64 x i8> %0363}364 365define <vscale x 4 x i8> @test_specify_reg_mf2(<vscale x 4 x i8> %in, <vscale x 4 x i8> %in2) nounwind {366; CHECK-LABEL: test_specify_reg_mf2:367; CHECK: # %bb.0: # %entry368; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma369; CHECK-NEXT: vmv1r.v v2, v9370; CHECK-NEXT: vmv1r.v v1, v8371; CHECK-NEXT: #APP372; CHECK-NEXT: vadd.vv v0, v1, v2373; CHECK-NEXT: #NO_APP374; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma375; CHECK-NEXT: vmv1r.v v8, v0376; CHECK-NEXT: ret377entry:378 %0 = tail call <vscale x 4 x i8> asm "vadd.vv $0, $1, $2", "={v0},{v1},{v2}"(<vscale x 4 x i8> %in, <vscale x 4 x i8> %in2)379 ret <vscale x 4 x i8> %0380}381 382define <vscale x 8 x i8> @test_specify_reg_m1(<vscale x 8 x i8> %in, <vscale x 8 x i8> %in2) nounwind {383; CHECK-LABEL: test_specify_reg_m1:384; CHECK: # %bb.0: # %entry385; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma386; CHECK-NEXT: vmv1r.v v2, v9387; CHECK-NEXT: vmv1r.v v1, v8388; CHECK-NEXT: #APP389; CHECK-NEXT: vadd.vv v0, v1, v2390; CHECK-NEXT: #NO_APP391; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma392; CHECK-NEXT: vmv1r.v v8, v0393; CHECK-NEXT: ret394entry:395 %0 = tail call <vscale x 8 x i8> asm "vadd.vv $0, $1, $2", "={v0},{v1},{v2}"(<vscale x 8 x i8> %in, <vscale x 8 x i8> %in2)396 ret <vscale x 8 x i8> %0397}398 399define <vscale x 16 x i8> @test_specify_reg_m2(<vscale x 16 x i8> %in, <vscale x 16 x i8> %in2) nounwind {400; CHECK-LABEL: test_specify_reg_m2:401; CHECK: # %bb.0: # %entry402; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma403; CHECK-NEXT: vmv2r.v v4, v10404; CHECK-NEXT: vmv2r.v v2, v8405; CHECK-NEXT: #APP406; CHECK-NEXT: vadd.vv v0, v2, v4407; CHECK-NEXT: #NO_APP408; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma409; CHECK-NEXT: vmv2r.v v8, v0410; CHECK-NEXT: ret411entry:412 %0 = tail call <vscale x 16 x i8> asm "vadd.vv $0, $1, $2", "={v0},{v2},{v4}"(<vscale x 16 x i8> %in, <vscale x 16 x i8> %in2)413 ret <vscale x 16 x i8> %0414}415 416define <vscale x 1 x i1> @test_specify_reg_mask(<vscale x 1 x i1> %in, <vscale x 1 x i1> %in2) nounwind {417; CHECK-LABEL: test_specify_reg_mask:418; CHECK: # %bb.0: # %entry419; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma420; CHECK-NEXT: vmv1r.v v2, v8421; CHECK-NEXT: vmv1r.v v1, v0422; CHECK-NEXT: #APP423; CHECK-NEXT: vmand.mm v0, v1, v2424; CHECK-NEXT: #NO_APP425; CHECK-NEXT: ret426entry:427 %0 = tail call <vscale x 1 x i1> asm "vmand.mm $0, $1, $2", "={v0},{v1},{v2}"(<vscale x 1 x i1> %in, <vscale x 1 x i1> %in2)428 ret <vscale x 1 x i1> %0429}430 431define void @test_vector_tuple_type0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base) nounwind {432; CHECK-LABEL: test_vector_tuple_type0:433; CHECK: # %bb.0: # %entry434; CHECK-NEXT: #APP435; CHECK-NEXT: vsseg3e8.v v8, (a0)436; CHECK-NEXT: #NO_APP437; CHECK-NEXT: ret438entry:439 tail call void asm "vsseg3e8.v $0, ($1)", "^vr,r"(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base)440 ret void441}442 443define void @test_vector_tuple_type1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base) nounwind {444; CHECK-LABEL: test_vector_tuple_type1:445; CHECK: # %bb.0: # %entry446; CHECK-NEXT: #APP447; CHECK-NEXT: vsseg3e8.v v8, (a0)448; CHECK-NEXT: #NO_APP449; CHECK-NEXT: ret450entry:451 tail call void asm "vsseg3e8.v $0, ($1)", "^vr,r"(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base)452 ret void453}454 455define void @test_vector_tuple_type2(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val3, ptr %base) nounwind {456; CHECK-LABEL: test_vector_tuple_type2:457; CHECK: # %bb.0: # %entry458; CHECK-NEXT: vl1r.v v23, (a0)459; CHECK-NEXT: csrr a2, vlenb460; CHECK-NEXT: add a0, a0, a2461; CHECK-NEXT: vl1r.v v24, (a0)462; CHECK-NEXT: add a0, a0, a2463; CHECK-NEXT: vl1r.v v25, (a0)464; CHECK-NEXT: add a0, a0, a2465; CHECK-NEXT: vl1r.v v26, (a0)466; CHECK-NEXT: add a0, a0, a2467; CHECK-NEXT: vl1r.v v27, (a0)468; CHECK-NEXT: add a0, a0, a2469; CHECK-NEXT: vl1r.v v28, (a0)470; CHECK-NEXT: add a0, a0, a2471; CHECK-NEXT: vl1r.v v29, (a0)472; CHECK-NEXT: #APP473; CHECK-NEXT: vsseg3e8.v v8, (a1)474; CHECK-NEXT: #NO_APP475; CHECK-NEXT: #APP476; CHECK-NEXT: vsseg7e8.v v16, (a1)477; CHECK-NEXT: #NO_APP478; CHECK-NEXT: #APP479; CHECK-NEXT: vsseg7e8.v v23, (a1)480; CHECK-NEXT: #NO_APP481; CHECK-NEXT: ret482entry:483 tail call void asm "vsseg3e8.v $0, ($1)", "^vr,r"(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base)484 tail call void asm "vsseg7e8.v $0, ($1)", "^vr,r"(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val2, ptr %base)485 tail call void asm "vsseg7e8.v $0, ($1)", "^vr,r"(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val3, ptr %base)486 ret void487}488