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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {6; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma9; CHECK-NEXT: vmv2r.v v8, v1210; CHECK-NEXT: ret11 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)12 ret <vscale x 8 x i32> %v13}14 15define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {16; CHECK-LABEL: insert_nxv8i32_nxv4i32_4:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma19; CHECK-NEXT: vmv2r.v v10, v1220; CHECK-NEXT: ret21 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)22 ret <vscale x 8 x i32> %v23}24 25define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {26; CHECK-LABEL: insert_nxv8i32_nxv2i32_0:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma29; CHECK-NEXT: vmv1r.v v8, v1230; CHECK-NEXT: ret31 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)32 ret <vscale x 8 x i32> %v33}34 35define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {36; CHECK-LABEL: insert_nxv8i32_nxv2i32_2:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma39; CHECK-NEXT: vmv1r.v v9, v1240; CHECK-NEXT: ret41 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)42 ret <vscale x 8 x i32> %v43}44 45define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {46; CHECK-LABEL: insert_nxv8i32_nxv2i32_4:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma49; CHECK-NEXT: vmv1r.v v10, v1250; CHECK-NEXT: ret51 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)52 ret <vscale x 8 x i32> %v53}54 55define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {56; CHECK-LABEL: insert_nxv8i32_nxv2i32_6:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma59; CHECK-NEXT: vmv1r.v v11, v1260; CHECK-NEXT: ret61 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)62 ret <vscale x 8 x i32> %v63}64 65define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {66; CHECK-LABEL: insert_nxv1i8_nxv4i8_0:67; CHECK: # %bb.0:68; CHECK-NEXT: csrr a0, vlenb69; CHECK-NEXT: srli a0, a0, 370; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma71; CHECK-NEXT: vmv.v.v v8, v972; CHECK-NEXT: ret73 %v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)74 ret <vscale x 4 x i8> %v75}76 77define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {78; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:79; CHECK: # %bb.0:80; CHECK-NEXT: csrr a0, vlenb81; CHECK-NEXT: srli a1, a0, 382; CHECK-NEXT: srli a0, a0, 283; CHECK-NEXT: add a0, a0, a184; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma85; CHECK-NEXT: vslideup.vx v8, v9, a086; CHECK-NEXT: ret87 %v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)88 ret <vscale x 4 x i8> %v89}90 91define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {92; CHECK-LABEL: insert_nxv16i32_nxv8i32_0:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma95; CHECK-NEXT: vmv4r.v v8, v1696; CHECK-NEXT: ret97 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 0)98 ret <vscale x 16 x i32> %v99}100 101define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {102; CHECK-LABEL: insert_nxv16i32_nxv8i32_8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma105; CHECK-NEXT: vmv4r.v v12, v16106; CHECK-NEXT: ret107 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 8)108 ret <vscale x 16 x i32> %v109}110 111define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {112; CHECK-LABEL: insert_nxv16i32_nxv4i32_0:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma115; CHECK-NEXT: vmv2r.v v8, v16116; CHECK-NEXT: ret117 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)118 ret <vscale x 16 x i32> %v119}120 121define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {122; CHECK-LABEL: insert_nxv16i32_nxv4i32_4:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma125; CHECK-NEXT: vmv2r.v v10, v16126; CHECK-NEXT: ret127 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)128 ret <vscale x 16 x i32> %v129}130 131define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {132; CHECK-LABEL: insert_nxv16i32_nxv4i32_8:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma135; CHECK-NEXT: vmv2r.v v12, v16136; CHECK-NEXT: ret137 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 8)138 ret <vscale x 16 x i32> %v139}140 141define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {142; CHECK-LABEL: insert_nxv16i32_nxv4i32_12:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma145; CHECK-NEXT: vmv2r.v v14, v16146; CHECK-NEXT: ret147 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 12)148 ret <vscale x 16 x i32> %v149}150 151define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {152; CHECK-LABEL: insert_nxv16i32_nxv2i32_0:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma155; CHECK-NEXT: vmv1r.v v8, v16156; CHECK-NEXT: ret157 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)158 ret <vscale x 16 x i32> %v159}160 161define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {162; CHECK-LABEL: insert_nxv16i32_nxv2i32_2:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma165; CHECK-NEXT: vmv1r.v v9, v16166; CHECK-NEXT: ret167 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)168 ret <vscale x 16 x i32> %v169}170 171define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {172; CHECK-LABEL: insert_nxv16i32_nxv2i32_4:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma175; CHECK-NEXT: vmv1r.v v10, v16176; CHECK-NEXT: ret177 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)178 ret <vscale x 16 x i32> %v179}180 181define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {182; CHECK-LABEL: insert_nxv16i32_nxv2i32_6:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma185; CHECK-NEXT: vmv1r.v v11, v16186; CHECK-NEXT: ret187 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)188 ret <vscale x 16 x i32> %v189}190 191define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {192; CHECK-LABEL: insert_nxv16i32_nxv2i32_8:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma195; CHECK-NEXT: vmv1r.v v12, v16196; CHECK-NEXT: ret197 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 8)198 ret <vscale x 16 x i32> %v199}200 201define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {202; CHECK-LABEL: insert_nxv16i32_nxv2i32_10:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma205; CHECK-NEXT: vmv1r.v v13, v16206; CHECK-NEXT: ret207 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 10)208 ret <vscale x 16 x i32> %v209}210 211define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {212; CHECK-LABEL: insert_nxv16i32_nxv2i32_12:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma215; CHECK-NEXT: vmv1r.v v14, v16216; CHECK-NEXT: ret217 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 12)218 ret <vscale x 16 x i32> %v219}220 221define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {222; CHECK-LABEL: insert_nxv16i32_nxv2i32_14:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma225; CHECK-NEXT: vmv1r.v v15, v16226; CHECK-NEXT: ret227 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 14)228 ret <vscale x 16 x i32> %v229}230 231define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {232; CHECK-LABEL: insert_nxv16i32_nxv1i32_0:233; CHECK: # %bb.0:234; CHECK-NEXT: csrr a0, vlenb235; CHECK-NEXT: srli a0, a0, 3236; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma237; CHECK-NEXT: vmv.v.v v8, v16238; CHECK-NEXT: ret239 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0)240 ret <vscale x 16 x i32> %v241}242 243define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {244; CHECK-LABEL: insert_nxv16i32_nxv1i32_1:245; CHECK: # %bb.0:246; CHECK-NEXT: csrr a0, vlenb247; CHECK-NEXT: srli a0, a0, 3248; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma249; CHECK-NEXT: vslideup.vx v8, v16, a0250; CHECK-NEXT: ret251 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1)252 ret <vscale x 16 x i32> %v253}254 255define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {256; CHECK-LABEL: insert_nxv16i32_nxv1i32_6:257; CHECK: # %bb.0:258; CHECK-NEXT: csrr a0, vlenb259; CHECK-NEXT: srli a0, a0, 3260; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma261; CHECK-NEXT: vmv.v.v v11, v16262; CHECK-NEXT: ret263 %v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6)264 ret <vscale x 16 x i32> %v265}266 267define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {268; CHECK-LABEL: insert_nxv16i8_nxv1i8_0:269; CHECK: # %bb.0:270; CHECK-NEXT: csrr a0, vlenb271; CHECK-NEXT: srli a0, a0, 3272; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma273; CHECK-NEXT: vmv.v.v v8, v10274; CHECK-NEXT: ret275 %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)276 ret <vscale x 16 x i8> %v277}278 279define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {280; CHECK-LABEL: insert_nxv16i8_nxv1i8_1:281; CHECK: # %bb.0:282; CHECK-NEXT: csrr a0, vlenb283; CHECK-NEXT: srli a1, a0, 2284; CHECK-NEXT: srli a0, a0, 3285; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma286; CHECK-NEXT: vslideup.vx v8, v10, a0287; CHECK-NEXT: ret288 %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1)289 ret <vscale x 16 x i8> %v290}291 292define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {293; CHECK-LABEL: insert_nxv16i8_nxv1i8_2:294; CHECK: # %bb.0:295; CHECK-NEXT: csrr a0, vlenb296; CHECK-NEXT: srli a1, a0, 3297; CHECK-NEXT: srli a0, a0, 2298; CHECK-NEXT: add a1, a0, a1299; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma300; CHECK-NEXT: vslideup.vx v8, v10, a0301; CHECK-NEXT: ret302 %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2)303 ret <vscale x 16 x i8> %v304}305 306define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {307; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:308; CHECK: # %bb.0:309; CHECK-NEXT: csrr a0, vlenb310; CHECK-NEXT: srli a1, a0, 3311; CHECK-NEXT: srli a2, a0, 2312; CHECK-NEXT: add a1, a2, a1313; CHECK-NEXT: srli a0, a0, 1314; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma315; CHECK-NEXT: vslideup.vx v8, v10, a1316; CHECK-NEXT: ret317 %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)318 ret <vscale x 16 x i8> %v319}320 321define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {322; CHECK-LABEL: insert_nxv16i8_nxv1i8_7:323; CHECK: # %bb.0:324; CHECK-NEXT: csrr a0, vlenb325; CHECK-NEXT: srli a1, a0, 3326; CHECK-NEXT: sub a0, a0, a1327; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma328; CHECK-NEXT: vslideup.vx v8, v10, a0329; CHECK-NEXT: ret330 %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7)331 ret <vscale x 16 x i8> %v332}333 334define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {335; CHECK-LABEL: insert_nxv16i8_nxv1i8_15:336; CHECK: # %bb.0:337; CHECK-NEXT: csrr a0, vlenb338; CHECK-NEXT: srli a1, a0, 3339; CHECK-NEXT: sub a0, a0, a1340; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma341; CHECK-NEXT: vslideup.vx v9, v10, a0342; CHECK-NEXT: ret343 %v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15)344 ret <vscale x 16 x i8> %v345}346 347define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {348; CHECK-LABEL: insert_nxv32f16_nxv2f16_0:349; CHECK: # %bb.0:350; CHECK-NEXT: csrr a0, vlenb351; CHECK-NEXT: srli a0, a0, 2352; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma353; CHECK-NEXT: vmv.v.v v8, v16354; CHECK-NEXT: ret355 %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0)356 ret <vscale x 32 x half> %v357}358 359define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {360; CHECK-LABEL: insert_nxv32f16_nxv2f16_2:361; CHECK: # %bb.0:362; CHECK-NEXT: csrr a0, vlenb363; CHECK-NEXT: srli a0, a0, 2364; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma365; CHECK-NEXT: vslideup.vx v8, v16, a0366; CHECK-NEXT: ret367 %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2)368 ret <vscale x 32 x half> %v369}370 371define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {372; CHECK-LABEL: insert_nxv32f16_nxv2f16_26:373; CHECK: # %bb.0:374; CHECK-NEXT: csrr a0, vlenb375; CHECK-NEXT: srli a0, a0, 2376; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma377; CHECK-NEXT: vslideup.vx v14, v16, a0378; CHECK-NEXT: ret379 %v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)380 ret <vscale x 32 x half> %v381}382 383define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {384; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:385; CHECK: # %bb.0:386; CHECK-NEXT: ret387 %v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> poison, <vscale x 1 x half> %subvec, i64 0)388 ret <vscale x 32 x half> %v389}390 391define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) {392; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26:393; CHECK: # %bb.0:394; CHECK-NEXT: csrr a0, vlenb395; CHECK-NEXT: srli a1, a0, 3396; CHECK-NEXT: srli a0, a0, 2397; CHECK-NEXT: add a1, a0, a1398; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma399; CHECK-NEXT: vslideup.vx v14, v8, a0400; CHECK-NEXT: ret401 %v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> poison, <vscale x 1 x half> %subvec, i64 26)402 ret <vscale x 32 x half> %v403}404 405define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {406; CHECK-LABEL: insert_nxv32i1_nxv8i1_0:407; CHECK: # %bb.0:408; CHECK-NEXT: csrr a0, vlenb409; CHECK-NEXT: srli a0, a0, 3410; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma411; CHECK-NEXT: vmv.v.v v0, v8412; CHECK-NEXT: ret413 %vec = call <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 0)414 ret <vscale x 32 x i1> %vec415}416 417define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_8(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {418; CHECK-LABEL: insert_nxv32i1_nxv8i1_8:419; CHECK: # %bb.0:420; CHECK-NEXT: csrr a0, vlenb421; CHECK-NEXT: srli a1, a0, 2422; CHECK-NEXT: srli a0, a0, 3423; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma424; CHECK-NEXT: vslideup.vx v0, v8, a0425; CHECK-NEXT: ret426 %vec = call <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 8)427 ret <vscale x 32 x i1> %vec428}429 430define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {431; CHECK-LABEL: insert_nxv4i1_nxv1i1_0:432; CHECK: # %bb.0:433; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma434; CHECK-NEXT: vmv.v.i v9, 0435; CHECK-NEXT: vmerge.vim v9, v9, 1, v0436; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma437; CHECK-NEXT: vmv.v.i v10, 0438; CHECK-NEXT: csrr a0, vlenb439; CHECK-NEXT: vmv1r.v v0, v8440; CHECK-NEXT: vmerge.vim v8, v10, 1, v0441; CHECK-NEXT: srli a0, a0, 3442; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma443; CHECK-NEXT: vmv.v.v v9, v8444; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma445; CHECK-NEXT: vmsne.vi v0, v9, 0446; CHECK-NEXT: ret447 %vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0)448 ret <vscale x 4 x i1> %vec449}450 451define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {452; CHECK-LABEL: insert_nxv4i1_nxv1i1_2:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma455; CHECK-NEXT: vmv.v.i v9, 0456; CHECK-NEXT: csrr a0, vlenb457; CHECK-NEXT: vmerge.vim v9, v9, 1, v0458; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma459; CHECK-NEXT: vmv.v.i v10, 0460; CHECK-NEXT: srli a1, a0, 3461; CHECK-NEXT: srli a0, a0, 2462; CHECK-NEXT: add a1, a0, a1463; CHECK-NEXT: vmv1r.v v0, v8464; CHECK-NEXT: vmerge.vim v8, v10, 1, v0465; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma466; CHECK-NEXT: vslideup.vx v9, v8, a0467; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma468; CHECK-NEXT: vmsne.vi v0, v9, 0469; CHECK-NEXT: ret470 %vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)471 ret <vscale x 4 x i1> %vec472}473 474define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, ptr %out) {475; CHECK-LABEL: insert_nxv8i64_nxv16i64:476; CHECK: # %bb.0:477; CHECK-NEXT: vs8r.v v8, (a0)478; CHECK-NEXT: csrr a1, vlenb479; CHECK-NEXT: slli a1, a1, 3480; CHECK-NEXT: add a0, a0, a1481; CHECK-NEXT: vs8r.v v16, (a0)482; CHECK-NEXT: ret483 %v0 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> poison, <vscale x 8 x i64> %sv0, i64 0)484 %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)485 store <vscale x 16 x i64> %v, ptr %out486 ret void487}488 489define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, ptr %out) {490; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:491; CHECK: # %bb.0:492; CHECK-NEXT: vs8r.v v8, (a0)493; CHECK-NEXT: ret494 %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> poison, <vscale x 8 x i64> %sv0, i64 0)495 store <vscale x 16 x i64> %v, ptr %out496 ret void497}498 499define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, ptr %out) {500; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:501; CHECK: # %bb.0:502; CHECK-NEXT: csrr a1, vlenb503; CHECK-NEXT: slli a1, a1, 3504; CHECK-NEXT: add a0, a0, a1505; CHECK-NEXT: vs8r.v v8, (a0)506; CHECK-NEXT: ret507 %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> poison, <vscale x 8 x i64> %sv0, i64 8)508 store <vscale x 16 x i64> %v, ptr %out509 ret void510}511 512; We should be able to widen the <3 x i64> subvector to a <4 x i64> here because513; we know that the minimum vscale is 2514define <vscale x 2 x i64> @insert_nxv2i64_nxv3i64(<3 x i64> %sv) #0 {515; CHECK-LABEL: insert_nxv2i64_nxv3i64:516; CHECK: # %bb.0:517; CHECK-NEXT: ret518 %vec = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v3i64(<vscale x 2 x i64> poison, <3 x i64> %sv, i64 0)519 ret <vscale x 2 x i64> %vec520}521 522; This shows a case where we were miscompiling because the index of the523; outer expects a scalable inner and the inner most subvector is fixed length.524; The code generated happens to be correct if VLEN=128, but is wrong if525; VLEN=256.526define <vscale x 8 x i32> @insert_insert_combine(<2 x i32> %subvec) {527; CHECK-LABEL: insert_insert_combine:528; CHECK: # %bb.0:529; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma530; CHECK-NEXT: vmv1r.v v10, v8531; CHECK-NEXT: ret532 %inner = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v2i32(<vscale x 4 x i32> poison, <2 x i32> %subvec, i64 0)533 %outer = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> %inner, i64 4)534 ret <vscale x 8 x i32> %outer535}536 537; We can combine these two (even with non-zero index on the outer) because538; the vector must be an even multiple.539define <vscale x 8 x i32> @insert_insert_combine2(<vscale x 2 x i32> %subvec) {540; CHECK-LABEL: insert_insert_combine2:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma543; CHECK-NEXT: vmv1r.v v10, v8544; CHECK-NEXT: ret545 %inner = call <vscale x 4 x i32> @llvm.vector.insert.nxv2i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 2 x i32> %subvec, i64 0)546 %outer = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> %inner, i64 4)547 ret <vscale x 8 x i32> %outer548}549 550define <vscale x 32 x bfloat> @insert_nxv32bf16_nxv2bf16_0(<vscale x 32 x bfloat> %vec, <vscale x 2 x bfloat> %subvec) {551; CHECK-LABEL: insert_nxv32bf16_nxv2bf16_0:552; CHECK: # %bb.0:553; CHECK-NEXT: csrr a0, vlenb554; CHECK-NEXT: srli a0, a0, 2555; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma556; CHECK-NEXT: vmv.v.v v8, v16557; CHECK-NEXT: ret558 %v = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %vec, <vscale x 2 x bfloat> %subvec, i64 0)559 ret <vscale x 32 x bfloat> %v560}561 562define <vscale x 32 x bfloat> @insert_nxv32bf16_nxv2bf16_2(<vscale x 32 x bfloat> %vec, <vscale x 2 x bfloat> %subvec) {563; CHECK-LABEL: insert_nxv32bf16_nxv2bf16_2:564; CHECK: # %bb.0:565; CHECK-NEXT: csrr a0, vlenb566; CHECK-NEXT: srli a0, a0, 2567; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma568; CHECK-NEXT: vslideup.vx v8, v16, a0569; CHECK-NEXT: ret570 %v = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %vec, <vscale x 2 x bfloat> %subvec, i64 2)571 ret <vscale x 32 x bfloat> %v572}573 574define <vscale x 32 x bfloat> @insert_nxv32bf16_nxv2bf16_26(<vscale x 32 x bfloat> %vec, <vscale x 2 x bfloat> %subvec) {575; CHECK-LABEL: insert_nxv32bf16_nxv2bf16_26:576; CHECK: # %bb.0:577; CHECK-NEXT: csrr a0, vlenb578; CHECK-NEXT: srli a0, a0, 2579; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma580; CHECK-NEXT: vslideup.vx v14, v16, a0581; CHECK-NEXT: ret582 %v = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %vec, <vscale x 2 x bfloat> %subvec, i64 26)583 ret <vscale x 32 x bfloat> %v584}585 586define <vscale x 32 x bfloat> @insert_nxv32bf16_undef_nxv1bf16_0(<vscale x 1 x bfloat> %subvec) {587; CHECK-LABEL: insert_nxv32bf16_undef_nxv1bf16_0:588; CHECK: # %bb.0:589; CHECK-NEXT: ret590 %v = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %subvec, i64 0)591 ret <vscale x 32 x bfloat> %v592}593 594define <vscale x 32 x bfloat> @insert_nxv32bf16_undef_nxv1bf16_26(<vscale x 1 x bfloat> %subvec) {595; CHECK-LABEL: insert_nxv32bf16_undef_nxv1bf16_26:596; CHECK: # %bb.0:597; CHECK-NEXT: csrr a0, vlenb598; CHECK-NEXT: srli a1, a0, 3599; CHECK-NEXT: srli a0, a0, 2600; CHECK-NEXT: add a1, a0, a1601; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma602; CHECK-NEXT: vslideup.vx v14, v8, a0603; CHECK-NEXT: ret604 %v = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %subvec, i64 26)605 ret <vscale x 32 x bfloat> %v606}607 608define <vscale x 8 x i32> @insert_splat_to_undef() {609; CHECK-LABEL: insert_splat_to_undef:610; CHECK: # %bb.0:611; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma612; CHECK-NEXT: vmv.v.i v8, 1613; CHECK-NEXT: ret614 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> splat (i32 1), i64 0)615 ret <vscale x 8 x i32> %v616}617 618define <vscale x 8 x i32> @insert_splat_to_splat() {619; CHECK-LABEL: insert_splat_to_splat:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma622; CHECK-NEXT: vmv.v.i v8, 1623; CHECK-NEXT: ret624 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 1), i64 0)625 ret <vscale x 8 x i32> %v626}627 628define <vscale x 8 x i32> @insert_splat_to_splat2() {629; CHECK-LABEL: insert_splat_to_splat2:630; CHECK: # %bb.0:631; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma632; CHECK-NEXT: vmv.v.i v12, 1633; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma634; CHECK-NEXT: vmv.v.i v8, 0635; CHECK-NEXT: vmv2r.v v8, v12636; CHECK-NEXT: ret637 %v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> splat (i32 0), <vscale x 4 x i32> splat (i32 1), i64 0)638 ret <vscale x 8 x i32> %v639}640 641attributes #0 = { vscale_range(2,1024) }642 643