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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {6; CHECK-LABEL: insertelt_nxv1i8_0:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma9; CHECK-NEXT: vmv.s.x v8, a010; CHECK-NEXT: ret11 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 012 ret <vscale x 1 x i8> %r13}14 15define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {16; CHECK-LABEL: insertelt_nxv1i8_imm:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, ma19; CHECK-NEXT: vmv.s.x v9, a020; CHECK-NEXT: vslideup.vi v8, v9, 321; CHECK-NEXT: ret22 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 323 ret <vscale x 1 x i8> %r24}25 26define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 zeroext %idx) {27; CHECK-LABEL: insertelt_nxv1i8_idx:28; CHECK: # %bb.0:29; CHECK-NEXT: addi a2, a1, 130; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma31; CHECK-NEXT: vmv.s.x v9, a032; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma33; CHECK-NEXT: vslideup.vx v8, v9, a134; CHECK-NEXT: ret35 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx36 ret <vscale x 1 x i8> %r37}38 39define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {40; CHECK-LABEL: insertelt_nxv2i8_0:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma43; CHECK-NEXT: vmv.s.x v8, a044; CHECK-NEXT: ret45 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 046 ret <vscale x 2 x i8> %r47}48 49define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {50; CHECK-LABEL: insertelt_nxv2i8_imm:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, ma53; CHECK-NEXT: vmv.s.x v9, a054; CHECK-NEXT: vslideup.vi v8, v9, 355; CHECK-NEXT: ret56 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 357 ret <vscale x 2 x i8> %r58}59 60define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 zeroext %idx) {61; CHECK-LABEL: insertelt_nxv2i8_idx:62; CHECK: # %bb.0:63; CHECK-NEXT: addi a2, a1, 164; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma65; CHECK-NEXT: vmv.s.x v9, a066; CHECK-NEXT: vsetvli zero, a2, e8, mf4, tu, ma67; CHECK-NEXT: vslideup.vx v8, v9, a168; CHECK-NEXT: ret69 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx70 ret <vscale x 2 x i8> %r71}72 73define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {74; CHECK-LABEL: insertelt_nxv4i8_0:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma77; CHECK-NEXT: vmv.s.x v8, a078; CHECK-NEXT: ret79 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 080 ret <vscale x 4 x i8> %r81}82 83define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {84; CHECK-LABEL: insertelt_nxv4i8_imm:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma87; CHECK-NEXT: vmv.s.x v9, a088; CHECK-NEXT: vslideup.vi v8, v9, 389; CHECK-NEXT: ret90 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 391 ret <vscale x 4 x i8> %r92}93 94define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 zeroext %idx) {95; CHECK-LABEL: insertelt_nxv4i8_idx:96; CHECK: # %bb.0:97; CHECK-NEXT: addi a2, a1, 198; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma99; CHECK-NEXT: vmv.s.x v9, a0100; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma101; CHECK-NEXT: vslideup.vx v8, v9, a1102; CHECK-NEXT: ret103 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx104 ret <vscale x 4 x i8> %r105}106 107define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {108; CHECK-LABEL: insertelt_nxv8i8_0:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma111; CHECK-NEXT: vmv.s.x v8, a0112; CHECK-NEXT: ret113 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0114 ret <vscale x 8 x i8> %r115}116 117define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {118; CHECK-LABEL: insertelt_nxv8i8_imm:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma121; CHECK-NEXT: vmv.s.x v9, a0122; CHECK-NEXT: vslideup.vi v8, v9, 3123; CHECK-NEXT: ret124 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3125 ret <vscale x 8 x i8> %r126}127 128define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 zeroext %idx) {129; CHECK-LABEL: insertelt_nxv8i8_idx:130; CHECK: # %bb.0:131; CHECK-NEXT: addi a2, a1, 1132; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma133; CHECK-NEXT: vmv.s.x v9, a0134; CHECK-NEXT: vsetvli zero, a2, e8, m1, tu, ma135; CHECK-NEXT: vslideup.vx v8, v9, a1136; CHECK-NEXT: ret137 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx138 ret <vscale x 8 x i8> %r139}140 141define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {142; CHECK-LABEL: insertelt_nxv16i8_0:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma145; CHECK-NEXT: vmv.s.x v8, a0146; CHECK-NEXT: ret147 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0148 ret <vscale x 16 x i8> %r149}150 151define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {152; CHECK-LABEL: insertelt_nxv16i8_imm:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma155; CHECK-NEXT: vmv.s.x v10, a0156; CHECK-NEXT: vslideup.vi v8, v10, 3157; CHECK-NEXT: ret158 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3159 ret <vscale x 16 x i8> %r160}161 162define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 zeroext %idx) {163; CHECK-LABEL: insertelt_nxv16i8_idx:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma166; CHECK-NEXT: vmv.s.x v10, a0167; CHECK-NEXT: addi a0, a1, 1168; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma169; CHECK-NEXT: vslideup.vx v8, v10, a1170; CHECK-NEXT: ret171 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx172 ret <vscale x 16 x i8> %r173}174 175define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {176; CHECK-LABEL: insertelt_nxv32i8_0:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma179; CHECK-NEXT: vmv.s.x v8, a0180; CHECK-NEXT: ret181 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0182 ret <vscale x 32 x i8> %r183}184 185define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {186; CHECK-LABEL: insertelt_nxv32i8_imm:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma189; CHECK-NEXT: vmv.s.x v12, a0190; CHECK-NEXT: vslideup.vi v8, v12, 3191; CHECK-NEXT: ret192 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3193 ret <vscale x 32 x i8> %r194}195 196define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 zeroext %idx) {197; CHECK-LABEL: insertelt_nxv32i8_idx:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma200; CHECK-NEXT: vmv.s.x v12, a0201; CHECK-NEXT: addi a0, a1, 1202; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma203; CHECK-NEXT: vslideup.vx v8, v12, a1204; CHECK-NEXT: ret205 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx206 ret <vscale x 32 x i8> %r207}208 209define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {210; CHECK-LABEL: insertelt_nxv64i8_0:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, ma213; CHECK-NEXT: vmv.s.x v8, a0214; CHECK-NEXT: ret215 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0216 ret <vscale x 64 x i8> %r217}218 219define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {220; CHECK-LABEL: insertelt_nxv64i8_imm:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma223; CHECK-NEXT: vmv.s.x v16, a0224; CHECK-NEXT: vslideup.vi v8, v16, 3225; CHECK-NEXT: ret226 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3227 ret <vscale x 64 x i8> %r228}229 230define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 zeroext %idx) {231; CHECK-LABEL: insertelt_nxv64i8_idx:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma234; CHECK-NEXT: vmv.s.x v16, a0235; CHECK-NEXT: addi a0, a1, 1236; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma237; CHECK-NEXT: vslideup.vx v8, v16, a1238; CHECK-NEXT: ret239 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx240 ret <vscale x 64 x i8> %r241}242 243define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {244; CHECK-LABEL: insertelt_nxv1i16_0:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma247; CHECK-NEXT: vmv.s.x v8, a0248; CHECK-NEXT: ret249 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0250 ret <vscale x 1 x i16> %r251}252 253define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {254; CHECK-LABEL: insertelt_nxv1i16_imm:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, ma257; CHECK-NEXT: vmv.s.x v9, a0258; CHECK-NEXT: vslideup.vi v8, v9, 3259; CHECK-NEXT: ret260 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3261 ret <vscale x 1 x i16> %r262}263 264define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 zeroext %idx) {265; CHECK-LABEL: insertelt_nxv1i16_idx:266; CHECK: # %bb.0:267; CHECK-NEXT: addi a2, a1, 1268; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma269; CHECK-NEXT: vmv.s.x v9, a0270; CHECK-NEXT: vsetvli zero, a2, e16, mf4, tu, ma271; CHECK-NEXT: vslideup.vx v8, v9, a1272; CHECK-NEXT: ret273 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx274 ret <vscale x 1 x i16> %r275}276 277define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {278; CHECK-LABEL: insertelt_nxv2i16_0:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma281; CHECK-NEXT: vmv.s.x v8, a0282; CHECK-NEXT: ret283 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0284 ret <vscale x 2 x i16> %r285}286 287define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {288; CHECK-LABEL: insertelt_nxv2i16_imm:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma291; CHECK-NEXT: vmv.s.x v9, a0292; CHECK-NEXT: vslideup.vi v8, v9, 3293; CHECK-NEXT: ret294 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3295 ret <vscale x 2 x i16> %r296}297 298define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 zeroext %idx) {299; CHECK-LABEL: insertelt_nxv2i16_idx:300; CHECK: # %bb.0:301; CHECK-NEXT: addi a2, a1, 1302; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma303; CHECK-NEXT: vmv.s.x v9, a0304; CHECK-NEXT: vsetvli zero, a2, e16, mf2, tu, ma305; CHECK-NEXT: vslideup.vx v8, v9, a1306; CHECK-NEXT: ret307 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx308 ret <vscale x 2 x i16> %r309}310 311define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {312; CHECK-LABEL: insertelt_nxv4i16_0:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma315; CHECK-NEXT: vmv.s.x v8, a0316; CHECK-NEXT: ret317 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0318 ret <vscale x 4 x i16> %r319}320 321define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {322; CHECK-LABEL: insertelt_nxv4i16_imm:323; CHECK: # %bb.0:324; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma325; CHECK-NEXT: vmv.s.x v9, a0326; CHECK-NEXT: vslideup.vi v8, v9, 3327; CHECK-NEXT: ret328 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3329 ret <vscale x 4 x i16> %r330}331 332define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 zeroext %idx) {333; CHECK-LABEL: insertelt_nxv4i16_idx:334; CHECK: # %bb.0:335; CHECK-NEXT: addi a2, a1, 1336; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma337; CHECK-NEXT: vmv.s.x v9, a0338; CHECK-NEXT: vsetvli zero, a2, e16, m1, tu, ma339; CHECK-NEXT: vslideup.vx v8, v9, a1340; CHECK-NEXT: ret341 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx342 ret <vscale x 4 x i16> %r343}344 345define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {346; CHECK-LABEL: insertelt_nxv8i16_0:347; CHECK: # %bb.0:348; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma349; CHECK-NEXT: vmv.s.x v8, a0350; CHECK-NEXT: ret351 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0352 ret <vscale x 8 x i16> %r353}354 355define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {356; CHECK-LABEL: insertelt_nxv8i16_imm:357; CHECK: # %bb.0:358; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma359; CHECK-NEXT: vmv.s.x v10, a0360; CHECK-NEXT: vslideup.vi v8, v10, 3361; CHECK-NEXT: ret362 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3363 ret <vscale x 8 x i16> %r364}365 366define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 zeroext %idx) {367; CHECK-LABEL: insertelt_nxv8i16_idx:368; CHECK: # %bb.0:369; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma370; CHECK-NEXT: vmv.s.x v10, a0371; CHECK-NEXT: addi a0, a1, 1372; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma373; CHECK-NEXT: vslideup.vx v8, v10, a1374; CHECK-NEXT: ret375 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx376 ret <vscale x 8 x i16> %r377}378 379define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {380; CHECK-LABEL: insertelt_nxv16i16_0:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma383; CHECK-NEXT: vmv.s.x v8, a0384; CHECK-NEXT: ret385 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0386 ret <vscale x 16 x i16> %r387}388 389define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {390; CHECK-LABEL: insertelt_nxv16i16_imm:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma393; CHECK-NEXT: vmv.s.x v12, a0394; CHECK-NEXT: vslideup.vi v8, v12, 3395; CHECK-NEXT: ret396 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3397 ret <vscale x 16 x i16> %r398}399 400define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 zeroext %idx) {401; CHECK-LABEL: insertelt_nxv16i16_idx:402; CHECK: # %bb.0:403; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma404; CHECK-NEXT: vmv.s.x v12, a0405; CHECK-NEXT: addi a0, a1, 1406; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma407; CHECK-NEXT: vslideup.vx v8, v12, a1408; CHECK-NEXT: ret409 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx410 ret <vscale x 16 x i16> %r411}412 413define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {414; CHECK-LABEL: insertelt_nxv32i16_0:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma417; CHECK-NEXT: vmv.s.x v8, a0418; CHECK-NEXT: ret419 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0420 ret <vscale x 32 x i16> %r421}422 423define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {424; CHECK-LABEL: insertelt_nxv32i16_imm:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma427; CHECK-NEXT: vmv.s.x v16, a0428; CHECK-NEXT: vslideup.vi v8, v16, 3429; CHECK-NEXT: ret430 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3431 ret <vscale x 32 x i16> %r432}433 434define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 zeroext %idx) {435; CHECK-LABEL: insertelt_nxv32i16_idx:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma438; CHECK-NEXT: vmv.s.x v16, a0439; CHECK-NEXT: addi a0, a1, 1440; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma441; CHECK-NEXT: vslideup.vx v8, v16, a1442; CHECK-NEXT: ret443 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx444 ret <vscale x 32 x i16> %r445}446 447define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) {448; CHECK-LABEL: insertelt_nxv1i32_0:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma451; CHECK-NEXT: vmv.s.x v8, a0452; CHECK-NEXT: ret453 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0454 ret <vscale x 1 x i32> %r455}456 457define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) {458; CHECK-LABEL: insertelt_nxv1i32_imm:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, ma461; CHECK-NEXT: vmv.s.x v9, a0462; CHECK-NEXT: vslideup.vi v8, v9, 3463; CHECK-NEXT: ret464 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3465 ret <vscale x 1 x i32> %r466}467 468define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 zeroext %idx) {469; CHECK-LABEL: insertelt_nxv1i32_idx:470; CHECK: # %bb.0:471; CHECK-NEXT: addi a2, a1, 1472; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma473; CHECK-NEXT: vmv.s.x v9, a0474; CHECK-NEXT: vsetvli zero, a2, e32, mf2, tu, ma475; CHECK-NEXT: vslideup.vx v8, v9, a1476; CHECK-NEXT: ret477 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx478 ret <vscale x 1 x i32> %r479}480 481define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) {482; CHECK-LABEL: insertelt_nxv2i32_0:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma485; CHECK-NEXT: vmv.s.x v8, a0486; CHECK-NEXT: ret487 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0488 ret <vscale x 2 x i32> %r489}490 491define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) {492; CHECK-LABEL: insertelt_nxv2i32_imm:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma495; CHECK-NEXT: vmv.s.x v9, a0496; CHECK-NEXT: vslideup.vi v8, v9, 3497; CHECK-NEXT: ret498 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3499 ret <vscale x 2 x i32> %r500}501 502define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 zeroext %idx) {503; CHECK-LABEL: insertelt_nxv2i32_idx:504; CHECK: # %bb.0:505; CHECK-NEXT: addi a2, a1, 1506; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma507; CHECK-NEXT: vmv.s.x v9, a0508; CHECK-NEXT: vsetvli zero, a2, e32, m1, tu, ma509; CHECK-NEXT: vslideup.vx v8, v9, a1510; CHECK-NEXT: ret511 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx512 ret <vscale x 2 x i32> %r513}514 515define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) {516; CHECK-LABEL: insertelt_nxv4i32_0:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma519; CHECK-NEXT: vmv.s.x v8, a0520; CHECK-NEXT: ret521 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0522 ret <vscale x 4 x i32> %r523}524 525define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) {526; CHECK-LABEL: insertelt_nxv4i32_imm:527; CHECK: # %bb.0:528; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma529; CHECK-NEXT: vmv.s.x v10, a0530; CHECK-NEXT: vslideup.vi v8, v10, 3531; CHECK-NEXT: ret532 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3533 ret <vscale x 4 x i32> %r534}535 536define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %elt, i32 zeroext %idx) {537; CHECK-LABEL: insertelt_nxv4i32_idx:538; CHECK: # %bb.0:539; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma540; CHECK-NEXT: vmv.s.x v10, a0541; CHECK-NEXT: addi a0, a1, 1542; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma543; CHECK-NEXT: vslideup.vx v8, v10, a1544; CHECK-NEXT: ret545 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx546 ret <vscale x 4 x i32> %r547}548 549define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) {550; CHECK-LABEL: insertelt_nxv8i32_0:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma553; CHECK-NEXT: vmv.s.x v8, a0554; CHECK-NEXT: ret555 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0556 ret <vscale x 8 x i32> %r557}558 559define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) {560; CHECK-LABEL: insertelt_nxv8i32_imm:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma563; CHECK-NEXT: vmv.s.x v12, a0564; CHECK-NEXT: vslideup.vi v8, v12, 3565; CHECK-NEXT: ret566 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3567 ret <vscale x 8 x i32> %r568}569 570define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %elt, i32 zeroext %idx) {571; CHECK-LABEL: insertelt_nxv8i32_idx:572; CHECK: # %bb.0:573; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma574; CHECK-NEXT: vmv.s.x v12, a0575; CHECK-NEXT: addi a0, a1, 1576; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma577; CHECK-NEXT: vslideup.vx v8, v12, a1578; CHECK-NEXT: ret579 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx580 ret <vscale x 8 x i32> %r581}582 583define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) {584; CHECK-LABEL: insertelt_nxv16i32_0:585; CHECK: # %bb.0:586; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, ma587; CHECK-NEXT: vmv.s.x v8, a0588; CHECK-NEXT: ret589 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0590 ret <vscale x 16 x i32> %r591}592 593define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) {594; CHECK-LABEL: insertelt_nxv16i32_imm:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma597; CHECK-NEXT: vmv.s.x v16, a0598; CHECK-NEXT: vslideup.vi v8, v16, 3599; CHECK-NEXT: ret600 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3601 ret <vscale x 16 x i32> %r602}603 604define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %elt, i32 zeroext %idx) {605; CHECK-LABEL: insertelt_nxv16i32_idx:606; CHECK: # %bb.0:607; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma608; CHECK-NEXT: vmv.s.x v16, a0609; CHECK-NEXT: addi a0, a1, 1610; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma611; CHECK-NEXT: vslideup.vx v8, v16, a1612; CHECK-NEXT: ret613 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx614 ret <vscale x 16 x i32> %r615}616 617define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {618; CHECK-LABEL: insertelt_nxv1i64_0:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma621; CHECK-NEXT: vmv.s.x v8, a0622; CHECK-NEXT: ret623 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0624 ret <vscale x 1 x i64> %r625}626 627define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {628; CHECK-LABEL: insertelt_nxv1i64_imm:629; CHECK: # %bb.0:630; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, ma631; CHECK-NEXT: vmv.s.x v9, a0632; CHECK-NEXT: vslideup.vi v8, v9, 3633; CHECK-NEXT: ret634 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3635 ret <vscale x 1 x i64> %r636}637 638define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {639; CHECK-LABEL: insertelt_nxv1i64_idx:640; CHECK: # %bb.0:641; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma642; CHECK-NEXT: vmv.s.x v9, a0643; CHECK-NEXT: slli a1, a1, 32644; CHECK-NEXT: srli a1, a1, 32645; CHECK-NEXT: addi a0, a1, 1646; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma647; CHECK-NEXT: vslideup.vx v8, v9, a1648; CHECK-NEXT: ret649 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx650 ret <vscale x 1 x i64> %r651}652 653define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {654; CHECK-LABEL: insertelt_nxv2i64_0:655; CHECK: # %bb.0:656; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma657; CHECK-NEXT: vmv.s.x v8, a0658; CHECK-NEXT: ret659 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0660 ret <vscale x 2 x i64> %r661}662 663define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {664; CHECK-LABEL: insertelt_nxv2i64_imm:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma667; CHECK-NEXT: vmv.s.x v10, a0668; CHECK-NEXT: vslideup.vi v8, v10, 3669; CHECK-NEXT: ret670 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3671 ret <vscale x 2 x i64> %r672}673 674define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {675; CHECK-LABEL: insertelt_nxv2i64_idx:676; CHECK: # %bb.0:677; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma678; CHECK-NEXT: vmv.s.x v10, a0679; CHECK-NEXT: slli a1, a1, 32680; CHECK-NEXT: srli a1, a1, 32681; CHECK-NEXT: addi a0, a1, 1682; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma683; CHECK-NEXT: vslideup.vx v8, v10, a1684; CHECK-NEXT: ret685 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx686 ret <vscale x 2 x i64> %r687}688 689define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {690; CHECK-LABEL: insertelt_nxv4i64_0:691; CHECK: # %bb.0:692; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma693; CHECK-NEXT: vmv.s.x v8, a0694; CHECK-NEXT: ret695 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0696 ret <vscale x 4 x i64> %r697}698 699define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {700; CHECK-LABEL: insertelt_nxv4i64_imm:701; CHECK: # %bb.0:702; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma703; CHECK-NEXT: vmv.s.x v12, a0704; CHECK-NEXT: vslideup.vi v8, v12, 3705; CHECK-NEXT: ret706 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3707 ret <vscale x 4 x i64> %r708}709 710define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {711; CHECK-LABEL: insertelt_nxv4i64_idx:712; CHECK: # %bb.0:713; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma714; CHECK-NEXT: vmv.s.x v12, a0715; CHECK-NEXT: slli a1, a1, 32716; CHECK-NEXT: srli a1, a1, 32717; CHECK-NEXT: addi a0, a1, 1718; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma719; CHECK-NEXT: vslideup.vx v8, v12, a1720; CHECK-NEXT: ret721 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx722 ret <vscale x 4 x i64> %r723}724 725define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {726; CHECK-LABEL: insertelt_nxv8i64_0:727; CHECK: # %bb.0:728; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, ma729; CHECK-NEXT: vmv.s.x v8, a0730; CHECK-NEXT: ret731 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0732 ret <vscale x 8 x i64> %r733}734 735define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {736; CHECK-LABEL: insertelt_nxv8i64_imm:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma739; CHECK-NEXT: vmv.s.x v16, a0740; CHECK-NEXT: vslideup.vi v8, v16, 3741; CHECK-NEXT: ret742 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3743 ret <vscale x 8 x i64> %r744}745 746define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {747; CHECK-LABEL: insertelt_nxv8i64_idx:748; CHECK: # %bb.0:749; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma750; CHECK-NEXT: vmv.s.x v16, a0751; CHECK-NEXT: slli a1, a1, 32752; CHECK-NEXT: srli a1, a1, 32753; CHECK-NEXT: addi a0, a1, 1754; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma755; CHECK-NEXT: vslideup.vx v8, v16, a1756; CHECK-NEXT: ret757 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx758 ret <vscale x 8 x i64> %r759}760 761define <vscale x 4 x i32> @insertelt_nxv4i32_zeroinitializer_0(i32 %x) {762; CHECK-LABEL: insertelt_nxv4i32_zeroinitializer_0:763; CHECK: # %bb.0:764; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma765; CHECK-NEXT: vmv.v.i v10, 0766; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma767; CHECK-NEXT: vmv.s.x v10, a0768; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma769; CHECK-NEXT: vmv.v.i v8, 0770; CHECK-NEXT: vmv1r.v v8, v10771; CHECK-NEXT: ret772 %v = insertelement <vscale x 4 x i32> zeroinitializer, i32 %x, i64 0773 ret <vscale x 4 x i32> %v774}775 776define <vscale x 4 x i32> @insertelt_imm_nxv4i32_zeroinitializer_0(i32 %x) {777; CHECK-LABEL: insertelt_imm_nxv4i32_zeroinitializer_0:778; CHECK: # %bb.0:779; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma780; CHECK-NEXT: vmv.v.i v10, 0781; CHECK-NEXT: li a0, 42782; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma783; CHECK-NEXT: vmv.s.x v10, a0784; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma785; CHECK-NEXT: vmv.v.i v8, 0786; CHECK-NEXT: vmv1r.v v8, v10787; CHECK-NEXT: ret788 %v = insertelement <vscale x 4 x i32> zeroinitializer, i32 42, i64 0789 ret <vscale x 4 x i32> %v790}791